1 /* 2 * Copyright (C) 2005-2006 Atmel Corporation 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <dm.h> 8 9 /* 10 * The u-boot networking stack is a little weird. It seems like the 11 * networking core allocates receive buffers up front without any 12 * regard to the hardware that's supposed to actually receive those 13 * packets. 14 * 15 * The MACB receives packets into 128-byte receive buffers, so the 16 * buffers allocated by the core isn't very practical to use. We'll 17 * allocate our own, but we need one such buffer in case a packet 18 * wraps around the DMA ring so that we have to copy it. 19 * 20 * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific 21 * configuration header. This way, the core allocates one RX buffer 22 * and one TX buffer, each of which can hold a ethernet packet of 23 * maximum size. 24 * 25 * For some reason, the networking core unconditionally specifies a 26 * 32-byte packet "alignment" (which really should be called 27 * "padding"). MACB shouldn't need that, but we'll refrain from any 28 * core modifications here... 29 */ 30 31 #include <net.h> 32 #ifndef CONFIG_DM_ETH 33 #include <netdev.h> 34 #endif 35 #include <malloc.h> 36 #include <miiphy.h> 37 38 #include <linux/mii.h> 39 #include <asm/io.h> 40 #include <asm/dma-mapping.h> 41 #include <asm/arch/clk.h> 42 #include <asm-generic/errno.h> 43 44 #include "macb.h" 45 46 DECLARE_GLOBAL_DATA_PTR; 47 48 #define MACB_RX_BUFFER_SIZE 4096 49 #define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128) 50 #define MACB_TX_RING_SIZE 16 51 #define MACB_TX_TIMEOUT 1000 52 #define MACB_AUTONEG_TIMEOUT 5000000 53 54 struct macb_dma_desc { 55 u32 addr; 56 u32 ctrl; 57 }; 58 59 #define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc)) 60 #define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE)) 61 #define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE)) 62 #define MACB_TX_DUMMY_DMA_DESC_SIZE (DMA_DESC_BYTES(1)) 63 64 #define RXADDR_USED 0x00000001 65 #define RXADDR_WRAP 0x00000002 66 67 #define RXBUF_FRMLEN_MASK 0x00000fff 68 #define RXBUF_FRAME_START 0x00004000 69 #define RXBUF_FRAME_END 0x00008000 70 #define RXBUF_TYPEID_MATCH 0x00400000 71 #define RXBUF_ADDR4_MATCH 0x00800000 72 #define RXBUF_ADDR3_MATCH 0x01000000 73 #define RXBUF_ADDR2_MATCH 0x02000000 74 #define RXBUF_ADDR1_MATCH 0x04000000 75 #define RXBUF_BROADCAST 0x80000000 76 77 #define TXBUF_FRMLEN_MASK 0x000007ff 78 #define TXBUF_FRAME_END 0x00008000 79 #define TXBUF_NOCRC 0x00010000 80 #define TXBUF_EXHAUSTED 0x08000000 81 #define TXBUF_UNDERRUN 0x10000000 82 #define TXBUF_MAXRETRY 0x20000000 83 #define TXBUF_WRAP 0x40000000 84 #define TXBUF_USED 0x80000000 85 86 struct macb_device { 87 void *regs; 88 89 unsigned int rx_tail; 90 unsigned int tx_head; 91 unsigned int tx_tail; 92 unsigned int next_rx_tail; 93 bool wrapped; 94 95 void *rx_buffer; 96 void *tx_buffer; 97 struct macb_dma_desc *rx_ring; 98 struct macb_dma_desc *tx_ring; 99 100 unsigned long rx_buffer_dma; 101 unsigned long rx_ring_dma; 102 unsigned long tx_ring_dma; 103 104 struct macb_dma_desc *dummy_desc; 105 unsigned long dummy_desc_dma; 106 107 const struct device *dev; 108 #ifndef CONFIG_DM_ETH 109 struct eth_device netdev; 110 #endif 111 unsigned short phy_addr; 112 struct mii_dev *bus; 113 114 #ifdef CONFIG_DM_ETH 115 phy_interface_t phy_interface; 116 #endif 117 }; 118 #ifndef CONFIG_DM_ETH 119 #define to_macb(_nd) container_of(_nd, struct macb_device, netdev) 120 #endif 121 122 static int macb_is_gem(struct macb_device *macb) 123 { 124 return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) == 0x2; 125 } 126 127 #ifndef cpu_is_sama5d2 128 #define cpu_is_sama5d2() 0 129 #endif 130 131 #ifndef cpu_is_sama5d4 132 #define cpu_is_sama5d4() 0 133 #endif 134 135 static int gem_is_gigabit_capable(struct macb_device *macb) 136 { 137 /* 138 * The GEM controllers embedded in SAMA5D2 and SAMA5D4 are 139 * configured to support only 10/100. 140 */ 141 return macb_is_gem(macb) && !cpu_is_sama5d2() && !cpu_is_sama5d4(); 142 } 143 144 static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value) 145 { 146 unsigned long netctl; 147 unsigned long netstat; 148 unsigned long frame; 149 150 netctl = macb_readl(macb, NCR); 151 netctl |= MACB_BIT(MPE); 152 macb_writel(macb, NCR, netctl); 153 154 frame = (MACB_BF(SOF, 1) 155 | MACB_BF(RW, 1) 156 | MACB_BF(PHYA, macb->phy_addr) 157 | MACB_BF(REGA, reg) 158 | MACB_BF(CODE, 2) 159 | MACB_BF(DATA, value)); 160 macb_writel(macb, MAN, frame); 161 162 do { 163 netstat = macb_readl(macb, NSR); 164 } while (!(netstat & MACB_BIT(IDLE))); 165 166 netctl = macb_readl(macb, NCR); 167 netctl &= ~MACB_BIT(MPE); 168 macb_writel(macb, NCR, netctl); 169 } 170 171 static u16 macb_mdio_read(struct macb_device *macb, u8 reg) 172 { 173 unsigned long netctl; 174 unsigned long netstat; 175 unsigned long frame; 176 177 netctl = macb_readl(macb, NCR); 178 netctl |= MACB_BIT(MPE); 179 macb_writel(macb, NCR, netctl); 180 181 frame = (MACB_BF(SOF, 1) 182 | MACB_BF(RW, 2) 183 | MACB_BF(PHYA, macb->phy_addr) 184 | MACB_BF(REGA, reg) 185 | MACB_BF(CODE, 2)); 186 macb_writel(macb, MAN, frame); 187 188 do { 189 netstat = macb_readl(macb, NSR); 190 } while (!(netstat & MACB_BIT(IDLE))); 191 192 frame = macb_readl(macb, MAN); 193 194 netctl = macb_readl(macb, NCR); 195 netctl &= ~MACB_BIT(MPE); 196 macb_writel(macb, NCR, netctl); 197 198 return MACB_BFEXT(DATA, frame); 199 } 200 201 void __weak arch_get_mdio_control(const char *name) 202 { 203 return; 204 } 205 206 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 207 208 int macb_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value) 209 { 210 #ifdef CONFIG_DM_ETH 211 struct udevice *dev = eth_get_dev_by_name(devname); 212 struct macb_device *macb = dev_get_priv(dev); 213 #else 214 struct eth_device *dev = eth_get_dev_by_name(devname); 215 struct macb_device *macb = to_macb(dev); 216 #endif 217 218 if (macb->phy_addr != phy_adr) 219 return -1; 220 221 arch_get_mdio_control(devname); 222 *value = macb_mdio_read(macb, reg); 223 224 return 0; 225 } 226 227 int macb_miiphy_write(const char *devname, u8 phy_adr, u8 reg, u16 value) 228 { 229 #ifdef CONFIG_DM_ETH 230 struct udevice *dev = eth_get_dev_by_name(devname); 231 struct macb_device *macb = dev_get_priv(dev); 232 #else 233 struct eth_device *dev = eth_get_dev_by_name(devname); 234 struct macb_device *macb = to_macb(dev); 235 #endif 236 237 if (macb->phy_addr != phy_adr) 238 return -1; 239 240 arch_get_mdio_control(devname); 241 macb_mdio_write(macb, reg, value); 242 243 return 0; 244 } 245 #endif 246 247 #define RX 1 248 #define TX 0 249 static inline void macb_invalidate_ring_desc(struct macb_device *macb, bool rx) 250 { 251 if (rx) 252 invalidate_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma + 253 MACB_RX_DMA_DESC_SIZE); 254 else 255 invalidate_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma + 256 MACB_TX_DMA_DESC_SIZE); 257 } 258 259 static inline void macb_flush_ring_desc(struct macb_device *macb, bool rx) 260 { 261 if (rx) 262 flush_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma + 263 MACB_RX_DMA_DESC_SIZE); 264 else 265 flush_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma + 266 MACB_TX_DMA_DESC_SIZE); 267 } 268 269 static inline void macb_flush_rx_buffer(struct macb_device *macb) 270 { 271 flush_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma + 272 MACB_RX_BUFFER_SIZE); 273 } 274 275 static inline void macb_invalidate_rx_buffer(struct macb_device *macb) 276 { 277 invalidate_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma + 278 MACB_RX_BUFFER_SIZE); 279 } 280 281 #if defined(CONFIG_CMD_NET) 282 283 static int _macb_send(struct macb_device *macb, const char *name, void *packet, 284 int length) 285 { 286 unsigned long paddr, ctrl; 287 unsigned int tx_head = macb->tx_head; 288 int i; 289 290 paddr = dma_map_single(packet, length, DMA_TO_DEVICE); 291 292 ctrl = length & TXBUF_FRMLEN_MASK; 293 ctrl |= TXBUF_FRAME_END; 294 if (tx_head == (MACB_TX_RING_SIZE - 1)) { 295 ctrl |= TXBUF_WRAP; 296 macb->tx_head = 0; 297 } else { 298 macb->tx_head++; 299 } 300 301 macb->tx_ring[tx_head].ctrl = ctrl; 302 macb->tx_ring[tx_head].addr = paddr; 303 barrier(); 304 macb_flush_ring_desc(macb, TX); 305 /* Do we need check paddr and length is dcache line aligned? */ 306 flush_dcache_range(paddr, paddr + ALIGN(length, ARCH_DMA_MINALIGN)); 307 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART)); 308 309 /* 310 * I guess this is necessary because the networking core may 311 * re-use the transmit buffer as soon as we return... 312 */ 313 for (i = 0; i <= MACB_TX_TIMEOUT; i++) { 314 barrier(); 315 macb_invalidate_ring_desc(macb, TX); 316 ctrl = macb->tx_ring[tx_head].ctrl; 317 if (ctrl & TXBUF_USED) 318 break; 319 udelay(1); 320 } 321 322 dma_unmap_single(packet, length, paddr); 323 324 if (i <= MACB_TX_TIMEOUT) { 325 if (ctrl & TXBUF_UNDERRUN) 326 printf("%s: TX underrun\n", name); 327 if (ctrl & TXBUF_EXHAUSTED) 328 printf("%s: TX buffers exhausted in mid frame\n", name); 329 } else { 330 printf("%s: TX timeout\n", name); 331 } 332 333 /* No one cares anyway */ 334 return 0; 335 } 336 337 static void reclaim_rx_buffers(struct macb_device *macb, 338 unsigned int new_tail) 339 { 340 unsigned int i; 341 342 i = macb->rx_tail; 343 344 macb_invalidate_ring_desc(macb, RX); 345 while (i > new_tail) { 346 macb->rx_ring[i].addr &= ~RXADDR_USED; 347 i++; 348 if (i > MACB_RX_RING_SIZE) 349 i = 0; 350 } 351 352 while (i < new_tail) { 353 macb->rx_ring[i].addr &= ~RXADDR_USED; 354 i++; 355 } 356 357 barrier(); 358 macb_flush_ring_desc(macb, RX); 359 macb->rx_tail = new_tail; 360 } 361 362 static int _macb_recv(struct macb_device *macb, uchar **packetp) 363 { 364 unsigned int next_rx_tail = macb->next_rx_tail; 365 void *buffer; 366 int length; 367 u32 status; 368 369 macb->wrapped = false; 370 for (;;) { 371 macb_invalidate_ring_desc(macb, RX); 372 373 if (!(macb->rx_ring[next_rx_tail].addr & RXADDR_USED)) 374 return -EAGAIN; 375 376 status = macb->rx_ring[next_rx_tail].ctrl; 377 if (status & RXBUF_FRAME_START) { 378 if (next_rx_tail != macb->rx_tail) 379 reclaim_rx_buffers(macb, next_rx_tail); 380 macb->wrapped = false; 381 } 382 383 if (status & RXBUF_FRAME_END) { 384 buffer = macb->rx_buffer + 128 * macb->rx_tail; 385 length = status & RXBUF_FRMLEN_MASK; 386 387 macb_invalidate_rx_buffer(macb); 388 if (macb->wrapped) { 389 unsigned int headlen, taillen; 390 391 headlen = 128 * (MACB_RX_RING_SIZE 392 - macb->rx_tail); 393 taillen = length - headlen; 394 memcpy((void *)net_rx_packets[0], 395 buffer, headlen); 396 memcpy((void *)net_rx_packets[0] + headlen, 397 macb->rx_buffer, taillen); 398 *packetp = (void *)net_rx_packets[0]; 399 } else { 400 *packetp = buffer; 401 } 402 403 if (++next_rx_tail >= MACB_RX_RING_SIZE) 404 next_rx_tail = 0; 405 macb->next_rx_tail = next_rx_tail; 406 return length; 407 } else { 408 if (++next_rx_tail >= MACB_RX_RING_SIZE) { 409 macb->wrapped = true; 410 next_rx_tail = 0; 411 } 412 } 413 barrier(); 414 } 415 } 416 417 static void macb_phy_reset(struct macb_device *macb, const char *name) 418 { 419 int i; 420 u16 status, adv; 421 422 adv = ADVERTISE_CSMA | ADVERTISE_ALL; 423 macb_mdio_write(macb, MII_ADVERTISE, adv); 424 printf("%s: Starting autonegotiation...\n", name); 425 macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE 426 | BMCR_ANRESTART)); 427 428 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) { 429 status = macb_mdio_read(macb, MII_BMSR); 430 if (status & BMSR_ANEGCOMPLETE) 431 break; 432 udelay(100); 433 } 434 435 if (status & BMSR_ANEGCOMPLETE) 436 printf("%s: Autonegotiation complete\n", name); 437 else 438 printf("%s: Autonegotiation timed out (status=0x%04x)\n", 439 name, status); 440 } 441 442 #ifdef CONFIG_MACB_SEARCH_PHY 443 static int macb_phy_find(struct macb_device *macb, const char *name) 444 { 445 int i; 446 u16 phy_id; 447 448 /* Search for PHY... */ 449 for (i = 0; i < 32; i++) { 450 macb->phy_addr = i; 451 phy_id = macb_mdio_read(macb, MII_PHYSID1); 452 if (phy_id != 0xffff) { 453 printf("%s: PHY present at %d\n", name, i); 454 return 1; 455 } 456 } 457 458 /* PHY isn't up to snuff */ 459 printf("%s: PHY not found\n", name); 460 461 return 0; 462 } 463 #endif /* CONFIG_MACB_SEARCH_PHY */ 464 465 #ifdef CONFIG_DM_ETH 466 static int macb_phy_init(struct udevice *dev, const char *name) 467 #else 468 static int macb_phy_init(struct macb_device *macb, const char *name) 469 #endif 470 { 471 #ifdef CONFIG_DM_ETH 472 struct macb_device *macb = dev_get_priv(dev); 473 #endif 474 #ifdef CONFIG_PHYLIB 475 struct phy_device *phydev; 476 #endif 477 u32 ncfgr; 478 u16 phy_id, status, adv, lpa; 479 int media, speed, duplex; 480 int i; 481 482 arch_get_mdio_control(name); 483 #ifdef CONFIG_MACB_SEARCH_PHY 484 /* Auto-detect phy_addr */ 485 if (!macb_phy_find(macb, name)) 486 return 0; 487 #endif /* CONFIG_MACB_SEARCH_PHY */ 488 489 /* Check if the PHY is up to snuff... */ 490 phy_id = macb_mdio_read(macb, MII_PHYSID1); 491 if (phy_id == 0xffff) { 492 printf("%s: No PHY present\n", name); 493 return 0; 494 } 495 496 #ifdef CONFIG_PHYLIB 497 #ifdef CONFIG_DM_ETH 498 phydev = phy_connect(macb->bus, macb->phy_addr, dev, 499 macb->phy_interface); 500 #else 501 /* need to consider other phy interface mode */ 502 phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev, 503 PHY_INTERFACE_MODE_RGMII); 504 #endif 505 if (!phydev) { 506 printf("phy_connect failed\n"); 507 return -ENODEV; 508 } 509 510 phy_config(phydev); 511 #endif 512 513 status = macb_mdio_read(macb, MII_BMSR); 514 if (!(status & BMSR_LSTATUS)) { 515 /* Try to re-negotiate if we don't have link already. */ 516 macb_phy_reset(macb, name); 517 518 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) { 519 status = macb_mdio_read(macb, MII_BMSR); 520 if (status & BMSR_LSTATUS) 521 break; 522 udelay(100); 523 } 524 } 525 526 if (!(status & BMSR_LSTATUS)) { 527 printf("%s: link down (status: 0x%04x)\n", 528 name, status); 529 return 0; 530 } 531 532 /* First check for GMAC and that it is GiB capable */ 533 if (gem_is_gigabit_capable(macb)) { 534 lpa = macb_mdio_read(macb, MII_STAT1000); 535 536 if (lpa & (LPA_1000FULL | LPA_1000HALF)) { 537 duplex = ((lpa & LPA_1000FULL) ? 1 : 0); 538 539 printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n", 540 name, 541 duplex ? "full" : "half", 542 lpa); 543 544 ncfgr = macb_readl(macb, NCFGR); 545 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); 546 ncfgr |= GEM_BIT(GBE); 547 548 if (duplex) 549 ncfgr |= MACB_BIT(FD); 550 551 macb_writel(macb, NCFGR, ncfgr); 552 553 return 1; 554 } 555 } 556 557 /* fall back for EMAC checking */ 558 adv = macb_mdio_read(macb, MII_ADVERTISE); 559 lpa = macb_mdio_read(macb, MII_LPA); 560 media = mii_nway_result(lpa & adv); 561 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) 562 ? 1 : 0); 563 duplex = (media & ADVERTISE_FULL) ? 1 : 0; 564 printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n", 565 name, 566 speed ? "100" : "10", 567 duplex ? "full" : "half", 568 lpa); 569 570 ncfgr = macb_readl(macb, NCFGR); 571 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE)); 572 if (speed) 573 ncfgr |= MACB_BIT(SPD); 574 if (duplex) 575 ncfgr |= MACB_BIT(FD); 576 macb_writel(macb, NCFGR, ncfgr); 577 578 return 1; 579 } 580 581 static int gmac_init_multi_queues(struct macb_device *macb) 582 { 583 int i, num_queues = 1; 584 u32 queue_mask; 585 586 /* bit 0 is never set but queue 0 always exists */ 587 queue_mask = gem_readl(macb, DCFG6) & 0xff; 588 queue_mask |= 0x1; 589 590 for (i = 1; i < MACB_MAX_QUEUES; i++) 591 if (queue_mask & (1 << i)) 592 num_queues++; 593 594 macb->dummy_desc->ctrl = TXBUF_USED; 595 macb->dummy_desc->addr = 0; 596 flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma + 597 MACB_TX_DUMMY_DMA_DESC_SIZE); 598 599 for (i = 1; i < num_queues; i++) 600 gem_writel_queue_TBQP(macb, macb->dummy_desc_dma, i - 1); 601 602 return 0; 603 } 604 605 #ifdef CONFIG_DM_ETH 606 static int _macb_init(struct udevice *dev, const char *name) 607 #else 608 static int _macb_init(struct macb_device *macb, const char *name) 609 #endif 610 { 611 #ifdef CONFIG_DM_ETH 612 struct macb_device *macb = dev_get_priv(dev); 613 #endif 614 unsigned long paddr; 615 int i; 616 617 /* 618 * macb_halt should have been called at some point before now, 619 * so we'll assume the controller is idle. 620 */ 621 622 /* initialize DMA descriptors */ 623 paddr = macb->rx_buffer_dma; 624 for (i = 0; i < MACB_RX_RING_SIZE; i++) { 625 if (i == (MACB_RX_RING_SIZE - 1)) 626 paddr |= RXADDR_WRAP; 627 macb->rx_ring[i].addr = paddr; 628 macb->rx_ring[i].ctrl = 0; 629 paddr += 128; 630 } 631 macb_flush_ring_desc(macb, RX); 632 macb_flush_rx_buffer(macb); 633 634 for (i = 0; i < MACB_TX_RING_SIZE; i++) { 635 macb->tx_ring[i].addr = 0; 636 if (i == (MACB_TX_RING_SIZE - 1)) 637 macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP; 638 else 639 macb->tx_ring[i].ctrl = TXBUF_USED; 640 } 641 macb_flush_ring_desc(macb, TX); 642 643 macb->rx_tail = 0; 644 macb->tx_head = 0; 645 macb->tx_tail = 0; 646 macb->next_rx_tail = 0; 647 648 macb_writel(macb, RBQP, macb->rx_ring_dma); 649 macb_writel(macb, TBQP, macb->tx_ring_dma); 650 651 if (macb_is_gem(macb)) { 652 /* Check the multi queue and initialize the queue for tx */ 653 gmac_init_multi_queues(macb); 654 655 /* 656 * When the GMAC IP with GE feature, this bit is used to 657 * select interface between RGMII and GMII. 658 * When the GMAC IP without GE feature, this bit is used 659 * to select interface between RMII and MII. 660 */ 661 #ifdef CONFIG_DM_ETH 662 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) 663 gem_writel(macb, UR, GEM_BIT(RGMII)); 664 else 665 gem_writel(macb, UR, 0); 666 #else 667 #if defined(CONFIG_RGMII) || defined(CONFIG_RMII) 668 gem_writel(macb, UR, GEM_BIT(RGMII)); 669 #else 670 gem_writel(macb, UR, 0); 671 #endif 672 #endif 673 } else { 674 /* choose RMII or MII mode. This depends on the board */ 675 #ifdef CONFIG_DM_ETH 676 #ifdef CONFIG_AT91FAMILY 677 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) { 678 macb_writel(macb, USRIO, 679 MACB_BIT(RMII) | MACB_BIT(CLKEN)); 680 } else { 681 macb_writel(macb, USRIO, MACB_BIT(CLKEN)); 682 } 683 #else 684 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) 685 macb_writel(macb, USRIO, 0); 686 else 687 macb_writel(macb, USRIO, MACB_BIT(MII)); 688 #endif 689 #else 690 #ifdef CONFIG_RMII 691 #ifdef CONFIG_AT91FAMILY 692 macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN)); 693 #else 694 macb_writel(macb, USRIO, 0); 695 #endif 696 #else 697 #ifdef CONFIG_AT91FAMILY 698 macb_writel(macb, USRIO, MACB_BIT(CLKEN)); 699 #else 700 macb_writel(macb, USRIO, MACB_BIT(MII)); 701 #endif 702 #endif /* CONFIG_RMII */ 703 #endif 704 } 705 706 #ifdef CONFIG_DM_ETH 707 if (!macb_phy_init(dev, name)) 708 #else 709 if (!macb_phy_init(macb, name)) 710 #endif 711 return -1; 712 713 /* Enable TX and RX */ 714 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE)); 715 716 return 0; 717 } 718 719 static void _macb_halt(struct macb_device *macb) 720 { 721 u32 ncr, tsr; 722 723 /* Halt the controller and wait for any ongoing transmission to end. */ 724 ncr = macb_readl(macb, NCR); 725 ncr |= MACB_BIT(THALT); 726 macb_writel(macb, NCR, ncr); 727 728 do { 729 tsr = macb_readl(macb, TSR); 730 } while (tsr & MACB_BIT(TGO)); 731 732 /* Disable TX and RX, and clear statistics */ 733 macb_writel(macb, NCR, MACB_BIT(CLRSTAT)); 734 } 735 736 static int _macb_write_hwaddr(struct macb_device *macb, unsigned char *enetaddr) 737 { 738 u32 hwaddr_bottom; 739 u16 hwaddr_top; 740 741 /* set hardware address */ 742 hwaddr_bottom = enetaddr[0] | enetaddr[1] << 8 | 743 enetaddr[2] << 16 | enetaddr[3] << 24; 744 macb_writel(macb, SA1B, hwaddr_bottom); 745 hwaddr_top = enetaddr[4] | enetaddr[5] << 8; 746 macb_writel(macb, SA1T, hwaddr_top); 747 return 0; 748 } 749 750 static u32 macb_mdc_clk_div(int id, struct macb_device *macb) 751 { 752 u32 config; 753 unsigned long macb_hz = get_macb_pclk_rate(id); 754 755 if (macb_hz < 20000000) 756 config = MACB_BF(CLK, MACB_CLK_DIV8); 757 else if (macb_hz < 40000000) 758 config = MACB_BF(CLK, MACB_CLK_DIV16); 759 else if (macb_hz < 80000000) 760 config = MACB_BF(CLK, MACB_CLK_DIV32); 761 else 762 config = MACB_BF(CLK, MACB_CLK_DIV64); 763 764 return config; 765 } 766 767 static u32 gem_mdc_clk_div(int id, struct macb_device *macb) 768 { 769 u32 config; 770 unsigned long macb_hz = get_macb_pclk_rate(id); 771 772 if (macb_hz < 20000000) 773 config = GEM_BF(CLK, GEM_CLK_DIV8); 774 else if (macb_hz < 40000000) 775 config = GEM_BF(CLK, GEM_CLK_DIV16); 776 else if (macb_hz < 80000000) 777 config = GEM_BF(CLK, GEM_CLK_DIV32); 778 else if (macb_hz < 120000000) 779 config = GEM_BF(CLK, GEM_CLK_DIV48); 780 else if (macb_hz < 160000000) 781 config = GEM_BF(CLK, GEM_CLK_DIV64); 782 else 783 config = GEM_BF(CLK, GEM_CLK_DIV96); 784 785 return config; 786 } 787 788 /* 789 * Get the DMA bus width field of the network configuration register that we 790 * should program. We find the width from decoding the design configuration 791 * register to find the maximum supported data bus width. 792 */ 793 static u32 macb_dbw(struct macb_device *macb) 794 { 795 switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) { 796 case 4: 797 return GEM_BF(DBW, GEM_DBW128); 798 case 2: 799 return GEM_BF(DBW, GEM_DBW64); 800 case 1: 801 default: 802 return GEM_BF(DBW, GEM_DBW32); 803 } 804 } 805 806 static void _macb_eth_initialize(struct macb_device *macb) 807 { 808 int id = 0; /* This is not used by functions we call */ 809 u32 ncfgr; 810 811 /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */ 812 macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE, 813 &macb->rx_buffer_dma); 814 macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE, 815 &macb->rx_ring_dma); 816 macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE, 817 &macb->tx_ring_dma); 818 macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE, 819 &macb->dummy_desc_dma); 820 821 /* 822 * Do some basic initialization so that we at least can talk 823 * to the PHY 824 */ 825 if (macb_is_gem(macb)) { 826 ncfgr = gem_mdc_clk_div(id, macb); 827 ncfgr |= macb_dbw(macb); 828 } else { 829 ncfgr = macb_mdc_clk_div(id, macb); 830 } 831 832 macb_writel(macb, NCFGR, ncfgr); 833 } 834 835 #ifndef CONFIG_DM_ETH 836 static int macb_send(struct eth_device *netdev, void *packet, int length) 837 { 838 struct macb_device *macb = to_macb(netdev); 839 840 return _macb_send(macb, netdev->name, packet, length); 841 } 842 843 static int macb_recv(struct eth_device *netdev) 844 { 845 struct macb_device *macb = to_macb(netdev); 846 uchar *packet; 847 int length; 848 849 macb->wrapped = false; 850 for (;;) { 851 macb->next_rx_tail = macb->rx_tail; 852 length = _macb_recv(macb, &packet); 853 if (length >= 0) { 854 net_process_received_packet(packet, length); 855 reclaim_rx_buffers(macb, macb->next_rx_tail); 856 } else if (length < 0) { 857 return length; 858 } 859 } 860 } 861 862 static int macb_init(struct eth_device *netdev, bd_t *bd) 863 { 864 struct macb_device *macb = to_macb(netdev); 865 866 return _macb_init(macb, netdev->name); 867 } 868 869 static void macb_halt(struct eth_device *netdev) 870 { 871 struct macb_device *macb = to_macb(netdev); 872 873 return _macb_halt(macb); 874 } 875 876 static int macb_write_hwaddr(struct eth_device *netdev) 877 { 878 struct macb_device *macb = to_macb(netdev); 879 880 return _macb_write_hwaddr(macb, netdev->enetaddr); 881 } 882 883 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) 884 { 885 struct macb_device *macb; 886 struct eth_device *netdev; 887 888 macb = malloc(sizeof(struct macb_device)); 889 if (!macb) { 890 printf("Error: Failed to allocate memory for MACB%d\n", id); 891 return -1; 892 } 893 memset(macb, 0, sizeof(struct macb_device)); 894 895 netdev = &macb->netdev; 896 897 macb->regs = regs; 898 macb->phy_addr = phy_addr; 899 900 if (macb_is_gem(macb)) 901 sprintf(netdev->name, "gmac%d", id); 902 else 903 sprintf(netdev->name, "macb%d", id); 904 905 netdev->init = macb_init; 906 netdev->halt = macb_halt; 907 netdev->send = macb_send; 908 netdev->recv = macb_recv; 909 netdev->write_hwaddr = macb_write_hwaddr; 910 911 _macb_eth_initialize(macb); 912 913 eth_register(netdev); 914 915 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 916 miiphy_register(netdev->name, macb_miiphy_read, macb_miiphy_write); 917 macb->bus = miiphy_get_dev_by_name(netdev->name); 918 #endif 919 return 0; 920 } 921 #endif /* !CONFIG_DM_ETH */ 922 923 #ifdef CONFIG_DM_ETH 924 925 static int macb_start(struct udevice *dev) 926 { 927 return _macb_init(dev, dev->name); 928 } 929 930 static int macb_send(struct udevice *dev, void *packet, int length) 931 { 932 struct macb_device *macb = dev_get_priv(dev); 933 934 return _macb_send(macb, dev->name, packet, length); 935 } 936 937 static int macb_recv(struct udevice *dev, int flags, uchar **packetp) 938 { 939 struct macb_device *macb = dev_get_priv(dev); 940 941 macb->next_rx_tail = macb->rx_tail; 942 macb->wrapped = false; 943 944 return _macb_recv(macb, packetp); 945 } 946 947 static int macb_free_pkt(struct udevice *dev, uchar *packet, int length) 948 { 949 struct macb_device *macb = dev_get_priv(dev); 950 951 reclaim_rx_buffers(macb, macb->next_rx_tail); 952 953 return 0; 954 } 955 956 static void macb_stop(struct udevice *dev) 957 { 958 struct macb_device *macb = dev_get_priv(dev); 959 960 _macb_halt(macb); 961 } 962 963 static int macb_write_hwaddr(struct udevice *dev) 964 { 965 struct eth_pdata *plat = dev_get_platdata(dev); 966 struct macb_device *macb = dev_get_priv(dev); 967 968 return _macb_write_hwaddr(macb, plat->enetaddr); 969 } 970 971 static const struct eth_ops macb_eth_ops = { 972 .start = macb_start, 973 .send = macb_send, 974 .recv = macb_recv, 975 .stop = macb_stop, 976 .free_pkt = macb_free_pkt, 977 .write_hwaddr = macb_write_hwaddr, 978 }; 979 980 static int macb_eth_probe(struct udevice *dev) 981 { 982 struct eth_pdata *pdata = dev_get_platdata(dev); 983 struct macb_device *macb = dev_get_priv(dev); 984 985 #ifdef CONFIG_DM_ETH 986 const char *phy_mode; 987 988 phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); 989 if (phy_mode) 990 macb->phy_interface = phy_get_interface_by_name(phy_mode); 991 if (macb->phy_interface == -1) { 992 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 993 return -EINVAL; 994 } 995 #endif 996 997 macb->regs = (void *)pdata->iobase; 998 999 _macb_eth_initialize(macb); 1000 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 1001 miiphy_register(dev->name, macb_miiphy_read, macb_miiphy_write); 1002 macb->bus = miiphy_get_dev_by_name(dev->name); 1003 #endif 1004 1005 return 0; 1006 } 1007 1008 static int macb_eth_ofdata_to_platdata(struct udevice *dev) 1009 { 1010 struct eth_pdata *pdata = dev_get_platdata(dev); 1011 1012 pdata->iobase = dev_get_addr(dev); 1013 return 0; 1014 } 1015 1016 static const struct udevice_id macb_eth_ids[] = { 1017 { .compatible = "cdns,macb" }, 1018 { } 1019 }; 1020 1021 U_BOOT_DRIVER(eth_macb) = { 1022 .name = "eth_macb", 1023 .id = UCLASS_ETH, 1024 .of_match = macb_eth_ids, 1025 .ofdata_to_platdata = macb_eth_ofdata_to_platdata, 1026 .probe = macb_eth_probe, 1027 .ops = &macb_eth_ops, 1028 .priv_auto_alloc_size = sizeof(struct macb_device), 1029 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 1030 }; 1031 #endif 1032 1033 #endif 1034