1 /* 2 * Copyright (C) 2005-2006 Atmel Corporation 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 */ 18 #include <common.h> 19 20 /* 21 * The u-boot networking stack is a little weird. It seems like the 22 * networking core allocates receive buffers up front without any 23 * regard to the hardware that's supposed to actually receive those 24 * packets. 25 * 26 * The MACB receives packets into 128-byte receive buffers, so the 27 * buffers allocated by the core isn't very practical to use. We'll 28 * allocate our own, but we need one such buffer in case a packet 29 * wraps around the DMA ring so that we have to copy it. 30 * 31 * Therefore, define CFG_RX_ETH_BUFFER to 1 in the board-specific 32 * configuration header. This way, the core allocates one RX buffer 33 * and one TX buffer, each of which can hold a ethernet packet of 34 * maximum size. 35 * 36 * For some reason, the networking core unconditionally specifies a 37 * 32-byte packet "alignment" (which really should be called 38 * "padding"). MACB shouldn't need that, but we'll refrain from any 39 * core modifications here... 40 */ 41 42 #include <net.h> 43 #include <malloc.h> 44 45 #include <linux/mii.h> 46 #include <asm/io.h> 47 #include <asm/dma-mapping.h> 48 #include <asm/arch/clk.h> 49 50 #include "macb.h" 51 52 #define barrier() asm volatile("" ::: "memory") 53 54 #define CFG_MACB_RX_BUFFER_SIZE 4096 55 #define CFG_MACB_RX_RING_SIZE (CFG_MACB_RX_BUFFER_SIZE / 128) 56 #define CFG_MACB_TX_RING_SIZE 16 57 #define CFG_MACB_TX_TIMEOUT 1000 58 #define CFG_MACB_AUTONEG_TIMEOUT 5000000 59 60 struct macb_dma_desc { 61 u32 addr; 62 u32 ctrl; 63 }; 64 65 #define RXADDR_USED 0x00000001 66 #define RXADDR_WRAP 0x00000002 67 68 #define RXBUF_FRMLEN_MASK 0x00000fff 69 #define RXBUF_FRAME_START 0x00004000 70 #define RXBUF_FRAME_END 0x00008000 71 #define RXBUF_TYPEID_MATCH 0x00400000 72 #define RXBUF_ADDR4_MATCH 0x00800000 73 #define RXBUF_ADDR3_MATCH 0x01000000 74 #define RXBUF_ADDR2_MATCH 0x02000000 75 #define RXBUF_ADDR1_MATCH 0x04000000 76 #define RXBUF_BROADCAST 0x80000000 77 78 #define TXBUF_FRMLEN_MASK 0x000007ff 79 #define TXBUF_FRAME_END 0x00008000 80 #define TXBUF_NOCRC 0x00010000 81 #define TXBUF_EXHAUSTED 0x08000000 82 #define TXBUF_UNDERRUN 0x10000000 83 #define TXBUF_MAXRETRY 0x20000000 84 #define TXBUF_WRAP 0x40000000 85 #define TXBUF_USED 0x80000000 86 87 struct macb_device { 88 void *regs; 89 90 unsigned int rx_tail; 91 unsigned int tx_head; 92 unsigned int tx_tail; 93 94 void *rx_buffer; 95 void *tx_buffer; 96 struct macb_dma_desc *rx_ring; 97 struct macb_dma_desc *tx_ring; 98 99 unsigned long rx_buffer_dma; 100 unsigned long rx_ring_dma; 101 unsigned long tx_ring_dma; 102 103 const struct device *dev; 104 struct eth_device netdev; 105 unsigned short phy_addr; 106 }; 107 #define to_macb(_nd) container_of(_nd, struct macb_device, netdev) 108 109 static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value) 110 { 111 unsigned long netctl; 112 unsigned long netstat; 113 unsigned long frame; 114 115 netctl = macb_readl(macb, NCR); 116 netctl |= MACB_BIT(MPE); 117 macb_writel(macb, NCR, netctl); 118 119 frame = (MACB_BF(SOF, 1) 120 | MACB_BF(RW, 1) 121 | MACB_BF(PHYA, macb->phy_addr) 122 | MACB_BF(REGA, reg) 123 | MACB_BF(CODE, 2) 124 | MACB_BF(DATA, value)); 125 macb_writel(macb, MAN, frame); 126 127 do { 128 netstat = macb_readl(macb, NSR); 129 } while (!(netstat & MACB_BIT(IDLE))); 130 131 netctl = macb_readl(macb, NCR); 132 netctl &= ~MACB_BIT(MPE); 133 macb_writel(macb, NCR, netctl); 134 } 135 136 static u16 macb_mdio_read(struct macb_device *macb, u8 reg) 137 { 138 unsigned long netctl; 139 unsigned long netstat; 140 unsigned long frame; 141 142 netctl = macb_readl(macb, NCR); 143 netctl |= MACB_BIT(MPE); 144 macb_writel(macb, NCR, netctl); 145 146 frame = (MACB_BF(SOF, 1) 147 | MACB_BF(RW, 2) 148 | MACB_BF(PHYA, macb->phy_addr) 149 | MACB_BF(REGA, reg) 150 | MACB_BF(CODE, 2)); 151 macb_writel(macb, MAN, frame); 152 153 do { 154 netstat = macb_readl(macb, NSR); 155 } while (!(netstat & MACB_BIT(IDLE))); 156 157 frame = macb_readl(macb, MAN); 158 159 netctl = macb_readl(macb, NCR); 160 netctl &= ~MACB_BIT(MPE); 161 macb_writel(macb, NCR, netctl); 162 163 return MACB_BFEXT(DATA, frame); 164 } 165 166 #if defined(CONFIG_CMD_NET) 167 168 static int macb_send(struct eth_device *netdev, volatile void *packet, 169 int length) 170 { 171 struct macb_device *macb = to_macb(netdev); 172 unsigned long paddr, ctrl; 173 unsigned int tx_head = macb->tx_head; 174 int i; 175 176 paddr = dma_map_single(packet, length, DMA_TO_DEVICE); 177 178 ctrl = length & TXBUF_FRMLEN_MASK; 179 ctrl |= TXBUF_FRAME_END; 180 if (tx_head == (CFG_MACB_TX_RING_SIZE - 1)) { 181 ctrl |= TXBUF_WRAP; 182 macb->tx_head = 0; 183 } else 184 macb->tx_head++; 185 186 macb->tx_ring[tx_head].ctrl = ctrl; 187 macb->tx_ring[tx_head].addr = paddr; 188 barrier(); 189 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART)); 190 191 /* 192 * I guess this is necessary because the networking core may 193 * re-use the transmit buffer as soon as we return... 194 */ 195 for (i = 0; i <= CFG_MACB_TX_TIMEOUT; i++) { 196 barrier(); 197 ctrl = macb->tx_ring[tx_head].ctrl; 198 if (ctrl & TXBUF_USED) 199 break; 200 udelay(1); 201 } 202 203 dma_unmap_single(packet, length, paddr); 204 205 if (i <= CFG_MACB_TX_TIMEOUT) { 206 if (ctrl & TXBUF_UNDERRUN) 207 printf("%s: TX underrun\n", netdev->name); 208 if (ctrl & TXBUF_EXHAUSTED) 209 printf("%s: TX buffers exhausted in mid frame\n", 210 netdev->name); 211 } else { 212 printf("%s: TX timeout\n", netdev->name); 213 } 214 215 /* No one cares anyway */ 216 return 0; 217 } 218 219 static void reclaim_rx_buffers(struct macb_device *macb, 220 unsigned int new_tail) 221 { 222 unsigned int i; 223 224 i = macb->rx_tail; 225 while (i > new_tail) { 226 macb->rx_ring[i].addr &= ~RXADDR_USED; 227 i++; 228 if (i > CFG_MACB_RX_RING_SIZE) 229 i = 0; 230 } 231 232 while (i < new_tail) { 233 macb->rx_ring[i].addr &= ~RXADDR_USED; 234 i++; 235 } 236 237 barrier(); 238 macb->rx_tail = new_tail; 239 } 240 241 static int macb_recv(struct eth_device *netdev) 242 { 243 struct macb_device *macb = to_macb(netdev); 244 unsigned int rx_tail = macb->rx_tail; 245 void *buffer; 246 int length; 247 int wrapped = 0; 248 u32 status; 249 250 for (;;) { 251 if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED)) 252 return -1; 253 254 status = macb->rx_ring[rx_tail].ctrl; 255 if (status & RXBUF_FRAME_START) { 256 if (rx_tail != macb->rx_tail) 257 reclaim_rx_buffers(macb, rx_tail); 258 wrapped = 0; 259 } 260 261 if (status & RXBUF_FRAME_END) { 262 buffer = macb->rx_buffer + 128 * macb->rx_tail; 263 length = status & RXBUF_FRMLEN_MASK; 264 if (wrapped) { 265 unsigned int headlen, taillen; 266 267 headlen = 128 * (CFG_MACB_RX_RING_SIZE 268 - macb->rx_tail); 269 taillen = length - headlen; 270 memcpy((void *)NetRxPackets[0], 271 buffer, headlen); 272 memcpy((void *)NetRxPackets[0] + headlen, 273 macb->rx_buffer, taillen); 274 buffer = (void *)NetRxPackets[0]; 275 } 276 277 NetReceive(buffer, length); 278 if (++rx_tail >= CFG_MACB_RX_RING_SIZE) 279 rx_tail = 0; 280 reclaim_rx_buffers(macb, rx_tail); 281 } else { 282 if (++rx_tail >= CFG_MACB_RX_RING_SIZE) { 283 wrapped = 1; 284 rx_tail = 0; 285 } 286 } 287 barrier(); 288 } 289 290 return 0; 291 } 292 293 static void macb_phy_reset(struct macb_device *macb) 294 { 295 struct eth_device *netdev = &macb->netdev; 296 int i; 297 u16 status, adv; 298 299 adv = ADVERTISE_CSMA | ADVERTISE_ALL; 300 macb_mdio_write(macb, MII_ADVERTISE, adv); 301 printf("%s: Starting autonegotiation...\n", netdev->name); 302 macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE 303 | BMCR_ANRESTART)); 304 305 for (i = 0; i < CFG_MACB_AUTONEG_TIMEOUT / 100; i++) { 306 status = macb_mdio_read(macb, MII_BMSR); 307 if (status & BMSR_ANEGCOMPLETE) 308 break; 309 udelay(100); 310 } 311 312 if (status & BMSR_ANEGCOMPLETE) 313 printf("%s: Autonegotiation complete\n", netdev->name); 314 else 315 printf("%s: Autonegotiation timed out (status=0x%04x)\n", 316 netdev->name, status); 317 } 318 319 static int macb_phy_init(struct macb_device *macb) 320 { 321 struct eth_device *netdev = &macb->netdev; 322 u32 ncfgr; 323 u16 phy_id, status, adv, lpa; 324 int media, speed, duplex; 325 int i; 326 327 /* Check if the PHY is up to snuff... */ 328 phy_id = macb_mdio_read(macb, MII_PHYSID1); 329 if (phy_id == 0xffff) { 330 printf("%s: No PHY present\n", netdev->name); 331 return 0; 332 } 333 334 status = macb_mdio_read(macb, MII_BMSR); 335 if (!(status & BMSR_LSTATUS)) { 336 /* Try to re-negotiate if we don't have link already. */ 337 macb_phy_reset(macb); 338 339 for (i = 0; i < CFG_MACB_AUTONEG_TIMEOUT / 100; i++) { 340 status = macb_mdio_read(macb, MII_BMSR); 341 if (status & BMSR_LSTATUS) 342 break; 343 udelay(100); 344 } 345 } 346 347 if (!(status & BMSR_LSTATUS)) { 348 printf("%s: link down (status: 0x%04x)\n", 349 netdev->name, status); 350 return 0; 351 } else { 352 adv = macb_mdio_read(macb, MII_ADVERTISE); 353 lpa = macb_mdio_read(macb, MII_LPA); 354 media = mii_nway_result(lpa & adv); 355 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) 356 ? 1 : 0); 357 duplex = (media & ADVERTISE_FULL) ? 1 : 0; 358 printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n", 359 netdev->name, 360 speed ? "100" : "10", 361 duplex ? "full" : "half", 362 lpa); 363 364 ncfgr = macb_readl(macb, NCFGR); 365 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); 366 if (speed) 367 ncfgr |= MACB_BIT(SPD); 368 if (duplex) 369 ncfgr |= MACB_BIT(FD); 370 macb_writel(macb, NCFGR, ncfgr); 371 return 1; 372 } 373 } 374 375 static int macb_init(struct eth_device *netdev, bd_t *bd) 376 { 377 struct macb_device *macb = to_macb(netdev); 378 unsigned long paddr; 379 u32 hwaddr_bottom; 380 u16 hwaddr_top; 381 int i; 382 383 /* 384 * macb_halt should have been called at some point before now, 385 * so we'll assume the controller is idle. 386 */ 387 388 /* initialize DMA descriptors */ 389 paddr = macb->rx_buffer_dma; 390 for (i = 0; i < CFG_MACB_RX_RING_SIZE; i++) { 391 if (i == (CFG_MACB_RX_RING_SIZE - 1)) 392 paddr |= RXADDR_WRAP; 393 macb->rx_ring[i].addr = paddr; 394 macb->rx_ring[i].ctrl = 0; 395 paddr += 128; 396 } 397 for (i = 0; i < CFG_MACB_TX_RING_SIZE; i++) { 398 macb->tx_ring[i].addr = 0; 399 if (i == (CFG_MACB_TX_RING_SIZE - 1)) 400 macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP; 401 else 402 macb->tx_ring[i].ctrl = TXBUF_USED; 403 } 404 macb->rx_tail = macb->tx_head = macb->tx_tail = 0; 405 406 macb_writel(macb, RBQP, macb->rx_ring_dma); 407 macb_writel(macb, TBQP, macb->tx_ring_dma); 408 409 /* set hardware address */ 410 hwaddr_bottom = cpu_to_le32(*((u32 *)netdev->enetaddr)); 411 macb_writel(macb, SA1B, hwaddr_bottom); 412 hwaddr_top = cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))); 413 macb_writel(macb, SA1T, hwaddr_top); 414 415 /* choose RMII or MII mode. This depends on the board */ 416 #ifdef CONFIG_RMII 417 #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ 418 defined(CONFIG_AT91SAM9263) 419 macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN)); 420 #else 421 macb_writel(macb, USRIO, 0); 422 #endif 423 #else 424 #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ 425 defined(CONFIG_AT91SAM9263) 426 macb_writel(macb, USRIO, MACB_BIT(CLKEN)); 427 #else 428 macb_writel(macb, USRIO, MACB_BIT(MII)); 429 #endif 430 #endif /* CONFIG_RMII */ 431 432 if (!macb_phy_init(macb)) 433 return -1; 434 435 /* Enable TX and RX */ 436 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE)); 437 438 return 0; 439 } 440 441 static void macb_halt(struct eth_device *netdev) 442 { 443 struct macb_device *macb = to_macb(netdev); 444 u32 ncr, tsr; 445 446 /* Halt the controller and wait for any ongoing transmission to end. */ 447 ncr = macb_readl(macb, NCR); 448 ncr |= MACB_BIT(THALT); 449 macb_writel(macb, NCR, ncr); 450 451 do { 452 tsr = macb_readl(macb, TSR); 453 } while (tsr & MACB_BIT(TGO)); 454 455 /* Disable TX and RX, and clear statistics */ 456 macb_writel(macb, NCR, MACB_BIT(CLRSTAT)); 457 } 458 459 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) 460 { 461 struct macb_device *macb; 462 struct eth_device *netdev; 463 unsigned long macb_hz; 464 u32 ncfgr; 465 466 macb = malloc(sizeof(struct macb_device)); 467 if (!macb) { 468 printf("Error: Failed to allocate memory for MACB%d\n", id); 469 return -1; 470 } 471 memset(macb, 0, sizeof(struct macb_device)); 472 473 netdev = &macb->netdev; 474 475 macb->rx_buffer = dma_alloc_coherent(CFG_MACB_RX_BUFFER_SIZE, 476 &macb->rx_buffer_dma); 477 macb->rx_ring = dma_alloc_coherent(CFG_MACB_RX_RING_SIZE 478 * sizeof(struct macb_dma_desc), 479 &macb->rx_ring_dma); 480 macb->tx_ring = dma_alloc_coherent(CFG_MACB_TX_RING_SIZE 481 * sizeof(struct macb_dma_desc), 482 &macb->tx_ring_dma); 483 484 macb->regs = regs; 485 macb->phy_addr = phy_addr; 486 487 sprintf(netdev->name, "macb%d", id); 488 netdev->init = macb_init; 489 netdev->halt = macb_halt; 490 netdev->send = macb_send; 491 netdev->recv = macb_recv; 492 493 /* 494 * Do some basic initialization so that we at least can talk 495 * to the PHY 496 */ 497 macb_hz = get_macb_pclk_rate(id); 498 if (macb_hz < 20000000) 499 ncfgr = MACB_BF(CLK, MACB_CLK_DIV8); 500 else if (macb_hz < 40000000) 501 ncfgr = MACB_BF(CLK, MACB_CLK_DIV16); 502 else if (macb_hz < 80000000) 503 ncfgr = MACB_BF(CLK, MACB_CLK_DIV32); 504 else 505 ncfgr = MACB_BF(CLK, MACB_CLK_DIV64); 506 507 macb_writel(macb, NCFGR, ncfgr); 508 509 eth_register(netdev); 510 511 return 0; 512 } 513 514 #endif 515 516 #if defined(CONFIG_CMD_MII) 517 518 int miiphy_read(unsigned char addr, unsigned char reg, unsigned short *value) 519 { 520 unsigned long netctl; 521 unsigned long netstat; 522 unsigned long frame; 523 int iflag; 524 525 iflag = disable_interrupts(); 526 netctl = macb_readl(&macb, EMACB_NCR); 527 netctl |= MACB_BIT(MPE); 528 macb_writel(&macb, EMACB_NCR, netctl); 529 if (iflag) 530 enable_interrupts(); 531 532 frame = (MACB_BF(SOF, 1) 533 | MACB_BF(RW, 2) 534 | MACB_BF(PHYA, addr) 535 | MACB_BF(REGA, reg) 536 | MACB_BF(CODE, 2)); 537 macb_writel(&macb, EMACB_MAN, frame); 538 539 do { 540 netstat = macb_readl(&macb, EMACB_NSR); 541 } while (!(netstat & MACB_BIT(IDLE))); 542 543 frame = macb_readl(&macb, EMACB_MAN); 544 *value = MACB_BFEXT(DATA, frame); 545 546 iflag = disable_interrupts(); 547 netctl = macb_readl(&macb, EMACB_NCR); 548 netctl &= ~MACB_BIT(MPE); 549 macb_writel(&macb, EMACB_NCR, netctl); 550 if (iflag) 551 enable_interrupts(); 552 553 return 0; 554 } 555 556 int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value) 557 { 558 unsigned long netctl; 559 unsigned long netstat; 560 unsigned long frame; 561 int iflag; 562 563 iflag = disable_interrupts(); 564 netctl = macb_readl(&macb, EMACB_NCR); 565 netctl |= MACB_BIT(MPE); 566 macb_writel(&macb, EMACB_NCR, netctl); 567 if (iflag) 568 enable_interrupts(); 569 570 frame = (MACB_BF(SOF, 1) 571 | MACB_BF(RW, 1) 572 | MACB_BF(PHYA, addr) 573 | MACB_BF(REGA, reg) 574 | MACB_BF(CODE, 2) 575 | MACB_BF(DATA, value)); 576 macb_writel(&macb, EMACB_MAN, frame); 577 578 do { 579 netstat = macb_readl(&macb, EMACB_NSR); 580 } while (!(netstat & MACB_BIT(IDLE))); 581 582 iflag = disable_interrupts(); 583 netctl = macb_readl(&macb, EMACB_NCR); 584 netctl &= ~MACB_BIT(MPE); 585 macb_writel(&macb, EMACB_NCR, netctl); 586 if (iflag) 587 enable_interrupts(); 588 589 return 0; 590 } 591 592 #endif 593