1 /* 2 * Copyright (C) 2005-2006 Atmel Corporation 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <clk.h> 8 #include <dm.h> 9 10 /* 11 * The u-boot networking stack is a little weird. It seems like the 12 * networking core allocates receive buffers up front without any 13 * regard to the hardware that's supposed to actually receive those 14 * packets. 15 * 16 * The MACB receives packets into 128-byte receive buffers, so the 17 * buffers allocated by the core isn't very practical to use. We'll 18 * allocate our own, but we need one such buffer in case a packet 19 * wraps around the DMA ring so that we have to copy it. 20 * 21 * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific 22 * configuration header. This way, the core allocates one RX buffer 23 * and one TX buffer, each of which can hold a ethernet packet of 24 * maximum size. 25 * 26 * For some reason, the networking core unconditionally specifies a 27 * 32-byte packet "alignment" (which really should be called 28 * "padding"). MACB shouldn't need that, but we'll refrain from any 29 * core modifications here... 30 */ 31 32 #include <net.h> 33 #ifndef CONFIG_DM_ETH 34 #include <netdev.h> 35 #endif 36 #include <malloc.h> 37 #include <miiphy.h> 38 39 #include <linux/mii.h> 40 #include <asm/io.h> 41 #include <asm/dma-mapping.h> 42 #include <asm/arch/clk.h> 43 #include <linux/errno.h> 44 45 #include "macb.h" 46 47 DECLARE_GLOBAL_DATA_PTR; 48 49 #define MACB_RX_BUFFER_SIZE 4096 50 #define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128) 51 #define MACB_TX_RING_SIZE 16 52 #define MACB_TX_TIMEOUT 1000 53 #define MACB_AUTONEG_TIMEOUT 5000000 54 55 struct macb_dma_desc { 56 u32 addr; 57 u32 ctrl; 58 }; 59 60 #define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc)) 61 #define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE)) 62 #define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE)) 63 #define MACB_TX_DUMMY_DMA_DESC_SIZE (DMA_DESC_BYTES(1)) 64 65 #define RXADDR_USED 0x00000001 66 #define RXADDR_WRAP 0x00000002 67 68 #define RXBUF_FRMLEN_MASK 0x00000fff 69 #define RXBUF_FRAME_START 0x00004000 70 #define RXBUF_FRAME_END 0x00008000 71 #define RXBUF_TYPEID_MATCH 0x00400000 72 #define RXBUF_ADDR4_MATCH 0x00800000 73 #define RXBUF_ADDR3_MATCH 0x01000000 74 #define RXBUF_ADDR2_MATCH 0x02000000 75 #define RXBUF_ADDR1_MATCH 0x04000000 76 #define RXBUF_BROADCAST 0x80000000 77 78 #define TXBUF_FRMLEN_MASK 0x000007ff 79 #define TXBUF_FRAME_END 0x00008000 80 #define TXBUF_NOCRC 0x00010000 81 #define TXBUF_EXHAUSTED 0x08000000 82 #define TXBUF_UNDERRUN 0x10000000 83 #define TXBUF_MAXRETRY 0x20000000 84 #define TXBUF_WRAP 0x40000000 85 #define TXBUF_USED 0x80000000 86 87 struct macb_device { 88 void *regs; 89 90 unsigned int rx_tail; 91 unsigned int tx_head; 92 unsigned int tx_tail; 93 unsigned int next_rx_tail; 94 bool wrapped; 95 96 void *rx_buffer; 97 void *tx_buffer; 98 struct macb_dma_desc *rx_ring; 99 struct macb_dma_desc *tx_ring; 100 101 unsigned long rx_buffer_dma; 102 unsigned long rx_ring_dma; 103 unsigned long tx_ring_dma; 104 105 struct macb_dma_desc *dummy_desc; 106 unsigned long dummy_desc_dma; 107 108 const struct device *dev; 109 #ifndef CONFIG_DM_ETH 110 struct eth_device netdev; 111 #endif 112 unsigned short phy_addr; 113 struct mii_dev *bus; 114 115 #ifdef CONFIG_DM_ETH 116 unsigned long pclk_rate; 117 phy_interface_t phy_interface; 118 #endif 119 }; 120 #ifndef CONFIG_DM_ETH 121 #define to_macb(_nd) container_of(_nd, struct macb_device, netdev) 122 #endif 123 124 static int macb_is_gem(struct macb_device *macb) 125 { 126 return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) == 0x2; 127 } 128 129 #ifndef cpu_is_sama5d2 130 #define cpu_is_sama5d2() 0 131 #endif 132 133 #ifndef cpu_is_sama5d4 134 #define cpu_is_sama5d4() 0 135 #endif 136 137 static int gem_is_gigabit_capable(struct macb_device *macb) 138 { 139 /* 140 * The GEM controllers embedded in SAMA5D2 and SAMA5D4 are 141 * configured to support only 10/100. 142 */ 143 return macb_is_gem(macb) && !cpu_is_sama5d2() && !cpu_is_sama5d4(); 144 } 145 146 static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value) 147 { 148 unsigned long netctl; 149 unsigned long netstat; 150 unsigned long frame; 151 152 netctl = macb_readl(macb, NCR); 153 netctl |= MACB_BIT(MPE); 154 macb_writel(macb, NCR, netctl); 155 156 frame = (MACB_BF(SOF, 1) 157 | MACB_BF(RW, 1) 158 | MACB_BF(PHYA, macb->phy_addr) 159 | MACB_BF(REGA, reg) 160 | MACB_BF(CODE, 2) 161 | MACB_BF(DATA, value)); 162 macb_writel(macb, MAN, frame); 163 164 do { 165 netstat = macb_readl(macb, NSR); 166 } while (!(netstat & MACB_BIT(IDLE))); 167 168 netctl = macb_readl(macb, NCR); 169 netctl &= ~MACB_BIT(MPE); 170 macb_writel(macb, NCR, netctl); 171 } 172 173 static u16 macb_mdio_read(struct macb_device *macb, u8 reg) 174 { 175 unsigned long netctl; 176 unsigned long netstat; 177 unsigned long frame; 178 179 netctl = macb_readl(macb, NCR); 180 netctl |= MACB_BIT(MPE); 181 macb_writel(macb, NCR, netctl); 182 183 frame = (MACB_BF(SOF, 1) 184 | MACB_BF(RW, 2) 185 | MACB_BF(PHYA, macb->phy_addr) 186 | MACB_BF(REGA, reg) 187 | MACB_BF(CODE, 2)); 188 macb_writel(macb, MAN, frame); 189 190 do { 191 netstat = macb_readl(macb, NSR); 192 } while (!(netstat & MACB_BIT(IDLE))); 193 194 frame = macb_readl(macb, MAN); 195 196 netctl = macb_readl(macb, NCR); 197 netctl &= ~MACB_BIT(MPE); 198 macb_writel(macb, NCR, netctl); 199 200 return MACB_BFEXT(DATA, frame); 201 } 202 203 void __weak arch_get_mdio_control(const char *name) 204 { 205 return; 206 } 207 208 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 209 210 int macb_miiphy_read(struct mii_dev *bus, int phy_adr, int devad, int reg) 211 { 212 u16 value = 0; 213 #ifdef CONFIG_DM_ETH 214 struct udevice *dev = eth_get_dev_by_name(bus->name); 215 struct macb_device *macb = dev_get_priv(dev); 216 #else 217 struct eth_device *dev = eth_get_dev_by_name(bus->name); 218 struct macb_device *macb = to_macb(dev); 219 #endif 220 221 if (macb->phy_addr != phy_adr) 222 return -1; 223 224 arch_get_mdio_control(bus->name); 225 value = macb_mdio_read(macb, reg); 226 227 return value; 228 } 229 230 int macb_miiphy_write(struct mii_dev *bus, int phy_adr, int devad, int reg, 231 u16 value) 232 { 233 #ifdef CONFIG_DM_ETH 234 struct udevice *dev = eth_get_dev_by_name(bus->name); 235 struct macb_device *macb = dev_get_priv(dev); 236 #else 237 struct eth_device *dev = eth_get_dev_by_name(bus->name); 238 struct macb_device *macb = to_macb(dev); 239 #endif 240 241 if (macb->phy_addr != phy_adr) 242 return -1; 243 244 arch_get_mdio_control(bus->name); 245 macb_mdio_write(macb, reg, value); 246 247 return 0; 248 } 249 #endif 250 251 #define RX 1 252 #define TX 0 253 static inline void macb_invalidate_ring_desc(struct macb_device *macb, bool rx) 254 { 255 if (rx) 256 invalidate_dcache_range(macb->rx_ring_dma, 257 ALIGN(macb->rx_ring_dma + MACB_RX_DMA_DESC_SIZE, 258 PKTALIGN)); 259 else 260 invalidate_dcache_range(macb->tx_ring_dma, 261 ALIGN(macb->tx_ring_dma + MACB_TX_DMA_DESC_SIZE, 262 PKTALIGN)); 263 } 264 265 static inline void macb_flush_ring_desc(struct macb_device *macb, bool rx) 266 { 267 if (rx) 268 flush_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma + 269 ALIGN(MACB_RX_DMA_DESC_SIZE, PKTALIGN)); 270 else 271 flush_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma + 272 ALIGN(MACB_TX_DMA_DESC_SIZE, PKTALIGN)); 273 } 274 275 static inline void macb_flush_rx_buffer(struct macb_device *macb) 276 { 277 flush_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma + 278 ALIGN(MACB_RX_BUFFER_SIZE, PKTALIGN)); 279 } 280 281 static inline void macb_invalidate_rx_buffer(struct macb_device *macb) 282 { 283 invalidate_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma + 284 ALIGN(MACB_RX_BUFFER_SIZE, PKTALIGN)); 285 } 286 287 #if defined(CONFIG_CMD_NET) 288 289 static int _macb_send(struct macb_device *macb, const char *name, void *packet, 290 int length) 291 { 292 unsigned long paddr, ctrl; 293 unsigned int tx_head = macb->tx_head; 294 int i; 295 296 paddr = dma_map_single(packet, length, DMA_TO_DEVICE); 297 298 ctrl = length & TXBUF_FRMLEN_MASK; 299 ctrl |= TXBUF_FRAME_END; 300 if (tx_head == (MACB_TX_RING_SIZE - 1)) { 301 ctrl |= TXBUF_WRAP; 302 macb->tx_head = 0; 303 } else { 304 macb->tx_head++; 305 } 306 307 macb->tx_ring[tx_head].ctrl = ctrl; 308 macb->tx_ring[tx_head].addr = paddr; 309 barrier(); 310 macb_flush_ring_desc(macb, TX); 311 /* Do we need check paddr and length is dcache line aligned? */ 312 flush_dcache_range(paddr, paddr + ALIGN(length, ARCH_DMA_MINALIGN)); 313 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART)); 314 315 /* 316 * I guess this is necessary because the networking core may 317 * re-use the transmit buffer as soon as we return... 318 */ 319 for (i = 0; i <= MACB_TX_TIMEOUT; i++) { 320 barrier(); 321 macb_invalidate_ring_desc(macb, TX); 322 ctrl = macb->tx_ring[tx_head].ctrl; 323 if (ctrl & TXBUF_USED) 324 break; 325 udelay(1); 326 } 327 328 dma_unmap_single(packet, length, paddr); 329 330 if (i <= MACB_TX_TIMEOUT) { 331 if (ctrl & TXBUF_UNDERRUN) 332 printf("%s: TX underrun\n", name); 333 if (ctrl & TXBUF_EXHAUSTED) 334 printf("%s: TX buffers exhausted in mid frame\n", name); 335 } else { 336 printf("%s: TX timeout\n", name); 337 } 338 339 /* No one cares anyway */ 340 return 0; 341 } 342 343 static void reclaim_rx_buffers(struct macb_device *macb, 344 unsigned int new_tail) 345 { 346 unsigned int i; 347 348 i = macb->rx_tail; 349 350 macb_invalidate_ring_desc(macb, RX); 351 while (i > new_tail) { 352 macb->rx_ring[i].addr &= ~RXADDR_USED; 353 i++; 354 if (i > MACB_RX_RING_SIZE) 355 i = 0; 356 } 357 358 while (i < new_tail) { 359 macb->rx_ring[i].addr &= ~RXADDR_USED; 360 i++; 361 } 362 363 barrier(); 364 macb_flush_ring_desc(macb, RX); 365 macb->rx_tail = new_tail; 366 } 367 368 static int _macb_recv(struct macb_device *macb, uchar **packetp) 369 { 370 unsigned int next_rx_tail = macb->next_rx_tail; 371 void *buffer; 372 int length; 373 u32 status; 374 375 macb->wrapped = false; 376 for (;;) { 377 macb_invalidate_ring_desc(macb, RX); 378 379 if (!(macb->rx_ring[next_rx_tail].addr & RXADDR_USED)) 380 return -EAGAIN; 381 382 status = macb->rx_ring[next_rx_tail].ctrl; 383 if (status & RXBUF_FRAME_START) { 384 if (next_rx_tail != macb->rx_tail) 385 reclaim_rx_buffers(macb, next_rx_tail); 386 macb->wrapped = false; 387 } 388 389 if (status & RXBUF_FRAME_END) { 390 buffer = macb->rx_buffer + 128 * macb->rx_tail; 391 length = status & RXBUF_FRMLEN_MASK; 392 393 macb_invalidate_rx_buffer(macb); 394 if (macb->wrapped) { 395 unsigned int headlen, taillen; 396 397 headlen = 128 * (MACB_RX_RING_SIZE 398 - macb->rx_tail); 399 taillen = length - headlen; 400 memcpy((void *)net_rx_packets[0], 401 buffer, headlen); 402 memcpy((void *)net_rx_packets[0] + headlen, 403 macb->rx_buffer, taillen); 404 *packetp = (void *)net_rx_packets[0]; 405 } else { 406 *packetp = buffer; 407 } 408 409 if (++next_rx_tail >= MACB_RX_RING_SIZE) 410 next_rx_tail = 0; 411 macb->next_rx_tail = next_rx_tail; 412 return length; 413 } else { 414 if (++next_rx_tail >= MACB_RX_RING_SIZE) { 415 macb->wrapped = true; 416 next_rx_tail = 0; 417 } 418 } 419 barrier(); 420 } 421 } 422 423 static void macb_phy_reset(struct macb_device *macb, const char *name) 424 { 425 int i; 426 u16 status, adv; 427 428 adv = ADVERTISE_CSMA | ADVERTISE_ALL; 429 macb_mdio_write(macb, MII_ADVERTISE, adv); 430 printf("%s: Starting autonegotiation...\n", name); 431 macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE 432 | BMCR_ANRESTART)); 433 434 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) { 435 status = macb_mdio_read(macb, MII_BMSR); 436 if (status & BMSR_ANEGCOMPLETE) 437 break; 438 udelay(100); 439 } 440 441 if (status & BMSR_ANEGCOMPLETE) 442 printf("%s: Autonegotiation complete\n", name); 443 else 444 printf("%s: Autonegotiation timed out (status=0x%04x)\n", 445 name, status); 446 } 447 448 #ifdef CONFIG_MACB_SEARCH_PHY 449 static int macb_phy_find(struct macb_device *macb, const char *name) 450 { 451 int i; 452 u16 phy_id; 453 454 /* Search for PHY... */ 455 for (i = 0; i < 32; i++) { 456 macb->phy_addr = i; 457 phy_id = macb_mdio_read(macb, MII_PHYSID1); 458 if (phy_id != 0xffff) { 459 printf("%s: PHY present at %d\n", name, i); 460 return 1; 461 } 462 } 463 464 /* PHY isn't up to snuff */ 465 printf("%s: PHY not found\n", name); 466 467 return 0; 468 } 469 #endif /* CONFIG_MACB_SEARCH_PHY */ 470 471 #ifdef CONFIG_DM_ETH 472 static int macb_phy_init(struct udevice *dev, const char *name) 473 #else 474 static int macb_phy_init(struct macb_device *macb, const char *name) 475 #endif 476 { 477 #ifdef CONFIG_DM_ETH 478 struct macb_device *macb = dev_get_priv(dev); 479 #endif 480 #ifdef CONFIG_PHYLIB 481 struct phy_device *phydev; 482 #endif 483 u32 ncfgr; 484 u16 phy_id, status, adv, lpa; 485 int media, speed, duplex; 486 int i; 487 488 arch_get_mdio_control(name); 489 #ifdef CONFIG_MACB_SEARCH_PHY 490 /* Auto-detect phy_addr */ 491 if (!macb_phy_find(macb, name)) 492 return 0; 493 #endif /* CONFIG_MACB_SEARCH_PHY */ 494 495 /* Check if the PHY is up to snuff... */ 496 phy_id = macb_mdio_read(macb, MII_PHYSID1); 497 if (phy_id == 0xffff) { 498 printf("%s: No PHY present\n", name); 499 return 0; 500 } 501 502 #ifdef CONFIG_PHYLIB 503 #ifdef CONFIG_DM_ETH 504 phydev = phy_connect(macb->bus, macb->phy_addr, dev, 505 macb->phy_interface); 506 #else 507 /* need to consider other phy interface mode */ 508 phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev, 509 PHY_INTERFACE_MODE_RGMII); 510 #endif 511 if (!phydev) { 512 printf("phy_connect failed\n"); 513 return -ENODEV; 514 } 515 516 phy_config(phydev); 517 #endif 518 519 status = macb_mdio_read(macb, MII_BMSR); 520 if (!(status & BMSR_LSTATUS)) { 521 /* Try to re-negotiate if we don't have link already. */ 522 macb_phy_reset(macb, name); 523 524 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) { 525 status = macb_mdio_read(macb, MII_BMSR); 526 if (status & BMSR_LSTATUS) 527 break; 528 udelay(100); 529 } 530 } 531 532 if (!(status & BMSR_LSTATUS)) { 533 printf("%s: link down (status: 0x%04x)\n", 534 name, status); 535 return 0; 536 } 537 538 /* First check for GMAC and that it is GiB capable */ 539 if (gem_is_gigabit_capable(macb)) { 540 lpa = macb_mdio_read(macb, MII_STAT1000); 541 542 if (lpa & (LPA_1000FULL | LPA_1000HALF)) { 543 duplex = ((lpa & LPA_1000FULL) ? 1 : 0); 544 545 printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n", 546 name, 547 duplex ? "full" : "half", 548 lpa); 549 550 ncfgr = macb_readl(macb, NCFGR); 551 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); 552 ncfgr |= GEM_BIT(GBE); 553 554 if (duplex) 555 ncfgr |= MACB_BIT(FD); 556 557 macb_writel(macb, NCFGR, ncfgr); 558 559 return 1; 560 } 561 } 562 563 /* fall back for EMAC checking */ 564 adv = macb_mdio_read(macb, MII_ADVERTISE); 565 lpa = macb_mdio_read(macb, MII_LPA); 566 media = mii_nway_result(lpa & adv); 567 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) 568 ? 1 : 0); 569 duplex = (media & ADVERTISE_FULL) ? 1 : 0; 570 printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n", 571 name, 572 speed ? "100" : "10", 573 duplex ? "full" : "half", 574 lpa); 575 576 ncfgr = macb_readl(macb, NCFGR); 577 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE)); 578 if (speed) 579 ncfgr |= MACB_BIT(SPD); 580 if (duplex) 581 ncfgr |= MACB_BIT(FD); 582 macb_writel(macb, NCFGR, ncfgr); 583 584 return 1; 585 } 586 587 static int gmac_init_multi_queues(struct macb_device *macb) 588 { 589 int i, num_queues = 1; 590 u32 queue_mask; 591 592 /* bit 0 is never set but queue 0 always exists */ 593 queue_mask = gem_readl(macb, DCFG6) & 0xff; 594 queue_mask |= 0x1; 595 596 for (i = 1; i < MACB_MAX_QUEUES; i++) 597 if (queue_mask & (1 << i)) 598 num_queues++; 599 600 macb->dummy_desc->ctrl = TXBUF_USED; 601 macb->dummy_desc->addr = 0; 602 flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma + 603 ALIGN(MACB_TX_DUMMY_DMA_DESC_SIZE, PKTALIGN)); 604 605 for (i = 1; i < num_queues; i++) 606 gem_writel_queue_TBQP(macb, macb->dummy_desc_dma, i - 1); 607 608 return 0; 609 } 610 611 #ifdef CONFIG_DM_ETH 612 static int _macb_init(struct udevice *dev, const char *name) 613 #else 614 static int _macb_init(struct macb_device *macb, const char *name) 615 #endif 616 { 617 #ifdef CONFIG_DM_ETH 618 struct macb_device *macb = dev_get_priv(dev); 619 #endif 620 unsigned long paddr; 621 int i; 622 623 /* 624 * macb_halt should have been called at some point before now, 625 * so we'll assume the controller is idle. 626 */ 627 628 /* initialize DMA descriptors */ 629 paddr = macb->rx_buffer_dma; 630 for (i = 0; i < MACB_RX_RING_SIZE; i++) { 631 if (i == (MACB_RX_RING_SIZE - 1)) 632 paddr |= RXADDR_WRAP; 633 macb->rx_ring[i].addr = paddr; 634 macb->rx_ring[i].ctrl = 0; 635 paddr += 128; 636 } 637 macb_flush_ring_desc(macb, RX); 638 macb_flush_rx_buffer(macb); 639 640 for (i = 0; i < MACB_TX_RING_SIZE; i++) { 641 macb->tx_ring[i].addr = 0; 642 if (i == (MACB_TX_RING_SIZE - 1)) 643 macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP; 644 else 645 macb->tx_ring[i].ctrl = TXBUF_USED; 646 } 647 macb_flush_ring_desc(macb, TX); 648 649 macb->rx_tail = 0; 650 macb->tx_head = 0; 651 macb->tx_tail = 0; 652 macb->next_rx_tail = 0; 653 654 macb_writel(macb, RBQP, macb->rx_ring_dma); 655 macb_writel(macb, TBQP, macb->tx_ring_dma); 656 657 if (macb_is_gem(macb)) { 658 /* Check the multi queue and initialize the queue for tx */ 659 gmac_init_multi_queues(macb); 660 661 /* 662 * When the GMAC IP with GE feature, this bit is used to 663 * select interface between RGMII and GMII. 664 * When the GMAC IP without GE feature, this bit is used 665 * to select interface between RMII and MII. 666 */ 667 #ifdef CONFIG_DM_ETH 668 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) 669 gem_writel(macb, UR, GEM_BIT(RGMII)); 670 else 671 gem_writel(macb, UR, 0); 672 #else 673 #if defined(CONFIG_RGMII) || defined(CONFIG_RMII) 674 gem_writel(macb, UR, GEM_BIT(RGMII)); 675 #else 676 gem_writel(macb, UR, 0); 677 #endif 678 #endif 679 } else { 680 /* choose RMII or MII mode. This depends on the board */ 681 #ifdef CONFIG_DM_ETH 682 #ifdef CONFIG_AT91FAMILY 683 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) { 684 macb_writel(macb, USRIO, 685 MACB_BIT(RMII) | MACB_BIT(CLKEN)); 686 } else { 687 macb_writel(macb, USRIO, MACB_BIT(CLKEN)); 688 } 689 #else 690 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) 691 macb_writel(macb, USRIO, 0); 692 else 693 macb_writel(macb, USRIO, MACB_BIT(MII)); 694 #endif 695 #else 696 #ifdef CONFIG_RMII 697 #ifdef CONFIG_AT91FAMILY 698 macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN)); 699 #else 700 macb_writel(macb, USRIO, 0); 701 #endif 702 #else 703 #ifdef CONFIG_AT91FAMILY 704 macb_writel(macb, USRIO, MACB_BIT(CLKEN)); 705 #else 706 macb_writel(macb, USRIO, MACB_BIT(MII)); 707 #endif 708 #endif /* CONFIG_RMII */ 709 #endif 710 } 711 712 #ifdef CONFIG_DM_ETH 713 if (!macb_phy_init(dev, name)) 714 #else 715 if (!macb_phy_init(macb, name)) 716 #endif 717 return -1; 718 719 /* Enable TX and RX */ 720 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE)); 721 722 return 0; 723 } 724 725 static void _macb_halt(struct macb_device *macb) 726 { 727 u32 ncr, tsr; 728 729 /* Halt the controller and wait for any ongoing transmission to end. */ 730 ncr = macb_readl(macb, NCR); 731 ncr |= MACB_BIT(THALT); 732 macb_writel(macb, NCR, ncr); 733 734 do { 735 tsr = macb_readl(macb, TSR); 736 } while (tsr & MACB_BIT(TGO)); 737 738 /* Disable TX and RX, and clear statistics */ 739 macb_writel(macb, NCR, MACB_BIT(CLRSTAT)); 740 } 741 742 static int _macb_write_hwaddr(struct macb_device *macb, unsigned char *enetaddr) 743 { 744 u32 hwaddr_bottom; 745 u16 hwaddr_top; 746 747 /* set hardware address */ 748 hwaddr_bottom = enetaddr[0] | enetaddr[1] << 8 | 749 enetaddr[2] << 16 | enetaddr[3] << 24; 750 macb_writel(macb, SA1B, hwaddr_bottom); 751 hwaddr_top = enetaddr[4] | enetaddr[5] << 8; 752 macb_writel(macb, SA1T, hwaddr_top); 753 return 0; 754 } 755 756 static u32 macb_mdc_clk_div(int id, struct macb_device *macb) 757 { 758 u32 config; 759 #ifdef CONFIG_DM_ETH 760 unsigned long macb_hz = macb->pclk_rate; 761 #else 762 unsigned long macb_hz = get_macb_pclk_rate(id); 763 #endif 764 765 if (macb_hz < 20000000) 766 config = MACB_BF(CLK, MACB_CLK_DIV8); 767 else if (macb_hz < 40000000) 768 config = MACB_BF(CLK, MACB_CLK_DIV16); 769 else if (macb_hz < 80000000) 770 config = MACB_BF(CLK, MACB_CLK_DIV32); 771 else 772 config = MACB_BF(CLK, MACB_CLK_DIV64); 773 774 return config; 775 } 776 777 static u32 gem_mdc_clk_div(int id, struct macb_device *macb) 778 { 779 u32 config; 780 781 #ifdef CONFIG_DM_ETH 782 unsigned long macb_hz = macb->pclk_rate; 783 #else 784 unsigned long macb_hz = get_macb_pclk_rate(id); 785 #endif 786 787 if (macb_hz < 20000000) 788 config = GEM_BF(CLK, GEM_CLK_DIV8); 789 else if (macb_hz < 40000000) 790 config = GEM_BF(CLK, GEM_CLK_DIV16); 791 else if (macb_hz < 80000000) 792 config = GEM_BF(CLK, GEM_CLK_DIV32); 793 else if (macb_hz < 120000000) 794 config = GEM_BF(CLK, GEM_CLK_DIV48); 795 else if (macb_hz < 160000000) 796 config = GEM_BF(CLK, GEM_CLK_DIV64); 797 else 798 config = GEM_BF(CLK, GEM_CLK_DIV96); 799 800 return config; 801 } 802 803 /* 804 * Get the DMA bus width field of the network configuration register that we 805 * should program. We find the width from decoding the design configuration 806 * register to find the maximum supported data bus width. 807 */ 808 static u32 macb_dbw(struct macb_device *macb) 809 { 810 switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) { 811 case 4: 812 return GEM_BF(DBW, GEM_DBW128); 813 case 2: 814 return GEM_BF(DBW, GEM_DBW64); 815 case 1: 816 default: 817 return GEM_BF(DBW, GEM_DBW32); 818 } 819 } 820 821 static void _macb_eth_initialize(struct macb_device *macb) 822 { 823 int id = 0; /* This is not used by functions we call */ 824 u32 ncfgr; 825 826 /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */ 827 macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE, 828 &macb->rx_buffer_dma); 829 macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE, 830 &macb->rx_ring_dma); 831 macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE, 832 &macb->tx_ring_dma); 833 macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE, 834 &macb->dummy_desc_dma); 835 836 /* 837 * Do some basic initialization so that we at least can talk 838 * to the PHY 839 */ 840 if (macb_is_gem(macb)) { 841 ncfgr = gem_mdc_clk_div(id, macb); 842 ncfgr |= macb_dbw(macb); 843 } else { 844 ncfgr = macb_mdc_clk_div(id, macb); 845 } 846 847 macb_writel(macb, NCFGR, ncfgr); 848 } 849 850 #ifndef CONFIG_DM_ETH 851 static int macb_send(struct eth_device *netdev, void *packet, int length) 852 { 853 struct macb_device *macb = to_macb(netdev); 854 855 return _macb_send(macb, netdev->name, packet, length); 856 } 857 858 static int macb_recv(struct eth_device *netdev) 859 { 860 struct macb_device *macb = to_macb(netdev); 861 uchar *packet; 862 int length; 863 864 macb->wrapped = false; 865 for (;;) { 866 macb->next_rx_tail = macb->rx_tail; 867 length = _macb_recv(macb, &packet); 868 if (length >= 0) { 869 net_process_received_packet(packet, length); 870 reclaim_rx_buffers(macb, macb->next_rx_tail); 871 } else if (length < 0) { 872 return length; 873 } 874 } 875 } 876 877 static int macb_init(struct eth_device *netdev, bd_t *bd) 878 { 879 struct macb_device *macb = to_macb(netdev); 880 881 return _macb_init(macb, netdev->name); 882 } 883 884 static void macb_halt(struct eth_device *netdev) 885 { 886 struct macb_device *macb = to_macb(netdev); 887 888 return _macb_halt(macb); 889 } 890 891 static int macb_write_hwaddr(struct eth_device *netdev) 892 { 893 struct macb_device *macb = to_macb(netdev); 894 895 return _macb_write_hwaddr(macb, netdev->enetaddr); 896 } 897 898 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) 899 { 900 struct macb_device *macb; 901 struct eth_device *netdev; 902 903 macb = malloc(sizeof(struct macb_device)); 904 if (!macb) { 905 printf("Error: Failed to allocate memory for MACB%d\n", id); 906 return -1; 907 } 908 memset(macb, 0, sizeof(struct macb_device)); 909 910 netdev = &macb->netdev; 911 912 macb->regs = regs; 913 macb->phy_addr = phy_addr; 914 915 if (macb_is_gem(macb)) 916 sprintf(netdev->name, "gmac%d", id); 917 else 918 sprintf(netdev->name, "macb%d", id); 919 920 netdev->init = macb_init; 921 netdev->halt = macb_halt; 922 netdev->send = macb_send; 923 netdev->recv = macb_recv; 924 netdev->write_hwaddr = macb_write_hwaddr; 925 926 _macb_eth_initialize(macb); 927 928 eth_register(netdev); 929 930 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 931 int retval; 932 struct mii_dev *mdiodev = mdio_alloc(); 933 if (!mdiodev) 934 return -ENOMEM; 935 strncpy(mdiodev->name, netdev->name, MDIO_NAME_LEN); 936 mdiodev->read = macb_miiphy_read; 937 mdiodev->write = macb_miiphy_write; 938 939 retval = mdio_register(mdiodev); 940 if (retval < 0) 941 return retval; 942 macb->bus = miiphy_get_dev_by_name(netdev->name); 943 #endif 944 return 0; 945 } 946 #endif /* !CONFIG_DM_ETH */ 947 948 #ifdef CONFIG_DM_ETH 949 950 static int macb_start(struct udevice *dev) 951 { 952 return _macb_init(dev, dev->name); 953 } 954 955 static int macb_send(struct udevice *dev, void *packet, int length) 956 { 957 struct macb_device *macb = dev_get_priv(dev); 958 959 return _macb_send(macb, dev->name, packet, length); 960 } 961 962 static int macb_recv(struct udevice *dev, int flags, uchar **packetp) 963 { 964 struct macb_device *macb = dev_get_priv(dev); 965 966 macb->next_rx_tail = macb->rx_tail; 967 macb->wrapped = false; 968 969 return _macb_recv(macb, packetp); 970 } 971 972 static int macb_free_pkt(struct udevice *dev, uchar *packet, int length) 973 { 974 struct macb_device *macb = dev_get_priv(dev); 975 976 reclaim_rx_buffers(macb, macb->next_rx_tail); 977 978 return 0; 979 } 980 981 static void macb_stop(struct udevice *dev) 982 { 983 struct macb_device *macb = dev_get_priv(dev); 984 985 _macb_halt(macb); 986 } 987 988 static int macb_write_hwaddr(struct udevice *dev) 989 { 990 struct eth_pdata *plat = dev_get_platdata(dev); 991 struct macb_device *macb = dev_get_priv(dev); 992 993 return _macb_write_hwaddr(macb, plat->enetaddr); 994 } 995 996 static const struct eth_ops macb_eth_ops = { 997 .start = macb_start, 998 .send = macb_send, 999 .recv = macb_recv, 1000 .stop = macb_stop, 1001 .free_pkt = macb_free_pkt, 1002 .write_hwaddr = macb_write_hwaddr, 1003 }; 1004 1005 static int macb_enable_clk(struct udevice *dev) 1006 { 1007 struct macb_device *macb = dev_get_priv(dev); 1008 struct clk clk; 1009 ulong clk_rate; 1010 int ret; 1011 1012 ret = clk_get_by_index(dev, 0, &clk); 1013 if (ret) 1014 return -EINVAL; 1015 1016 ret = clk_enable(&clk); 1017 if (ret) 1018 return ret; 1019 1020 clk_rate = clk_get_rate(&clk); 1021 if (!clk_rate) 1022 return -EINVAL; 1023 1024 macb->pclk_rate = clk_rate; 1025 1026 return 0; 1027 } 1028 1029 static int macb_eth_probe(struct udevice *dev) 1030 { 1031 struct eth_pdata *pdata = dev_get_platdata(dev); 1032 struct macb_device *macb = dev_get_priv(dev); 1033 const char *phy_mode; 1034 int ret; 1035 1036 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", 1037 NULL); 1038 if (phy_mode) 1039 macb->phy_interface = phy_get_interface_by_name(phy_mode); 1040 if (macb->phy_interface == -1) { 1041 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 1042 return -EINVAL; 1043 } 1044 1045 macb->regs = (void *)pdata->iobase; 1046 1047 ret = macb_enable_clk(dev); 1048 if (ret) 1049 return ret; 1050 1051 _macb_eth_initialize(macb); 1052 1053 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 1054 int retval; 1055 struct mii_dev *mdiodev = mdio_alloc(); 1056 if (!mdiodev) 1057 return -ENOMEM; 1058 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); 1059 mdiodev->read = macb_miiphy_read; 1060 mdiodev->write = macb_miiphy_write; 1061 1062 retval = mdio_register(mdiodev); 1063 if (retval < 0) 1064 return retval; 1065 macb->bus = miiphy_get_dev_by_name(dev->name); 1066 #endif 1067 1068 return 0; 1069 } 1070 1071 static int macb_eth_ofdata_to_platdata(struct udevice *dev) 1072 { 1073 struct eth_pdata *pdata = dev_get_platdata(dev); 1074 1075 pdata->iobase = dev_get_addr(dev); 1076 return 0; 1077 } 1078 1079 static const struct udevice_id macb_eth_ids[] = { 1080 { .compatible = "cdns,macb" }, 1081 { } 1082 }; 1083 1084 U_BOOT_DRIVER(eth_macb) = { 1085 .name = "eth_macb", 1086 .id = UCLASS_ETH, 1087 .of_match = macb_eth_ids, 1088 .ofdata_to_platdata = macb_eth_ofdata_to_platdata, 1089 .probe = macb_eth_probe, 1090 .ops = &macb_eth_ops, 1091 .priv_auto_alloc_size = sizeof(struct macb_device), 1092 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 1093 }; 1094 #endif 1095 1096 #endif 1097