1 /* 2 * Copyright (C) 2005-2006 Atmel Corporation 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 */ 18 #include <common.h> 19 20 /* 21 * The u-boot networking stack is a little weird. It seems like the 22 * networking core allocates receive buffers up front without any 23 * regard to the hardware that's supposed to actually receive those 24 * packets. 25 * 26 * The MACB receives packets into 128-byte receive buffers, so the 27 * buffers allocated by the core isn't very practical to use. We'll 28 * allocate our own, but we need one such buffer in case a packet 29 * wraps around the DMA ring so that we have to copy it. 30 * 31 * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific 32 * configuration header. This way, the core allocates one RX buffer 33 * and one TX buffer, each of which can hold a ethernet packet of 34 * maximum size. 35 * 36 * For some reason, the networking core unconditionally specifies a 37 * 32-byte packet "alignment" (which really should be called 38 * "padding"). MACB shouldn't need that, but we'll refrain from any 39 * core modifications here... 40 */ 41 42 #include <net.h> 43 #include <netdev.h> 44 #include <malloc.h> 45 #include <miiphy.h> 46 47 #include <linux/mii.h> 48 #include <asm/io.h> 49 #include <asm/dma-mapping.h> 50 #include <asm/arch/clk.h> 51 52 #include "macb.h" 53 54 #define CONFIG_SYS_MACB_RX_BUFFER_SIZE 4096 55 #define CONFIG_SYS_MACB_RX_RING_SIZE (CONFIG_SYS_MACB_RX_BUFFER_SIZE / 128) 56 #define CONFIG_SYS_MACB_TX_RING_SIZE 16 57 #define CONFIG_SYS_MACB_TX_TIMEOUT 1000 58 #define CONFIG_SYS_MACB_AUTONEG_TIMEOUT 5000000 59 60 struct macb_dma_desc { 61 u32 addr; 62 u32 ctrl; 63 }; 64 65 #define RXADDR_USED 0x00000001 66 #define RXADDR_WRAP 0x00000002 67 68 #define RXBUF_FRMLEN_MASK 0x00000fff 69 #define RXBUF_FRAME_START 0x00004000 70 #define RXBUF_FRAME_END 0x00008000 71 #define RXBUF_TYPEID_MATCH 0x00400000 72 #define RXBUF_ADDR4_MATCH 0x00800000 73 #define RXBUF_ADDR3_MATCH 0x01000000 74 #define RXBUF_ADDR2_MATCH 0x02000000 75 #define RXBUF_ADDR1_MATCH 0x04000000 76 #define RXBUF_BROADCAST 0x80000000 77 78 #define TXBUF_FRMLEN_MASK 0x000007ff 79 #define TXBUF_FRAME_END 0x00008000 80 #define TXBUF_NOCRC 0x00010000 81 #define TXBUF_EXHAUSTED 0x08000000 82 #define TXBUF_UNDERRUN 0x10000000 83 #define TXBUF_MAXRETRY 0x20000000 84 #define TXBUF_WRAP 0x40000000 85 #define TXBUF_USED 0x80000000 86 87 struct macb_device { 88 void *regs; 89 90 unsigned int rx_tail; 91 unsigned int tx_head; 92 unsigned int tx_tail; 93 94 void *rx_buffer; 95 void *tx_buffer; 96 struct macb_dma_desc *rx_ring; 97 struct macb_dma_desc *tx_ring; 98 99 unsigned long rx_buffer_dma; 100 unsigned long rx_ring_dma; 101 unsigned long tx_ring_dma; 102 103 const struct device *dev; 104 struct eth_device netdev; 105 unsigned short phy_addr; 106 }; 107 #define to_macb(_nd) container_of(_nd, struct macb_device, netdev) 108 109 static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value) 110 { 111 unsigned long netctl; 112 unsigned long netstat; 113 unsigned long frame; 114 115 netctl = macb_readl(macb, NCR); 116 netctl |= MACB_BIT(MPE); 117 macb_writel(macb, NCR, netctl); 118 119 frame = (MACB_BF(SOF, 1) 120 | MACB_BF(RW, 1) 121 | MACB_BF(PHYA, macb->phy_addr) 122 | MACB_BF(REGA, reg) 123 | MACB_BF(CODE, 2) 124 | MACB_BF(DATA, value)); 125 macb_writel(macb, MAN, frame); 126 127 do { 128 netstat = macb_readl(macb, NSR); 129 } while (!(netstat & MACB_BIT(IDLE))); 130 131 netctl = macb_readl(macb, NCR); 132 netctl &= ~MACB_BIT(MPE); 133 macb_writel(macb, NCR, netctl); 134 } 135 136 static u16 macb_mdio_read(struct macb_device *macb, u8 reg) 137 { 138 unsigned long netctl; 139 unsigned long netstat; 140 unsigned long frame; 141 142 netctl = macb_readl(macb, NCR); 143 netctl |= MACB_BIT(MPE); 144 macb_writel(macb, NCR, netctl); 145 146 frame = (MACB_BF(SOF, 1) 147 | MACB_BF(RW, 2) 148 | MACB_BF(PHYA, macb->phy_addr) 149 | MACB_BF(REGA, reg) 150 | MACB_BF(CODE, 2)); 151 macb_writel(macb, MAN, frame); 152 153 do { 154 netstat = macb_readl(macb, NSR); 155 } while (!(netstat & MACB_BIT(IDLE))); 156 157 frame = macb_readl(macb, MAN); 158 159 netctl = macb_readl(macb, NCR); 160 netctl &= ~MACB_BIT(MPE); 161 macb_writel(macb, NCR, netctl); 162 163 return MACB_BFEXT(DATA, frame); 164 } 165 166 void __weak arch_get_mdio_control(const char *name) 167 { 168 return; 169 } 170 171 #if defined(CONFIG_CMD_MII) 172 173 int macb_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value) 174 { 175 struct eth_device *dev = eth_get_dev_by_name(devname); 176 struct macb_device *macb = to_macb(dev); 177 178 if ( macb->phy_addr != phy_adr ) 179 return -1; 180 181 arch_get_mdio_control(devname); 182 *value = macb_mdio_read(macb, reg); 183 184 return 0; 185 } 186 187 int macb_miiphy_write(const char *devname, u8 phy_adr, u8 reg, u16 value) 188 { 189 struct eth_device *dev = eth_get_dev_by_name(devname); 190 struct macb_device *macb = to_macb(dev); 191 192 if ( macb->phy_addr != phy_adr ) 193 return -1; 194 195 arch_get_mdio_control(devname); 196 macb_mdio_write(macb, reg, value); 197 198 return 0; 199 } 200 #endif 201 202 203 #if defined(CONFIG_CMD_NET) 204 205 static int macb_send(struct eth_device *netdev, void *packet, int length) 206 { 207 struct macb_device *macb = to_macb(netdev); 208 unsigned long paddr, ctrl; 209 unsigned int tx_head = macb->tx_head; 210 int i; 211 212 paddr = dma_map_single(packet, length, DMA_TO_DEVICE); 213 214 ctrl = length & TXBUF_FRMLEN_MASK; 215 ctrl |= TXBUF_FRAME_END; 216 if (tx_head == (CONFIG_SYS_MACB_TX_RING_SIZE - 1)) { 217 ctrl |= TXBUF_WRAP; 218 macb->tx_head = 0; 219 } else 220 macb->tx_head++; 221 222 macb->tx_ring[tx_head].ctrl = ctrl; 223 macb->tx_ring[tx_head].addr = paddr; 224 barrier(); 225 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART)); 226 227 /* 228 * I guess this is necessary because the networking core may 229 * re-use the transmit buffer as soon as we return... 230 */ 231 for (i = 0; i <= CONFIG_SYS_MACB_TX_TIMEOUT; i++) { 232 barrier(); 233 ctrl = macb->tx_ring[tx_head].ctrl; 234 if (ctrl & TXBUF_USED) 235 break; 236 udelay(1); 237 } 238 239 dma_unmap_single(packet, length, paddr); 240 241 if (i <= CONFIG_SYS_MACB_TX_TIMEOUT) { 242 if (ctrl & TXBUF_UNDERRUN) 243 printf("%s: TX underrun\n", netdev->name); 244 if (ctrl & TXBUF_EXHAUSTED) 245 printf("%s: TX buffers exhausted in mid frame\n", 246 netdev->name); 247 } else { 248 printf("%s: TX timeout\n", netdev->name); 249 } 250 251 /* No one cares anyway */ 252 return 0; 253 } 254 255 static void reclaim_rx_buffers(struct macb_device *macb, 256 unsigned int new_tail) 257 { 258 unsigned int i; 259 260 i = macb->rx_tail; 261 while (i > new_tail) { 262 macb->rx_ring[i].addr &= ~RXADDR_USED; 263 i++; 264 if (i > CONFIG_SYS_MACB_RX_RING_SIZE) 265 i = 0; 266 } 267 268 while (i < new_tail) { 269 macb->rx_ring[i].addr &= ~RXADDR_USED; 270 i++; 271 } 272 273 barrier(); 274 macb->rx_tail = new_tail; 275 } 276 277 static int macb_recv(struct eth_device *netdev) 278 { 279 struct macb_device *macb = to_macb(netdev); 280 unsigned int rx_tail = macb->rx_tail; 281 void *buffer; 282 int length; 283 int wrapped = 0; 284 u32 status; 285 286 for (;;) { 287 if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED)) 288 return -1; 289 290 status = macb->rx_ring[rx_tail].ctrl; 291 if (status & RXBUF_FRAME_START) { 292 if (rx_tail != macb->rx_tail) 293 reclaim_rx_buffers(macb, rx_tail); 294 wrapped = 0; 295 } 296 297 if (status & RXBUF_FRAME_END) { 298 buffer = macb->rx_buffer + 128 * macb->rx_tail; 299 length = status & RXBUF_FRMLEN_MASK; 300 if (wrapped) { 301 unsigned int headlen, taillen; 302 303 headlen = 128 * (CONFIG_SYS_MACB_RX_RING_SIZE 304 - macb->rx_tail); 305 taillen = length - headlen; 306 memcpy((void *)NetRxPackets[0], 307 buffer, headlen); 308 memcpy((void *)NetRxPackets[0] + headlen, 309 macb->rx_buffer, taillen); 310 buffer = (void *)NetRxPackets[0]; 311 } 312 313 NetReceive(buffer, length); 314 if (++rx_tail >= CONFIG_SYS_MACB_RX_RING_SIZE) 315 rx_tail = 0; 316 reclaim_rx_buffers(macb, rx_tail); 317 } else { 318 if (++rx_tail >= CONFIG_SYS_MACB_RX_RING_SIZE) { 319 wrapped = 1; 320 rx_tail = 0; 321 } 322 } 323 barrier(); 324 } 325 326 return 0; 327 } 328 329 static void macb_phy_reset(struct macb_device *macb) 330 { 331 struct eth_device *netdev = &macb->netdev; 332 int i; 333 u16 status, adv; 334 335 adv = ADVERTISE_CSMA | ADVERTISE_ALL; 336 macb_mdio_write(macb, MII_ADVERTISE, adv); 337 printf("%s: Starting autonegotiation...\n", netdev->name); 338 macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE 339 | BMCR_ANRESTART)); 340 341 for (i = 0; i < CONFIG_SYS_MACB_AUTONEG_TIMEOUT / 100; i++) { 342 status = macb_mdio_read(macb, MII_BMSR); 343 if (status & BMSR_ANEGCOMPLETE) 344 break; 345 udelay(100); 346 } 347 348 if (status & BMSR_ANEGCOMPLETE) 349 printf("%s: Autonegotiation complete\n", netdev->name); 350 else 351 printf("%s: Autonegotiation timed out (status=0x%04x)\n", 352 netdev->name, status); 353 } 354 355 #ifdef CONFIG_MACB_SEARCH_PHY 356 static int macb_phy_find(struct macb_device *macb) 357 { 358 int i; 359 u16 phy_id; 360 361 /* Search for PHY... */ 362 for (i = 0; i < 32; i++) { 363 macb->phy_addr = i; 364 phy_id = macb_mdio_read(macb, MII_PHYSID1); 365 if (phy_id != 0xffff) { 366 printf("%s: PHY present at %d\n", macb->netdev.name, i); 367 return 1; 368 } 369 } 370 371 /* PHY isn't up to snuff */ 372 printf("%s: PHY not found\n", macb->netdev.name); 373 374 return 0; 375 } 376 #endif /* CONFIG_MACB_SEARCH_PHY */ 377 378 379 static int macb_phy_init(struct macb_device *macb) 380 { 381 struct eth_device *netdev = &macb->netdev; 382 u32 ncfgr; 383 u16 phy_id, status, adv, lpa; 384 int media, speed, duplex; 385 int i; 386 387 arch_get_mdio_control(netdev->name); 388 #ifdef CONFIG_MACB_SEARCH_PHY 389 /* Auto-detect phy_addr */ 390 if (!macb_phy_find(macb)) { 391 return 0; 392 } 393 #endif /* CONFIG_MACB_SEARCH_PHY */ 394 395 /* Check if the PHY is up to snuff... */ 396 phy_id = macb_mdio_read(macb, MII_PHYSID1); 397 if (phy_id == 0xffff) { 398 printf("%s: No PHY present\n", netdev->name); 399 return 0; 400 } 401 402 status = macb_mdio_read(macb, MII_BMSR); 403 if (!(status & BMSR_LSTATUS)) { 404 /* Try to re-negotiate if we don't have link already. */ 405 macb_phy_reset(macb); 406 407 for (i = 0; i < CONFIG_SYS_MACB_AUTONEG_TIMEOUT / 100; i++) { 408 status = macb_mdio_read(macb, MII_BMSR); 409 if (status & BMSR_LSTATUS) 410 break; 411 udelay(100); 412 } 413 } 414 415 if (!(status & BMSR_LSTATUS)) { 416 printf("%s: link down (status: 0x%04x)\n", 417 netdev->name, status); 418 return 0; 419 } else { 420 adv = macb_mdio_read(macb, MII_ADVERTISE); 421 lpa = macb_mdio_read(macb, MII_LPA); 422 media = mii_nway_result(lpa & adv); 423 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) 424 ? 1 : 0); 425 duplex = (media & ADVERTISE_FULL) ? 1 : 0; 426 printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n", 427 netdev->name, 428 speed ? "100" : "10", 429 duplex ? "full" : "half", 430 lpa); 431 432 ncfgr = macb_readl(macb, NCFGR); 433 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); 434 if (speed) 435 ncfgr |= MACB_BIT(SPD); 436 if (duplex) 437 ncfgr |= MACB_BIT(FD); 438 macb_writel(macb, NCFGR, ncfgr); 439 return 1; 440 } 441 } 442 443 static int macb_init(struct eth_device *netdev, bd_t *bd) 444 { 445 struct macb_device *macb = to_macb(netdev); 446 unsigned long paddr; 447 int i; 448 449 /* 450 * macb_halt should have been called at some point before now, 451 * so we'll assume the controller is idle. 452 */ 453 454 /* initialize DMA descriptors */ 455 paddr = macb->rx_buffer_dma; 456 for (i = 0; i < CONFIG_SYS_MACB_RX_RING_SIZE; i++) { 457 if (i == (CONFIG_SYS_MACB_RX_RING_SIZE - 1)) 458 paddr |= RXADDR_WRAP; 459 macb->rx_ring[i].addr = paddr; 460 macb->rx_ring[i].ctrl = 0; 461 paddr += 128; 462 } 463 for (i = 0; i < CONFIG_SYS_MACB_TX_RING_SIZE; i++) { 464 macb->tx_ring[i].addr = 0; 465 if (i == (CONFIG_SYS_MACB_TX_RING_SIZE - 1)) 466 macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP; 467 else 468 macb->tx_ring[i].ctrl = TXBUF_USED; 469 } 470 macb->rx_tail = macb->tx_head = macb->tx_tail = 0; 471 472 macb_writel(macb, RBQP, macb->rx_ring_dma); 473 macb_writel(macb, TBQP, macb->tx_ring_dma); 474 475 /* choose RMII or MII mode. This depends on the board */ 476 #ifdef CONFIG_RMII 477 #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ 478 defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \ 479 defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \ 480 defined(CONFIG_AT91SAM9XE) || defined(CONFIG_AT91SAM9X5) 481 macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN)); 482 #else 483 macb_writel(macb, USRIO, 0); 484 #endif 485 #else 486 #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ 487 defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \ 488 defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \ 489 defined(CONFIG_AT91SAM9XE) || defined(CONFIG_AT91SAM9X5) 490 macb_writel(macb, USRIO, MACB_BIT(CLKEN)); 491 #else 492 macb_writel(macb, USRIO, MACB_BIT(MII)); 493 #endif 494 #endif /* CONFIG_RMII */ 495 496 if (!macb_phy_init(macb)) 497 return -1; 498 499 /* Enable TX and RX */ 500 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE)); 501 502 return 0; 503 } 504 505 static void macb_halt(struct eth_device *netdev) 506 { 507 struct macb_device *macb = to_macb(netdev); 508 u32 ncr, tsr; 509 510 /* Halt the controller and wait for any ongoing transmission to end. */ 511 ncr = macb_readl(macb, NCR); 512 ncr |= MACB_BIT(THALT); 513 macb_writel(macb, NCR, ncr); 514 515 do { 516 tsr = macb_readl(macb, TSR); 517 } while (tsr & MACB_BIT(TGO)); 518 519 /* Disable TX and RX, and clear statistics */ 520 macb_writel(macb, NCR, MACB_BIT(CLRSTAT)); 521 } 522 523 static int macb_write_hwaddr(struct eth_device *dev) 524 { 525 struct macb_device *macb = to_macb(dev); 526 u32 hwaddr_bottom; 527 u16 hwaddr_top; 528 529 /* set hardware address */ 530 hwaddr_bottom = dev->enetaddr[0] | dev->enetaddr[1] << 8 | 531 dev->enetaddr[2] << 16 | dev->enetaddr[3] << 24; 532 macb_writel(macb, SA1B, hwaddr_bottom); 533 hwaddr_top = dev->enetaddr[4] | dev->enetaddr[5] << 8; 534 macb_writel(macb, SA1T, hwaddr_top); 535 return 0; 536 } 537 538 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) 539 { 540 struct macb_device *macb; 541 struct eth_device *netdev; 542 unsigned long macb_hz; 543 u32 ncfgr; 544 545 macb = malloc(sizeof(struct macb_device)); 546 if (!macb) { 547 printf("Error: Failed to allocate memory for MACB%d\n", id); 548 return -1; 549 } 550 memset(macb, 0, sizeof(struct macb_device)); 551 552 netdev = &macb->netdev; 553 554 macb->rx_buffer = dma_alloc_coherent(CONFIG_SYS_MACB_RX_BUFFER_SIZE, 555 &macb->rx_buffer_dma); 556 macb->rx_ring = dma_alloc_coherent(CONFIG_SYS_MACB_RX_RING_SIZE 557 * sizeof(struct macb_dma_desc), 558 &macb->rx_ring_dma); 559 macb->tx_ring = dma_alloc_coherent(CONFIG_SYS_MACB_TX_RING_SIZE 560 * sizeof(struct macb_dma_desc), 561 &macb->tx_ring_dma); 562 563 macb->regs = regs; 564 macb->phy_addr = phy_addr; 565 566 sprintf(netdev->name, "macb%d", id); 567 netdev->init = macb_init; 568 netdev->halt = macb_halt; 569 netdev->send = macb_send; 570 netdev->recv = macb_recv; 571 netdev->write_hwaddr = macb_write_hwaddr; 572 573 /* 574 * Do some basic initialization so that we at least can talk 575 * to the PHY 576 */ 577 macb_hz = get_macb_pclk_rate(id); 578 if (macb_hz < 20000000) 579 ncfgr = MACB_BF(CLK, MACB_CLK_DIV8); 580 else if (macb_hz < 40000000) 581 ncfgr = MACB_BF(CLK, MACB_CLK_DIV16); 582 else if (macb_hz < 80000000) 583 ncfgr = MACB_BF(CLK, MACB_CLK_DIV32); 584 else 585 ncfgr = MACB_BF(CLK, MACB_CLK_DIV64); 586 587 macb_writel(macb, NCFGR, ncfgr); 588 589 eth_register(netdev); 590 591 #if defined(CONFIG_CMD_MII) 592 miiphy_register(netdev->name, macb_miiphy_read, macb_miiphy_write); 593 #endif 594 return 0; 595 } 596 597 #endif 598