1 /* 2 * Copyright (C) 2014 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LDPAA_ETH_H 8 #define __LDPAA_ETH_H 9 10 #include <linux/netdevice.h> 11 #include <fsl-mc/fsl_mc.h> 12 #include <fsl-mc/fsl_dpaa_fd.h> 13 #include <fsl-mc/fsl_dprc.h> 14 #include <fsl-mc/fsl_dpni.h> 15 #include <fsl-mc/fsl_dpbp.h> 16 #include <fsl-mc/fsl_dpio.h> 17 #include <fsl-mc/fsl_qbman_portal.h> 18 #include <fsl-mc/fsl_mc_private.h> 19 20 21 enum ldpaa_eth_type { 22 LDPAA_ETH_1G_E, 23 LDPAA_ETH_10G_E, 24 }; 25 26 /* Arbitrary values for now, but we'll need to tune */ 27 #define LDPAA_ETH_NUM_BUFS (2 * 7) 28 #define LDPAA_ETH_REFILL_THRESH (LDPAA_ETH_NUM_BUFS/2) 29 #define LDPAA_ETH_RX_BUFFER_SIZE 2048 30 31 /* Hardware requires alignment for ingress/egress buffer addresses 32 * and ingress buffer lengths. 33 */ 34 #define LDPAA_ETH_BUF_ALIGN 64 35 36 /* So far we're only accomodating a skb backpointer in the frame's 37 * software annotation, but the hardware options are either 0 or 64. 38 */ 39 #define LDPAA_ETH_SWA_SIZE 64 40 41 /* Annotation valid bits in FD FRC */ 42 #define LDPAA_FD_FRC_FASV 0x8000 43 #define LDPAA_FD_FRC_FAEADV 0x4000 44 #define LDPAA_FD_FRC_FAPRV 0x2000 45 #define LDPAA_FD_FRC_FAIADV 0x1000 46 #define LDPAA_FD_FRC_FASWOV 0x0800 47 #define LDPAA_FD_FRC_FAICFDV 0x0400 48 49 /* Annotation bits in FD CTRL */ 50 #define LDPAA_FD_CTRL_ASAL 0x00020000 /* ASAL = 128 */ 51 #define LDPAA_FD_CTRL_PTA 0x00800000 52 #define LDPAA_FD_CTRL_PTV1 0x00400000 53 54 /* TODO: we may want to move this and other WRIOP related defines 55 * to a separate header 56 */ 57 /* Frame annotation status */ 58 struct ldpaa_fas { 59 u8 reserved; 60 u8 ppid; 61 __le16 ifpid; 62 __le32 status; 63 } __packed; 64 65 /* Debug frame, otherwise supposed to be discarded */ 66 #define LDPAA_ETH_FAS_DISC 0x80000000 67 /* MACSEC frame */ 68 #define LDPAA_ETH_FAS_MS 0x40000000 69 #define LDPAA_ETH_FAS_PTP 0x08000000 70 /* Ethernet multicast frame */ 71 #define LDPAA_ETH_FAS_MC 0x04000000 72 /* Ethernet broadcast frame */ 73 #define LDPAA_ETH_FAS_BC 0x02000000 74 #define LDPAA_ETH_FAS_KSE 0x00040000 75 #define LDPAA_ETH_FAS_EOFHE 0x00020000 76 #define LDPAA_ETH_FAS_MNLE 0x00010000 77 #define LDPAA_ETH_FAS_TIDE 0x00008000 78 #define LDPAA_ETH_FAS_PIEE 0x00004000 79 /* Frame length error */ 80 #define LDPAA_ETH_FAS_FLE 0x00002000 81 /* Frame physical error; our favourite pastime */ 82 #define LDPAA_ETH_FAS_FPE 0x00001000 83 #define LDPAA_ETH_FAS_PTE 0x00000080 84 #define LDPAA_ETH_FAS_ISP 0x00000040 85 #define LDPAA_ETH_FAS_PHE 0x00000020 86 #define LDPAA_ETH_FAS_BLE 0x00000010 87 /* L3 csum validation performed */ 88 #define LDPAA_ETH_FAS_L3CV 0x00000008 89 /* L3 csum error */ 90 #define LDPAA_ETH_FAS_L3CE 0x00000004 91 /* L4 csum validation performed */ 92 #define LDPAA_ETH_FAS_L4CV 0x00000002 93 /* L4 csum error */ 94 #define LDPAA_ETH_FAS_L4CE 0x00000001 95 /* These bits always signal errors */ 96 #define LDPAA_ETH_RX_ERR_MASK (LDPAA_ETH_FAS_DISC | \ 97 LDPAA_ETH_FAS_KSE | \ 98 LDPAA_ETH_FAS_EOFHE | \ 99 LDPAA_ETH_FAS_MNLE | \ 100 LDPAA_ETH_FAS_TIDE | \ 101 LDPAA_ETH_FAS_PIEE | \ 102 LDPAA_ETH_FAS_FLE | \ 103 LDPAA_ETH_FAS_FPE | \ 104 LDPAA_ETH_FAS_PTE | \ 105 LDPAA_ETH_FAS_ISP | \ 106 LDPAA_ETH_FAS_PHE | \ 107 LDPAA_ETH_FAS_BLE | \ 108 LDPAA_ETH_FAS_L3CE | \ 109 LDPAA_ETH_FAS_L4CE) 110 /* Unsupported features in the ingress */ 111 #define LDPAA_ETH_RX_UNSUPP_MASK LDPAA_ETH_FAS_MS 112 /* TODO trim down the bitmask; not all of them apply to Tx-confirm */ 113 #define LDPAA_ETH_TXCONF_ERR_MASK (LDPAA_ETH_FAS_KSE | \ 114 LDPAA_ETH_FAS_EOFHE | \ 115 LDPAA_ETH_FAS_MNLE | \ 116 LDPAA_ETH_FAS_TIDE) 117 118 struct ldpaa_eth_priv { 119 struct eth_device *net_dev; 120 int dpni_id; 121 uint16_t dpni_handle; 122 struct dpni_attr dpni_attrs; 123 /* Insofar as the MC is concerned, we're using one layout on all 3 types 124 * of buffers (Rx, Tx, Tx-Conf). 125 */ 126 struct dpni_buffer_layout buf_layout; 127 uint16_t tx_data_offset; 128 129 uint32_t rx_dflt_fqid; 130 uint16_t tx_qdid; 131 uint16_t tx_flow_id; 132 133 enum ldpaa_eth_type type; /* 1G or 10G ethernet */ 134 struct phy_device *phydev; 135 }; 136 137 extern struct fsl_mc_io *dflt_mc_io; 138 extern struct fsl_dpbp_obj *dflt_dpbp; 139 extern struct fsl_dpio_obj *dflt_dpio; 140 141 static void ldpaa_dpbp_drain_cnt(int count); 142 static void ldpaa_dpbp_drain(void); 143 static int ldpaa_dpbp_seed(uint16_t bpid); 144 static void ldpaa_dpbp_free(void); 145 static int ldpaa_dpni_setup(struct ldpaa_eth_priv *priv); 146 static int ldpaa_dpbp_setup(void); 147 static int ldpaa_dpni_bind(struct ldpaa_eth_priv *priv); 148 #endif /* __LDPAA_H */ 149