1 /*------------------------------------------------------------------------ 2 * lan91c96.h 3 * 4 * (C) Copyright 2002 5 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 6 * Rolf Offermanns <rof@sysgo.de> 7 * Copyright (C) 2001 Standard Microsystems Corporation (SMSC) 8 * Developed by Simple Network Magic Corporation (SNMC) 9 * Copyright (C) 1996 by Erik Stahlman (ES) 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 * 13 * This file contains register information and access macros for 14 * the LAN91C96 single chip ethernet controller. It is a modified 15 * version of the smc9111.h file. 16 * 17 * Information contained in this file was obtained from the LAN91C96 18 * manual from SMC. To get a copy, if you really want one, you can find 19 * information under www.smsc.com. 20 * 21 * Authors 22 * Erik Stahlman ( erik@vt.edu ) 23 * Daris A Nevil ( dnevil@snmc.com ) 24 * 25 * History 26 * 04/30/03 Mathijs Haarman Modified smc91111.h (u-boot version) 27 * for lan91c96 28 *------------------------------------------------------------------------- 29 */ 30 #ifndef _LAN91C96_H_ 31 #define _LAN91C96_H_ 32 33 #include <asm/types.h> 34 #include <asm/io.h> 35 #include <config.h> 36 37 /* I want some simple types */ 38 39 typedef unsigned char byte; 40 typedef unsigned short word; 41 typedef unsigned long int dword; 42 43 /* 44 * DEBUGGING LEVELS 45 * 46 * 0 for normal operation 47 * 1 for slightly more details 48 * >2 for various levels of increasingly useless information 49 * 2 for interrupt tracking, status flags 50 * 3 for packet info 51 * 4 for complete packet dumps 52 */ 53 /*#define SMC_DEBUG 0 */ 54 55 /* Because of bank switching, the LAN91xxx uses only 16 I/O ports */ 56 57 #define SMC_IO_EXTENT 16 58 59 #ifdef CONFIG_CPU_PXA25X 60 61 #ifdef CONFIG_LUBBOCK 62 #define SMC_IO_SHIFT 2 63 #undef USE_32_BIT 64 65 #else 66 #define SMC_IO_SHIFT 0 67 #endif 68 69 #define SMCREG(edev, r) ((edev)->iobase+((r)<<SMC_IO_SHIFT)) 70 71 #define SMC_inl(edev, r) (*((volatile dword *)SMCREG(edev, r))) 72 #define SMC_inw(edev, r) (*((volatile word *)SMCREG(edev, r))) 73 #define SMC_inb(edev, p) ({ \ 74 unsigned int __p = p; \ 75 unsigned int __v = SMC_inw(edev, __p & ~1); \ 76 if (__p & 1) __v >>= 8; \ 77 else __v &= 0xff; \ 78 __v; }) 79 80 #define SMC_outl(edev, d, r) (*((volatile dword *)SMCREG(edev, r)) = d) 81 #define SMC_outw(edev, d, r) (*((volatile word *)SMCREG(edev, r)) = d) 82 #define SMC_outb(edev, d, r) ({ word __d = (byte)(d); \ 83 word __w = SMC_inw(edev, (r)&~1); \ 84 __w &= ((r)&1) ? 0x00FF : 0xFF00; \ 85 __w |= ((r)&1) ? __d<<8 : __d; \ 86 SMC_outw(edev, __w, (r)&~1); \ 87 }) 88 89 #define SMC_outsl(edev, r, b, l) ({ int __i; \ 90 dword *__b2; \ 91 __b2 = (dword *) b; \ 92 for (__i = 0; __i < l; __i++) { \ 93 SMC_outl(edev, *(__b2 + __i),\ 94 r); \ 95 } \ 96 }) 97 98 #define SMC_outsw(edev, r, b, l) ({ int __i; \ 99 word *__b2; \ 100 __b2 = (word *) b; \ 101 for (__i = 0; __i < l; __i++) { \ 102 SMC_outw(edev, *(__b2 + __i),\ 103 r); \ 104 } \ 105 }) 106 107 #define SMC_insl(edev, r, b, l) ({ int __i ; \ 108 dword *__b2; \ 109 __b2 = (dword *) b; \ 110 for (__i = 0; __i < l; __i++) { \ 111 *(__b2 + __i) = SMC_inl(edev,\ 112 r); \ 113 SMC_inl(edev, 0); \ 114 }; \ 115 }) 116 117 #define SMC_insw(edev, r, b, l) ({ int __i ; \ 118 word *__b2; \ 119 __b2 = (word *) b; \ 120 for (__i = 0; __i < l; __i++) { \ 121 *(__b2 + __i) = SMC_inw(edev,\ 122 r); \ 123 SMC_inw(edev, 0); \ 124 }; \ 125 }) 126 127 #define SMC_insb(edev, r, b, l) ({ int __i ; \ 128 byte *__b2; \ 129 __b2 = (byte *) b; \ 130 for (__i = 0; __i < l; __i++) { \ 131 *(__b2 + __i) = SMC_inb(edev,\ 132 r); \ 133 SMC_inb(edev, 0); \ 134 }; \ 135 }) 136 137 #else /* if not CONFIG_CPU_PXA25X */ 138 139 /* 140 * We have only 16 Bit PCMCIA access on Socket 0 141 */ 142 143 #define SMC_inw(edev, r) (*((volatile word *)((edev)->iobase+(r)))) 144 #define SMC_inb(edev, r) (((r)&1) ? SMC_inw(edev, (r)&~1)>>8 :\ 145 SMC_inw(edev, r)&0xFF) 146 147 #define SMC_outw(edev, d, r) (*((volatile word *)((edev)->iobase+(r))) = d) 148 #define SMC_outb(edev, d, r) ({ word __d = (byte)(d); \ 149 word __w = SMC_inw(edev, (r)&~1); \ 150 __w &= ((r)&1) ? 0x00FF : 0xFF00; \ 151 __w |= ((r)&1) ? __d<<8 : __d; \ 152 SMC_outw(edev, __w, (r)&~1); \ 153 }) 154 #define SMC_outsw(edev, r, b, l) ({ int __i; \ 155 word *__b2; \ 156 __b2 = (word *) b; \ 157 for (__i = 0; __i < l; __i++) { \ 158 SMC_outw(edev, *(__b2 + __i),\ 159 r); \ 160 } \ 161 }) 162 163 #define SMC_insw(edev, r, b, l) ({ int __i ; \ 164 word *__b2; \ 165 __b2 = (word *) b; \ 166 for (__i = 0; __i < l; __i++) { \ 167 *(__b2 + __i) = SMC_inw(edev,\ 168 r); \ 169 SMC_inw(edev, 0); \ 170 }; \ 171 }) 172 173 #endif 174 175 /* 176 **************************************************************************** 177 * Bank Select Field 178 **************************************************************************** 179 */ 180 #define LAN91C96_BANK_SELECT 14 /* Bank Select Register */ 181 #define LAN91C96_BANKSELECT (0x3UC << 0) 182 #define BANK0 0x00 183 #define BANK1 0x01 184 #define BANK2 0x02 185 #define BANK3 0x03 186 #define BANK4 0x04 187 188 /* 189 **************************************************************************** 190 * EEPROM Addresses. 191 **************************************************************************** 192 */ 193 #define EEPROM_MAC_OFFSET_1 0x6020 194 #define EEPROM_MAC_OFFSET_2 0x6021 195 #define EEPROM_MAC_OFFSET_3 0x6022 196 197 /* 198 **************************************************************************** 199 * Bank 0 Register Map in I/O Space 200 **************************************************************************** 201 */ 202 #define LAN91C96_TCR 0 /* Transmit Control Register */ 203 #define LAN91C96_EPH_STATUS 2 /* EPH Status Register */ 204 #define LAN91C96_RCR 4 /* Receive Control Register */ 205 #define LAN91C96_COUNTER 6 /* Counter Register */ 206 #define LAN91C96_MIR 8 /* Memory Information Register */ 207 #define LAN91C96_MCR 10 /* Memory Configuration Register */ 208 209 /* 210 **************************************************************************** 211 * Transmit Control Register - Bank 0 - Offset 0 212 **************************************************************************** 213 */ 214 #define LAN91C96_TCR_TXENA (0x1U << 0) 215 #define LAN91C96_TCR_LOOP (0x1U << 1) 216 #define LAN91C96_TCR_FORCOL (0x1U << 2) 217 #define LAN91C96_TCR_TXP_EN (0x1U << 3) 218 #define LAN91C96_TCR_PAD_EN (0x1U << 7) 219 #define LAN91C96_TCR_NOCRC (0x1U << 8) 220 #define LAN91C96_TCR_MON_CSN (0x1U << 10) 221 #define LAN91C96_TCR_FDUPLX (0x1U << 11) 222 #define LAN91C96_TCR_STP_SQET (0x1U << 12) 223 #define LAN91C96_TCR_EPH_LOOP (0x1U << 13) 224 #define LAN91C96_TCR_ETEN_TYPE (0x1U << 14) 225 #define LAN91C96_TCR_FDSE (0x1U << 15) 226 227 /* 228 **************************************************************************** 229 * EPH Status Register - Bank 0 - Offset 2 230 **************************************************************************** 231 */ 232 #define LAN91C96_EPHSR_TX_SUC (0x1U << 0) 233 #define LAN91C96_EPHSR_SNGL_COL (0x1U << 1) 234 #define LAN91C96_EPHSR_MUL_COL (0x1U << 2) 235 #define LAN91C96_EPHSR_LTX_MULT (0x1U << 3) 236 #define LAN91C96_EPHSR_16COL (0x1U << 4) 237 #define LAN91C96_EPHSR_SQET (0x1U << 5) 238 #define LAN91C96_EPHSR_LTX_BRD (0x1U << 6) 239 #define LAN91C96_EPHSR_TX_DEFR (0x1U << 7) 240 #define LAN91C96_EPHSR_WAKEUP (0x1U << 8) 241 #define LAN91C96_EPHSR_LATCOL (0x1U << 9) 242 #define LAN91C96_EPHSR_LOST_CARR (0x1U << 10) 243 #define LAN91C96_EPHSR_EXC_DEF (0x1U << 11) 244 #define LAN91C96_EPHSR_CTR_ROL (0x1U << 12) 245 246 #define LAN91C96_EPHSR_LINK_OK (0x1U << 14) 247 #define LAN91C96_EPHSR_TX_UNRN (0x1U << 15) 248 249 #define LAN91C96_EPHSR_ERRORS (LAN91C96_EPHSR_SNGL_COL | \ 250 LAN91C96_EPHSR_MUL_COL | \ 251 LAN91C96_EPHSR_16COL | \ 252 LAN91C96_EPHSR_SQET | \ 253 LAN91C96_EPHSR_TX_DEFR | \ 254 LAN91C96_EPHSR_LATCOL | \ 255 LAN91C96_EPHSR_LOST_CARR | \ 256 LAN91C96_EPHSR_EXC_DEF | \ 257 LAN91C96_EPHSR_LINK_OK | \ 258 LAN91C96_EPHSR_TX_UNRN) 259 260 /* 261 **************************************************************************** 262 * Receive Control Register - Bank 0 - Offset 4 263 **************************************************************************** 264 */ 265 #define LAN91C96_RCR_RX_ABORT (0x1U << 0) 266 #define LAN91C96_RCR_PRMS (0x1U << 1) 267 #define LAN91C96_RCR_ALMUL (0x1U << 2) 268 #define LAN91C96_RCR_RXEN (0x1U << 8) 269 #define LAN91C96_RCR_STRIP_CRC (0x1U << 9) 270 #define LAN91C96_RCR_FILT_CAR (0x1U << 14) 271 #define LAN91C96_RCR_SOFT_RST (0x1U << 15) 272 273 /* 274 **************************************************************************** 275 * Counter Register - Bank 0 - Offset 6 276 **************************************************************************** 277 */ 278 #define LAN91C96_ECR_SNGL_COL (0xFU << 0) 279 #define LAN91C96_ECR_MULT_COL (0xFU << 5) 280 #define LAN91C96_ECR_DEF_TX (0xFU << 8) 281 #define LAN91C96_ECR_EXC_DEF_TX (0xFU << 12) 282 283 /* 284 **************************************************************************** 285 * Memory Information Register - Bank 0 - OFfset 8 286 **************************************************************************** 287 */ 288 #define LAN91C96_MIR_SIZE (0x18 << 0) /* 6144 bytes */ 289 290 /* 291 **************************************************************************** 292 * Memory Configuration Register - Bank 0 - Offset 10 293 **************************************************************************** 294 */ 295 #define LAN91C96_MCR_MEM_RES (0xFFU << 0) 296 #define LAN91C96_MCR_MEM_MULT (0x3U << 9) 297 #define LAN91C96_MCR_HIGH_ID (0x3U << 12) 298 299 #define LAN91C96_MCR_TRANSMIT_PAGES 0x6 300 301 /* 302 **************************************************************************** 303 * Bank 1 Register Map in I/O Space 304 **************************************************************************** 305 */ 306 #define LAN91C96_CONFIG 0 /* Configuration Register */ 307 #define LAN91C96_BASE 2 /* Base Address Register */ 308 #define LAN91C96_IA0 4 /* Individual Address Register - 0 */ 309 #define LAN91C96_IA1 5 /* Individual Address Register - 1 */ 310 #define LAN91C96_IA2 6 /* Individual Address Register - 2 */ 311 #define LAN91C96_IA3 7 /* Individual Address Register - 3 */ 312 #define LAN91C96_IA4 8 /* Individual Address Register - 4 */ 313 #define LAN91C96_IA5 9 /* Individual Address Register - 5 */ 314 #define LAN91C96_GEN_PURPOSE 10 /* General Address Registers */ 315 #define LAN91C96_CONTROL 12 /* Control Register */ 316 317 /* 318 **************************************************************************** 319 * Configuration Register - Bank 1 - Offset 0 320 **************************************************************************** 321 */ 322 #define LAN91C96_CR_INT_SEL0 (0x1U << 1) 323 #define LAN91C96_CR_INT_SEL1 (0x1U << 2) 324 #define LAN91C96_CR_RES (0x3U << 3) 325 #define LAN91C96_CR_DIS_LINK (0x1U << 6) 326 #define LAN91C96_CR_16BIT (0x1U << 7) 327 #define LAN91C96_CR_AUI_SELECT (0x1U << 8) 328 #define LAN91C96_CR_SET_SQLCH (0x1U << 9) 329 #define LAN91C96_CR_FULL_STEP (0x1U << 10) 330 #define LAN91C96_CR_NO_WAIT (0x1U << 12) 331 332 /* 333 **************************************************************************** 334 * Base Address Register - Bank 1 - Offset 2 335 **************************************************************************** 336 */ 337 #define LAN91C96_BAR_RA_BITS (0x27U << 0) 338 #define LAN91C96_BAR_ROM_SIZE (0x1U << 6) 339 #define LAN91C96_BAR_A_BITS (0xFFU << 8) 340 341 /* 342 **************************************************************************** 343 * Control Register - Bank 1 - Offset 12 344 **************************************************************************** 345 */ 346 #define LAN91C96_CTR_STORE (0x1U << 0) 347 #define LAN91C96_CTR_RELOAD (0x1U << 1) 348 #define LAN91C96_CTR_EEPROM (0x1U << 2) 349 #define LAN91C96_CTR_TE_ENABLE (0x1U << 5) 350 #define LAN91C96_CTR_CR_ENABLE (0x1U << 6) 351 #define LAN91C96_CTR_LE_ENABLE (0x1U << 7) 352 #define LAN91C96_CTR_BIT_8 (0x1U << 8) 353 #define LAN91C96_CTR_AUTO_RELEASE (0x1U << 11) 354 #define LAN91C96_CTR_WAKEUP_EN (0x1U << 12) 355 #define LAN91C96_CTR_PWRDN (0x1U << 13) 356 #define LAN91C96_CTR_RCV_BAD (0x1U << 14) 357 358 /* 359 **************************************************************************** 360 * Bank 2 Register Map in I/O Space 361 **************************************************************************** 362 */ 363 #define LAN91C96_MMU 0 /* MMU Command Register */ 364 #define LAN91C96_AUTO_TX_START 1 /* Auto Tx Start Register */ 365 #define LAN91C96_PNR 2 /* Packet Number Register */ 366 #define LAN91C96_ARR 3 /* Allocation Result Register */ 367 #define LAN91C96_FIFO 4 /* FIFO Ports Register */ 368 #define LAN91C96_POINTER 6 /* Pointer Register */ 369 #define LAN91C96_DATA_HIGH 8 /* Data High Register */ 370 #define LAN91C96_DATA_LOW 10 /* Data Low Register */ 371 #define LAN91C96_INT_STATS 12 /* Interrupt Status Register - RO */ 372 #define LAN91C96_INT_ACK 12 /* Interrupt Acknowledge Register -WO */ 373 #define LAN91C96_INT_MASK 13 /* Interrupt Mask Register */ 374 375 /* 376 **************************************************************************** 377 * MMU Command Register - Bank 2 - Offset 0 378 **************************************************************************** 379 */ 380 #define LAN91C96_MMUCR_NO_BUSY (0x1U << 0) 381 #define LAN91C96_MMUCR_N1 (0x1U << 1) 382 #define LAN91C96_MMUCR_N2 (0x1U << 2) 383 #define LAN91C96_MMUCR_COMMAND (0xFU << 4) 384 #define LAN91C96_MMUCR_ALLOC_TX (0x2U << 4) /* WXYZ = 0010 */ 385 #define LAN91C96_MMUCR_RESET_MMU (0x4U << 4) /* WXYZ = 0100 */ 386 #define LAN91C96_MMUCR_REMOVE_RX (0x6U << 4) /* WXYZ = 0110 */ 387 #define LAN91C96_MMUCR_REMOVE_TX (0x7U << 4) /* WXYZ = 0111 */ 388 #define LAN91C96_MMUCR_RELEASE_RX (0x8U << 4) /* WXYZ = 1000 */ 389 #define LAN91C96_MMUCR_RELEASE_TX (0xAU << 4) /* WXYZ = 1010 */ 390 #define LAN91C96_MMUCR_ENQUEUE (0xCU << 4) /* WXYZ = 1100 */ 391 #define LAN91C96_MMUCR_RESET_TX (0xEU << 4) /* WXYZ = 1110 */ 392 393 /* 394 **************************************************************************** 395 * Auto Tx Start Register - Bank 2 - Offset 1 396 **************************************************************************** 397 */ 398 #define LAN91C96_AUTOTX (0xFFU << 0) 399 400 /* 401 **************************************************************************** 402 * Packet Number Register - Bank 2 - Offset 2 403 **************************************************************************** 404 */ 405 #define LAN91C96_PNR_TX (0x1FU << 0) 406 407 /* 408 **************************************************************************** 409 * Allocation Result Register - Bank 2 - Offset 3 410 **************************************************************************** 411 */ 412 #define LAN91C96_ARR_ALLOC_PN (0x7FU << 0) 413 #define LAN91C96_ARR_FAILED (0x1U << 7) 414 415 /* 416 **************************************************************************** 417 * FIFO Ports Register - Bank 2 - Offset 4 418 **************************************************************************** 419 */ 420 #define LAN91C96_FIFO_TX_DONE_PN (0x1FU << 0) 421 #define LAN91C96_FIFO_TEMPTY (0x1U << 7) 422 #define LAN91C96_FIFO_RX_DONE_PN (0x1FU << 8) 423 #define LAN91C96_FIFO_RXEMPTY (0x1U << 15) 424 425 /* 426 **************************************************************************** 427 * Pointer Register - Bank 2 - Offset 6 428 **************************************************************************** 429 */ 430 #define LAN91C96_PTR_LOW (0xFFU << 0) 431 #define LAN91C96_PTR_HIGH (0x7U << 8) 432 #define LAN91C96_PTR_AUTO_TX (0x1U << 11) 433 #define LAN91C96_PTR_ETEN (0x1U << 12) 434 #define LAN91C96_PTR_READ (0x1U << 13) 435 #define LAN91C96_PTR_AUTO_INCR (0x1U << 14) 436 #define LAN91C96_PTR_RCV (0x1U << 15) 437 438 #define LAN91C96_PTR_RX_FRAME (LAN91C96_PTR_RCV | \ 439 LAN91C96_PTR_AUTO_INCR | \ 440 LAN91C96_PTR_READ) 441 442 /* 443 **************************************************************************** 444 * Data Register - Bank 2 - Offset 8 445 **************************************************************************** 446 */ 447 #define LAN91C96_CONTROL_CRC (0x1U << 4) /* CRC bit */ 448 #define LAN91C96_CONTROL_ODD (0x1U << 5) /* ODD bit */ 449 450 /* 451 **************************************************************************** 452 * Interrupt Status Register - Bank 2 - Offset 12 453 **************************************************************************** 454 */ 455 #define LAN91C96_IST_RCV_INT (0x1U << 0) 456 #define LAN91C96_IST_TX_INT (0x1U << 1) 457 #define LAN91C96_IST_TX_EMPTY_INT (0x1U << 2) 458 #define LAN91C96_IST_ALLOC_INT (0x1U << 3) 459 #define LAN91C96_IST_RX_OVRN_INT (0x1U << 4) 460 #define LAN91C96_IST_EPH_INT (0x1U << 5) 461 #define LAN91C96_IST_ERCV_INT (0x1U << 6) 462 #define LAN91C96_IST_RX_IDLE_INT (0x1U << 7) 463 464 /* 465 **************************************************************************** 466 * Interrupt Acknowledge Register - Bank 2 - Offset 12 467 **************************************************************************** 468 */ 469 #define LAN91C96_ACK_TX_INT (0x1U << 1) 470 #define LAN91C96_ACK_TX_EMPTY_INT (0x1U << 2) 471 #define LAN91C96_ACK_RX_OVRN_INT (0x1U << 4) 472 #define LAN91C96_ACK_ERCV_INT (0x1U << 6) 473 474 /* 475 **************************************************************************** 476 * Interrupt Mask Register - Bank 2 - Offset 13 477 **************************************************************************** 478 */ 479 #define LAN91C96_MSK_RCV_INT (0x1U << 0) 480 #define LAN91C96_MSK_TX_INT (0x1U << 1) 481 #define LAN91C96_MSK_TX_EMPTY_INT (0x1U << 2) 482 #define LAN91C96_MSK_ALLOC_INT (0x1U << 3) 483 #define LAN91C96_MSK_RX_OVRN_INT (0x1U << 4) 484 #define LAN91C96_MSK_EPH_INT (0x1U << 5) 485 #define LAN91C96_MSK_ERCV_INT (0x1U << 6) 486 #define LAN91C96_MSK_TX_IDLE_INT (0x1U << 7) 487 488 /* 489 **************************************************************************** 490 * Bank 3 Register Map in I/O Space 491 ************************************************************************** 492 */ 493 #define LAN91C96_MGMT_MDO (0x1U << 0) 494 #define LAN91C96_MGMT_MDI (0x1U << 1) 495 #define LAN91C96_MGMT_MCLK (0x1U << 2) 496 #define LAN91C96_MGMT_MDOE (0x1U << 3) 497 #define LAN91C96_MGMT_LOW_ID (0x3U << 4) 498 #define LAN91C96_MGMT_IOS0 (0x1U << 8) 499 #define LAN91C96_MGMT_IOS1 (0x1U << 9) 500 #define LAN91C96_MGMT_IOS2 (0x1U << 10) 501 #define LAN91C96_MGMT_nXNDEC (0x1U << 11) 502 #define LAN91C96_MGMT_HIGH_ID (0x3U << 12) 503 504 /* 505 **************************************************************************** 506 * Revision Register - Bank 3 - Offset 10 507 **************************************************************************** 508 */ 509 #define LAN91C96_REV_REVID (0xFU << 0) 510 #define LAN91C96_REV_CHIPID (0xFU << 4) 511 512 /* 513 **************************************************************************** 514 * Early RCV Register - Bank 3 - Offset 12 515 **************************************************************************** 516 */ 517 #define LAN91C96_ERCV_THRESHOLD (0x1FU << 0) 518 #define LAN91C96_ERCV_RCV_DISCRD (0x1U << 7) 519 520 /* 521 **************************************************************************** 522 * PCMCIA Configuration Registers 523 **************************************************************************** 524 */ 525 #define LAN91C96_ECOR 0x8000 /* Ethernet Configuration Register */ 526 #define LAN91C96_ECSR 0x8002 /* Ethernet Configuration and Status */ 527 528 /* 529 **************************************************************************** 530 * PCMCIA Ethernet Configuration Option Register (ECOR) 531 **************************************************************************** 532 */ 533 #define LAN91C96_ECOR_ENABLE (0x1U << 0) 534 #define LAN91C96_ECOR_WR_ATTRIB (0x1U << 2) 535 #define LAN91C96_ECOR_LEVEL_REQ (0x1U << 6) 536 #define LAN91C96_ECOR_SRESET (0x1U << 7) 537 538 /* 539 **************************************************************************** 540 * PCMCIA Ethernet Configuration and Status Register (ECSR) 541 **************************************************************************** 542 */ 543 #define LAN91C96_ECSR_INTR (0x1U << 1) 544 #define LAN91C96_ECSR_PWRDWN (0x1U << 2) 545 #define LAN91C96_ECSR_IOIS8 (0x1U << 5) 546 547 /* 548 **************************************************************************** 549 * Receive Frame Status Word - See page 38 of the LAN91C96 specification. 550 **************************************************************************** 551 */ 552 #define LAN91C96_TOO_SHORT (0x1U << 10) 553 #define LAN91C96_TOO_LONG (0x1U << 11) 554 #define LAN91C96_ODD_FRM (0x1U << 12) 555 #define LAN91C96_BAD_CRC (0x1U << 13) 556 #define LAN91C96_BROD_CAST (0x1U << 14) 557 #define LAN91C96_ALGN_ERR (0x1U << 15) 558 559 #define FRAME_FILTER (LAN91C96_TOO_SHORT | LAN91C96_TOO_LONG | LAN91C96_BAD_CRC | LAN91C96_ALGN_ERR) 560 561 /* 562 **************************************************************************** 563 * Default MAC Address 564 **************************************************************************** 565 */ 566 #define MAC_DEF_HI 0x0800 567 #define MAC_DEF_MED 0x3333 568 #define MAC_DEF_LO 0x0100 569 570 /* 571 **************************************************************************** 572 * Default I/O Signature - 0x33 573 **************************************************************************** 574 */ 575 #define LAN91C96_LOW_SIGNATURE (0x33U << 0) 576 #define LAN91C96_HIGH_SIGNATURE (0x33U << 8) 577 #define LAN91C96_SIGNATURE (LAN91C96_HIGH_SIGNATURE | LAN91C96_LOW_SIGNATURE) 578 579 #define LAN91C96_MAX_PAGES 6 /* Maximum number of 256 pages. */ 580 #define ETHERNET_MAX_LENGTH 1514 581 582 583 /*------------------------------------------------------------------------- 584 * I define some macros to make it easier to do somewhat common 585 * or slightly complicated, repeated tasks. 586 *------------------------------------------------------------------------- 587 */ 588 589 /* select a register bank, 0 to 3 */ 590 591 #define SMC_SELECT_BANK(edev, x) { SMC_outw(edev, x, LAN91C96_BANK_SELECT); } 592 593 /* this enables an interrupt in the interrupt mask register */ 594 #define SMC_ENABLE_INT(edev, x) {\ 595 unsigned char mask;\ 596 SMC_SELECT_BANK(edev, 2);\ 597 mask = SMC_inb(edev, LAN91C96_INT_MASK);\ 598 mask |= (x);\ 599 SMC_outb(edev, mask, LAN91C96_INT_MASK); \ 600 } 601 602 /* this disables an interrupt from the interrupt mask register */ 603 604 #define SMC_DISABLE_INT(edev, x) {\ 605 unsigned char mask;\ 606 SMC_SELECT_BANK(edev, 2);\ 607 mask = SMC_inb(edev, LAN91C96_INT_MASK);\ 608 mask &= ~(x);\ 609 SMC_outb(edev, mask, LAN91C96_INT_MASK); \ 610 } 611 612 /*---------------------------------------------------------------------- 613 * Define the interrupts that I want to receive from the card 614 * 615 * I want: 616 * LAN91C96_IST_EPH_INT, for nasty errors 617 * LAN91C96_IST_RCV_INT, for happy received packets 618 * LAN91C96_IST_RX_OVRN_INT, because I have to kick the receiver 619 *------------------------------------------------------------------------- 620 */ 621 #define SMC_INTERRUPT_MASK (LAN91C96_IST_EPH_INT | LAN91C96_IST_RX_OVRN_INT | LAN91C96_IST_RCV_INT) 622 623 #endif /* _LAN91C96_H_ */ 624