1 /*------------------------------------------------------------------------ 2 * lan91c96.h 3 * 4 * (C) Copyright 2002 5 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 6 * Rolf Offermanns <rof@sysgo.de> 7 * Copyright (C) 2001 Standard Microsystems Corporation (SMSC) 8 * Developed by Simple Network Magic Corporation (SNMC) 9 * Copyright (C) 1996 by Erik Stahlman (ES) 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 24 * 25 * This file contains register information and access macros for 26 * the LAN91C96 single chip ethernet controller. It is a modified 27 * version of the smc9111.h file. 28 * 29 * Information contained in this file was obtained from the LAN91C96 30 * manual from SMC. To get a copy, if you really want one, you can find 31 * information under www.smsc.com. 32 * 33 * Authors 34 * Erik Stahlman ( erik@vt.edu ) 35 * Daris A Nevil ( dnevil@snmc.com ) 36 * 37 * History 38 * 04/30/03 Mathijs Haarman Modified smc91111.h (u-boot version) 39 * for lan91c96 40 *------------------------------------------------------------------------- 41 */ 42 #ifndef _LAN91C96_H_ 43 #define _LAN91C96_H_ 44 45 #include <asm/types.h> 46 #include <asm/io.h> 47 #include <config.h> 48 49 /* I want some simple types */ 50 51 typedef unsigned char byte; 52 typedef unsigned short word; 53 typedef unsigned long int dword; 54 55 /* 56 * DEBUGGING LEVELS 57 * 58 * 0 for normal operation 59 * 1 for slightly more details 60 * >2 for various levels of increasingly useless information 61 * 2 for interrupt tracking, status flags 62 * 3 for packet info 63 * 4 for complete packet dumps 64 */ 65 /*#define SMC_DEBUG 0 */ 66 67 /* Because of bank switching, the LAN91xxx uses only 16 I/O ports */ 68 69 #define SMC_IO_EXTENT 16 70 71 #ifdef CONFIG_CPU_PXA25X 72 73 #ifdef CONFIG_LUBBOCK 74 #define SMC_IO_SHIFT 2 75 #undef USE_32_BIT 76 77 #else 78 #define SMC_IO_SHIFT 0 79 #endif 80 81 #define SMCREG(edev, r) ((edev)->iobase+((r)<<SMC_IO_SHIFT)) 82 83 #define SMC_inl(edev, r) (*((volatile dword *)SMCREG(edev, r))) 84 #define SMC_inw(edev, r) (*((volatile word *)SMCREG(edev, r))) 85 #define SMC_inb(edev, p) ({ \ 86 unsigned int __p = p; \ 87 unsigned int __v = SMC_inw(edev, __p & ~1); \ 88 if (__p & 1) __v >>= 8; \ 89 else __v &= 0xff; \ 90 __v; }) 91 92 #define SMC_outl(edev, d, r) (*((volatile dword *)SMCREG(edev, r)) = d) 93 #define SMC_outw(edev, d, r) (*((volatile word *)SMCREG(edev, r)) = d) 94 #define SMC_outb(edev, d, r) ({ word __d = (byte)(d); \ 95 word __w = SMC_inw(edev, (r)&~1); \ 96 __w &= ((r)&1) ? 0x00FF : 0xFF00; \ 97 __w |= ((r)&1) ? __d<<8 : __d; \ 98 SMC_outw(edev, __w, (r)&~1); \ 99 }) 100 101 #define SMC_outsl(edev, r, b, l) ({ int __i; \ 102 dword *__b2; \ 103 __b2 = (dword *) b; \ 104 for (__i = 0; __i < l; __i++) { \ 105 SMC_outl(edev, *(__b2 + __i),\ 106 r); \ 107 } \ 108 }) 109 110 #define SMC_outsw(edev, r, b, l) ({ int __i; \ 111 word *__b2; \ 112 __b2 = (word *) b; \ 113 for (__i = 0; __i < l; __i++) { \ 114 SMC_outw(edev, *(__b2 + __i),\ 115 r); \ 116 } \ 117 }) 118 119 #define SMC_insl(edev, r, b, l) ({ int __i ; \ 120 dword *__b2; \ 121 __b2 = (dword *) b; \ 122 for (__i = 0; __i < l; __i++) { \ 123 *(__b2 + __i) = SMC_inl(edev,\ 124 r); \ 125 SMC_inl(edev, 0); \ 126 }; \ 127 }) 128 129 #define SMC_insw(edev, r, b, l) ({ int __i ; \ 130 word *__b2; \ 131 __b2 = (word *) b; \ 132 for (__i = 0; __i < l; __i++) { \ 133 *(__b2 + __i) = SMC_inw(edev,\ 134 r); \ 135 SMC_inw(edev, 0); \ 136 }; \ 137 }) 138 139 #define SMC_insb(edev, r, b, l) ({ int __i ; \ 140 byte *__b2; \ 141 __b2 = (byte *) b; \ 142 for (__i = 0; __i < l; __i++) { \ 143 *(__b2 + __i) = SMC_inb(edev,\ 144 r); \ 145 SMC_inb(edev, 0); \ 146 }; \ 147 }) 148 149 #else /* if not CONFIG_CPU_PXA25X */ 150 151 /* 152 * We have only 16 Bit PCMCIA access on Socket 0 153 */ 154 155 #define SMC_inw(edev, r) (*((volatile word *)((edev)->iobase+(r)))) 156 #define SMC_inb(edev, r) (((r)&1) ? SMC_inw(edev, (r)&~1)>>8 :\ 157 SMC_inw(edev, r)&0xFF) 158 159 #define SMC_outw(edev, d, r) (*((volatile word *)((edev)->iobase+(r))) = d) 160 #define SMC_outb(edev, d, r) ({ word __d = (byte)(d); \ 161 word __w = SMC_inw(edev, (r)&~1); \ 162 __w &= ((r)&1) ? 0x00FF : 0xFF00; \ 163 __w |= ((r)&1) ? __d<<8 : __d; \ 164 SMC_outw(edev, __w, (r)&~1); \ 165 }) 166 #define SMC_outsw(edev, r, b, l) ({ int __i; \ 167 word *__b2; \ 168 __b2 = (word *) b; \ 169 for (__i = 0; __i < l; __i++) { \ 170 SMC_outw(edev, *(__b2 + __i),\ 171 r); \ 172 } \ 173 }) 174 175 #define SMC_insw(edev, r, b, l) ({ int __i ; \ 176 word *__b2; \ 177 __b2 = (word *) b; \ 178 for (__i = 0; __i < l; __i++) { \ 179 *(__b2 + __i) = SMC_inw(edev,\ 180 r); \ 181 SMC_inw(edev, 0); \ 182 }; \ 183 }) 184 185 #endif 186 187 /* 188 **************************************************************************** 189 * Bank Select Field 190 **************************************************************************** 191 */ 192 #define LAN91C96_BANK_SELECT 14 /* Bank Select Register */ 193 #define LAN91C96_BANKSELECT (0x3UC << 0) 194 #define BANK0 0x00 195 #define BANK1 0x01 196 #define BANK2 0x02 197 #define BANK3 0x03 198 #define BANK4 0x04 199 200 /* 201 **************************************************************************** 202 * EEPROM Addresses. 203 **************************************************************************** 204 */ 205 #define EEPROM_MAC_OFFSET_1 0x6020 206 #define EEPROM_MAC_OFFSET_2 0x6021 207 #define EEPROM_MAC_OFFSET_3 0x6022 208 209 /* 210 **************************************************************************** 211 * Bank 0 Register Map in I/O Space 212 **************************************************************************** 213 */ 214 #define LAN91C96_TCR 0 /* Transmit Control Register */ 215 #define LAN91C96_EPH_STATUS 2 /* EPH Status Register */ 216 #define LAN91C96_RCR 4 /* Receive Control Register */ 217 #define LAN91C96_COUNTER 6 /* Counter Register */ 218 #define LAN91C96_MIR 8 /* Memory Information Register */ 219 #define LAN91C96_MCR 10 /* Memory Configuration Register */ 220 221 /* 222 **************************************************************************** 223 * Transmit Control Register - Bank 0 - Offset 0 224 **************************************************************************** 225 */ 226 #define LAN91C96_TCR_TXENA (0x1U << 0) 227 #define LAN91C96_TCR_LOOP (0x1U << 1) 228 #define LAN91C96_TCR_FORCOL (0x1U << 2) 229 #define LAN91C96_TCR_TXP_EN (0x1U << 3) 230 #define LAN91C96_TCR_PAD_EN (0x1U << 7) 231 #define LAN91C96_TCR_NOCRC (0x1U << 8) 232 #define LAN91C96_TCR_MON_CSN (0x1U << 10) 233 #define LAN91C96_TCR_FDUPLX (0x1U << 11) 234 #define LAN91C96_TCR_STP_SQET (0x1U << 12) 235 #define LAN91C96_TCR_EPH_LOOP (0x1U << 13) 236 #define LAN91C96_TCR_ETEN_TYPE (0x1U << 14) 237 #define LAN91C96_TCR_FDSE (0x1U << 15) 238 239 /* 240 **************************************************************************** 241 * EPH Status Register - Bank 0 - Offset 2 242 **************************************************************************** 243 */ 244 #define LAN91C96_EPHSR_TX_SUC (0x1U << 0) 245 #define LAN91C96_EPHSR_SNGL_COL (0x1U << 1) 246 #define LAN91C96_EPHSR_MUL_COL (0x1U << 2) 247 #define LAN91C96_EPHSR_LTX_MULT (0x1U << 3) 248 #define LAN91C96_EPHSR_16COL (0x1U << 4) 249 #define LAN91C96_EPHSR_SQET (0x1U << 5) 250 #define LAN91C96_EPHSR_LTX_BRD (0x1U << 6) 251 #define LAN91C96_EPHSR_TX_DEFR (0x1U << 7) 252 #define LAN91C96_EPHSR_WAKEUP (0x1U << 8) 253 #define LAN91C96_EPHSR_LATCOL (0x1U << 9) 254 #define LAN91C96_EPHSR_LOST_CARR (0x1U << 10) 255 #define LAN91C96_EPHSR_EXC_DEF (0x1U << 11) 256 #define LAN91C96_EPHSR_CTR_ROL (0x1U << 12) 257 258 #define LAN91C96_EPHSR_LINK_OK (0x1U << 14) 259 #define LAN91C96_EPHSR_TX_UNRN (0x1U << 15) 260 261 #define LAN91C96_EPHSR_ERRORS (LAN91C96_EPHSR_SNGL_COL | \ 262 LAN91C96_EPHSR_MUL_COL | \ 263 LAN91C96_EPHSR_16COL | \ 264 LAN91C96_EPHSR_SQET | \ 265 LAN91C96_EPHSR_TX_DEFR | \ 266 LAN91C96_EPHSR_LATCOL | \ 267 LAN91C96_EPHSR_LOST_CARR | \ 268 LAN91C96_EPHSR_EXC_DEF | \ 269 LAN91C96_EPHSR_LINK_OK | \ 270 LAN91C96_EPHSR_TX_UNRN) 271 272 /* 273 **************************************************************************** 274 * Receive Control Register - Bank 0 - Offset 4 275 **************************************************************************** 276 */ 277 #define LAN91C96_RCR_RX_ABORT (0x1U << 0) 278 #define LAN91C96_RCR_PRMS (0x1U << 1) 279 #define LAN91C96_RCR_ALMUL (0x1U << 2) 280 #define LAN91C96_RCR_RXEN (0x1U << 8) 281 #define LAN91C96_RCR_STRIP_CRC (0x1U << 9) 282 #define LAN91C96_RCR_FILT_CAR (0x1U << 14) 283 #define LAN91C96_RCR_SOFT_RST (0x1U << 15) 284 285 /* 286 **************************************************************************** 287 * Counter Register - Bank 0 - Offset 6 288 **************************************************************************** 289 */ 290 #define LAN91C96_ECR_SNGL_COL (0xFU << 0) 291 #define LAN91C96_ECR_MULT_COL (0xFU << 5) 292 #define LAN91C96_ECR_DEF_TX (0xFU << 8) 293 #define LAN91C96_ECR_EXC_DEF_TX (0xFU << 12) 294 295 /* 296 **************************************************************************** 297 * Memory Information Register - Bank 0 - OFfset 8 298 **************************************************************************** 299 */ 300 #define LAN91C96_MIR_SIZE (0x18 << 0) /* 6144 bytes */ 301 302 /* 303 **************************************************************************** 304 * Memory Configuration Register - Bank 0 - Offset 10 305 **************************************************************************** 306 */ 307 #define LAN91C96_MCR_MEM_RES (0xFFU << 0) 308 #define LAN91C96_MCR_MEM_MULT (0x3U << 9) 309 #define LAN91C96_MCR_HIGH_ID (0x3U << 12) 310 311 #define LAN91C96_MCR_TRANSMIT_PAGES 0x6 312 313 /* 314 **************************************************************************** 315 * Bank 1 Register Map in I/O Space 316 **************************************************************************** 317 */ 318 #define LAN91C96_CONFIG 0 /* Configuration Register */ 319 #define LAN91C96_BASE 2 /* Base Address Register */ 320 #define LAN91C96_IA0 4 /* Individual Address Register - 0 */ 321 #define LAN91C96_IA1 5 /* Individual Address Register - 1 */ 322 #define LAN91C96_IA2 6 /* Individual Address Register - 2 */ 323 #define LAN91C96_IA3 7 /* Individual Address Register - 3 */ 324 #define LAN91C96_IA4 8 /* Individual Address Register - 4 */ 325 #define LAN91C96_IA5 9 /* Individual Address Register - 5 */ 326 #define LAN91C96_GEN_PURPOSE 10 /* General Address Registers */ 327 #define LAN91C96_CONTROL 12 /* Control Register */ 328 329 /* 330 **************************************************************************** 331 * Configuration Register - Bank 1 - Offset 0 332 **************************************************************************** 333 */ 334 #define LAN91C96_CR_INT_SEL0 (0x1U << 1) 335 #define LAN91C96_CR_INT_SEL1 (0x1U << 2) 336 #define LAN91C96_CR_RES (0x3U << 3) 337 #define LAN91C96_CR_DIS_LINK (0x1U << 6) 338 #define LAN91C96_CR_16BIT (0x1U << 7) 339 #define LAN91C96_CR_AUI_SELECT (0x1U << 8) 340 #define LAN91C96_CR_SET_SQLCH (0x1U << 9) 341 #define LAN91C96_CR_FULL_STEP (0x1U << 10) 342 #define LAN91C96_CR_NO_WAIT (0x1U << 12) 343 344 /* 345 **************************************************************************** 346 * Base Address Register - Bank 1 - Offset 2 347 **************************************************************************** 348 */ 349 #define LAN91C96_BAR_RA_BITS (0x27U << 0) 350 #define LAN91C96_BAR_ROM_SIZE (0x1U << 6) 351 #define LAN91C96_BAR_A_BITS (0xFFU << 8) 352 353 /* 354 **************************************************************************** 355 * Control Register - Bank 1 - Offset 12 356 **************************************************************************** 357 */ 358 #define LAN91C96_CTR_STORE (0x1U << 0) 359 #define LAN91C96_CTR_RELOAD (0x1U << 1) 360 #define LAN91C96_CTR_EEPROM (0x1U << 2) 361 #define LAN91C96_CTR_TE_ENABLE (0x1U << 5) 362 #define LAN91C96_CTR_CR_ENABLE (0x1U << 6) 363 #define LAN91C96_CTR_LE_ENABLE (0x1U << 7) 364 #define LAN91C96_CTR_BIT_8 (0x1U << 8) 365 #define LAN91C96_CTR_AUTO_RELEASE (0x1U << 11) 366 #define LAN91C96_CTR_WAKEUP_EN (0x1U << 12) 367 #define LAN91C96_CTR_PWRDN (0x1U << 13) 368 #define LAN91C96_CTR_RCV_BAD (0x1U << 14) 369 370 /* 371 **************************************************************************** 372 * Bank 2 Register Map in I/O Space 373 **************************************************************************** 374 */ 375 #define LAN91C96_MMU 0 /* MMU Command Register */ 376 #define LAN91C96_AUTO_TX_START 1 /* Auto Tx Start Register */ 377 #define LAN91C96_PNR 2 /* Packet Number Register */ 378 #define LAN91C96_ARR 3 /* Allocation Result Register */ 379 #define LAN91C96_FIFO 4 /* FIFO Ports Register */ 380 #define LAN91C96_POINTER 6 /* Pointer Register */ 381 #define LAN91C96_DATA_HIGH 8 /* Data High Register */ 382 #define LAN91C96_DATA_LOW 10 /* Data Low Register */ 383 #define LAN91C96_INT_STATS 12 /* Interrupt Status Register - RO */ 384 #define LAN91C96_INT_ACK 12 /* Interrupt Acknowledge Register -WO */ 385 #define LAN91C96_INT_MASK 13 /* Interrupt Mask Register */ 386 387 /* 388 **************************************************************************** 389 * MMU Command Register - Bank 2 - Offset 0 390 **************************************************************************** 391 */ 392 #define LAN91C96_MMUCR_NO_BUSY (0x1U << 0) 393 #define LAN91C96_MMUCR_N1 (0x1U << 1) 394 #define LAN91C96_MMUCR_N2 (0x1U << 2) 395 #define LAN91C96_MMUCR_COMMAND (0xFU << 4) 396 #define LAN91C96_MMUCR_ALLOC_TX (0x2U << 4) /* WXYZ = 0010 */ 397 #define LAN91C96_MMUCR_RESET_MMU (0x4U << 4) /* WXYZ = 0100 */ 398 #define LAN91C96_MMUCR_REMOVE_RX (0x6U << 4) /* WXYZ = 0110 */ 399 #define LAN91C96_MMUCR_REMOVE_TX (0x7U << 4) /* WXYZ = 0111 */ 400 #define LAN91C96_MMUCR_RELEASE_RX (0x8U << 4) /* WXYZ = 1000 */ 401 #define LAN91C96_MMUCR_RELEASE_TX (0xAU << 4) /* WXYZ = 1010 */ 402 #define LAN91C96_MMUCR_ENQUEUE (0xCU << 4) /* WXYZ = 1100 */ 403 #define LAN91C96_MMUCR_RESET_TX (0xEU << 4) /* WXYZ = 1110 */ 404 405 /* 406 **************************************************************************** 407 * Auto Tx Start Register - Bank 2 - Offset 1 408 **************************************************************************** 409 */ 410 #define LAN91C96_AUTOTX (0xFFU << 0) 411 412 /* 413 **************************************************************************** 414 * Packet Number Register - Bank 2 - Offset 2 415 **************************************************************************** 416 */ 417 #define LAN91C96_PNR_TX (0x1FU << 0) 418 419 /* 420 **************************************************************************** 421 * Allocation Result Register - Bank 2 - Offset 3 422 **************************************************************************** 423 */ 424 #define LAN91C96_ARR_ALLOC_PN (0x7FU << 0) 425 #define LAN91C96_ARR_FAILED (0x1U << 7) 426 427 /* 428 **************************************************************************** 429 * FIFO Ports Register - Bank 2 - Offset 4 430 **************************************************************************** 431 */ 432 #define LAN91C96_FIFO_TX_DONE_PN (0x1FU << 0) 433 #define LAN91C96_FIFO_TEMPTY (0x1U << 7) 434 #define LAN91C96_FIFO_RX_DONE_PN (0x1FU << 8) 435 #define LAN91C96_FIFO_RXEMPTY (0x1U << 15) 436 437 /* 438 **************************************************************************** 439 * Pointer Register - Bank 2 - Offset 6 440 **************************************************************************** 441 */ 442 #define LAN91C96_PTR_LOW (0xFFU << 0) 443 #define LAN91C96_PTR_HIGH (0x7U << 8) 444 #define LAN91C96_PTR_AUTO_TX (0x1U << 11) 445 #define LAN91C96_PTR_ETEN (0x1U << 12) 446 #define LAN91C96_PTR_READ (0x1U << 13) 447 #define LAN91C96_PTR_AUTO_INCR (0x1U << 14) 448 #define LAN91C96_PTR_RCV (0x1U << 15) 449 450 #define LAN91C96_PTR_RX_FRAME (LAN91C96_PTR_RCV | \ 451 LAN91C96_PTR_AUTO_INCR | \ 452 LAN91C96_PTR_READ) 453 454 /* 455 **************************************************************************** 456 * Data Register - Bank 2 - Offset 8 457 **************************************************************************** 458 */ 459 #define LAN91C96_CONTROL_CRC (0x1U << 4) /* CRC bit */ 460 #define LAN91C96_CONTROL_ODD (0x1U << 5) /* ODD bit */ 461 462 /* 463 **************************************************************************** 464 * Interrupt Status Register - Bank 2 - Offset 12 465 **************************************************************************** 466 */ 467 #define LAN91C96_IST_RCV_INT (0x1U << 0) 468 #define LAN91C96_IST_TX_INT (0x1U << 1) 469 #define LAN91C96_IST_TX_EMPTY_INT (0x1U << 2) 470 #define LAN91C96_IST_ALLOC_INT (0x1U << 3) 471 #define LAN91C96_IST_RX_OVRN_INT (0x1U << 4) 472 #define LAN91C96_IST_EPH_INT (0x1U << 5) 473 #define LAN91C96_IST_ERCV_INT (0x1U << 6) 474 #define LAN91C96_IST_RX_IDLE_INT (0x1U << 7) 475 476 /* 477 **************************************************************************** 478 * Interrupt Acknowledge Register - Bank 2 - Offset 12 479 **************************************************************************** 480 */ 481 #define LAN91C96_ACK_TX_INT (0x1U << 1) 482 #define LAN91C96_ACK_TX_EMPTY_INT (0x1U << 2) 483 #define LAN91C96_ACK_RX_OVRN_INT (0x1U << 4) 484 #define LAN91C96_ACK_ERCV_INT (0x1U << 6) 485 486 /* 487 **************************************************************************** 488 * Interrupt Mask Register - Bank 2 - Offset 13 489 **************************************************************************** 490 */ 491 #define LAN91C96_MSK_RCV_INT (0x1U << 0) 492 #define LAN91C96_MSK_TX_INT (0x1U << 1) 493 #define LAN91C96_MSK_TX_EMPTY_INT (0x1U << 2) 494 #define LAN91C96_MSK_ALLOC_INT (0x1U << 3) 495 #define LAN91C96_MSK_RX_OVRN_INT (0x1U << 4) 496 #define LAN91C96_MSK_EPH_INT (0x1U << 5) 497 #define LAN91C96_MSK_ERCV_INT (0x1U << 6) 498 #define LAN91C96_MSK_TX_IDLE_INT (0x1U << 7) 499 500 /* 501 **************************************************************************** 502 * Bank 3 Register Map in I/O Space 503 ************************************************************************** 504 */ 505 #define LAN91C96_MGMT_MDO (0x1U << 0) 506 #define LAN91C96_MGMT_MDI (0x1U << 1) 507 #define LAN91C96_MGMT_MCLK (0x1U << 2) 508 #define LAN91C96_MGMT_MDOE (0x1U << 3) 509 #define LAN91C96_MGMT_LOW_ID (0x3U << 4) 510 #define LAN91C96_MGMT_IOS0 (0x1U << 8) 511 #define LAN91C96_MGMT_IOS1 (0x1U << 9) 512 #define LAN91C96_MGMT_IOS2 (0x1U << 10) 513 #define LAN91C96_MGMT_nXNDEC (0x1U << 11) 514 #define LAN91C96_MGMT_HIGH_ID (0x3U << 12) 515 516 /* 517 **************************************************************************** 518 * Revision Register - Bank 3 - Offset 10 519 **************************************************************************** 520 */ 521 #define LAN91C96_REV_REVID (0xFU << 0) 522 #define LAN91C96_REV_CHIPID (0xFU << 4) 523 524 /* 525 **************************************************************************** 526 * Early RCV Register - Bank 3 - Offset 12 527 **************************************************************************** 528 */ 529 #define LAN91C96_ERCV_THRESHOLD (0x1FU << 0) 530 #define LAN91C96_ERCV_RCV_DISCRD (0x1U << 7) 531 532 /* 533 **************************************************************************** 534 * PCMCIA Configuration Registers 535 **************************************************************************** 536 */ 537 #define LAN91C96_ECOR 0x8000 /* Ethernet Configuration Register */ 538 #define LAN91C96_ECSR 0x8002 /* Ethernet Configuration and Status */ 539 540 /* 541 **************************************************************************** 542 * PCMCIA Ethernet Configuration Option Register (ECOR) 543 **************************************************************************** 544 */ 545 #define LAN91C96_ECOR_ENABLE (0x1U << 0) 546 #define LAN91C96_ECOR_WR_ATTRIB (0x1U << 2) 547 #define LAN91C96_ECOR_LEVEL_REQ (0x1U << 6) 548 #define LAN91C96_ECOR_SRESET (0x1U << 7) 549 550 /* 551 **************************************************************************** 552 * PCMCIA Ethernet Configuration and Status Register (ECSR) 553 **************************************************************************** 554 */ 555 #define LAN91C96_ECSR_INTR (0x1U << 1) 556 #define LAN91C96_ECSR_PWRDWN (0x1U << 2) 557 #define LAN91C96_ECSR_IOIS8 (0x1U << 5) 558 559 /* 560 **************************************************************************** 561 * Receive Frame Status Word - See page 38 of the LAN91C96 specification. 562 **************************************************************************** 563 */ 564 #define LAN91C96_TOO_SHORT (0x1U << 10) 565 #define LAN91C96_TOO_LONG (0x1U << 11) 566 #define LAN91C96_ODD_FRM (0x1U << 12) 567 #define LAN91C96_BAD_CRC (0x1U << 13) 568 #define LAN91C96_BROD_CAST (0x1U << 14) 569 #define LAN91C96_ALGN_ERR (0x1U << 15) 570 571 #define FRAME_FILTER (LAN91C96_TOO_SHORT | LAN91C96_TOO_LONG | LAN91C96_BAD_CRC | LAN91C96_ALGN_ERR) 572 573 /* 574 **************************************************************************** 575 * Default MAC Address 576 **************************************************************************** 577 */ 578 #define MAC_DEF_HI 0x0800 579 #define MAC_DEF_MED 0x3333 580 #define MAC_DEF_LO 0x0100 581 582 /* 583 **************************************************************************** 584 * Default I/O Signature - 0x33 585 **************************************************************************** 586 */ 587 #define LAN91C96_LOW_SIGNATURE (0x33U << 0) 588 #define LAN91C96_HIGH_SIGNATURE (0x33U << 8) 589 #define LAN91C96_SIGNATURE (LAN91C96_HIGH_SIGNATURE | LAN91C96_LOW_SIGNATURE) 590 591 #define LAN91C96_MAX_PAGES 6 /* Maximum number of 256 pages. */ 592 #define ETHERNET_MAX_LENGTH 1514 593 594 595 /*------------------------------------------------------------------------- 596 * I define some macros to make it easier to do somewhat common 597 * or slightly complicated, repeated tasks. 598 *------------------------------------------------------------------------- 599 */ 600 601 /* select a register bank, 0 to 3 */ 602 603 #define SMC_SELECT_BANK(edev, x) { SMC_outw(edev, x, LAN91C96_BANK_SELECT); } 604 605 /* this enables an interrupt in the interrupt mask register */ 606 #define SMC_ENABLE_INT(edev, x) {\ 607 unsigned char mask;\ 608 SMC_SELECT_BANK(edev, 2);\ 609 mask = SMC_inb(edev, LAN91C96_INT_MASK);\ 610 mask |= (x);\ 611 SMC_outb(edev, mask, LAN91C96_INT_MASK); \ 612 } 613 614 /* this disables an interrupt from the interrupt mask register */ 615 616 #define SMC_DISABLE_INT(edev, x) {\ 617 unsigned char mask;\ 618 SMC_SELECT_BANK(edev, 2);\ 619 mask = SMC_inb(edev, LAN91C96_INT_MASK);\ 620 mask &= ~(x);\ 621 SMC_outb(edev, mask, LAN91C96_INT_MASK); \ 622 } 623 624 /*---------------------------------------------------------------------- 625 * Define the interrupts that I want to receive from the card 626 * 627 * I want: 628 * LAN91C96_IST_EPH_INT, for nasty errors 629 * LAN91C96_IST_RCV_INT, for happy received packets 630 * LAN91C96_IST_RX_OVRN_INT, because I have to kick the receiver 631 *------------------------------------------------------------------------- 632 */ 633 #define SMC_INTERRUPT_MASK (LAN91C96_IST_EPH_INT | LAN91C96_IST_RX_OVRN_INT | LAN91C96_IST_RCV_INT) 634 635 #endif /* _LAN91C96_H_ */ 636