1 /*------------------------------------------------------------------------ 2 * lan91c96.h 3 * 4 * (C) Copyright 2002 5 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 6 * Rolf Offermanns <rof@sysgo.de> 7 * Copyright (C) 2001 Standard Microsystems Corporation (SMSC) 8 * Developed by Simple Network Magic Corporation (SNMC) 9 * Copyright (C) 1996 by Erik Stahlman (ES) 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 * 13 * This file contains register information and access macros for 14 * the LAN91C96 single chip ethernet controller. It is a modified 15 * version of the smc9111.h file. 16 * 17 * Information contained in this file was obtained from the LAN91C96 18 * manual from SMC. To get a copy, if you really want one, you can find 19 * information under www.smsc.com. 20 * 21 * Authors 22 * Erik Stahlman ( erik@vt.edu ) 23 * Daris A Nevil ( dnevil@snmc.com ) 24 * 25 * History 26 * 04/30/03 Mathijs Haarman Modified smc91111.h (u-boot version) 27 * for lan91c96 28 *------------------------------------------------------------------------- 29 */ 30 #ifndef _LAN91C96_H_ 31 #define _LAN91C96_H_ 32 33 #include <asm/types.h> 34 #include <asm/io.h> 35 #include <config.h> 36 37 /* I want some simple types */ 38 39 typedef unsigned char byte; 40 typedef unsigned short word; 41 typedef unsigned long int dword; 42 43 /* 44 * DEBUGGING LEVELS 45 * 46 * 0 for normal operation 47 * 1 for slightly more details 48 * >2 for various levels of increasingly useless information 49 * 2 for interrupt tracking, status flags 50 * 3 for packet info 51 * 4 for complete packet dumps 52 */ 53 /*#define SMC_DEBUG 0 */ 54 55 /* Because of bank switching, the LAN91xxx uses only 16 I/O ports */ 56 57 #define SMC_IO_EXTENT 16 58 59 #ifdef CONFIG_CPU_PXA25X 60 61 #define SMC_IO_SHIFT 0 62 63 #define SMCREG(edev, r) ((edev)->iobase+((r)<<SMC_IO_SHIFT)) 64 65 #define SMC_inl(edev, r) (*((volatile dword *)SMCREG(edev, r))) 66 #define SMC_inw(edev, r) (*((volatile word *)SMCREG(edev, r))) 67 #define SMC_inb(edev, p) ({ \ 68 unsigned int __p = p; \ 69 unsigned int __v = SMC_inw(edev, __p & ~1); \ 70 if (__p & 1) __v >>= 8; \ 71 else __v &= 0xff; \ 72 __v; }) 73 74 #define SMC_outl(edev, d, r) (*((volatile dword *)SMCREG(edev, r)) = d) 75 #define SMC_outw(edev, d, r) (*((volatile word *)SMCREG(edev, r)) = d) 76 #define SMC_outb(edev, d, r) ({ word __d = (byte)(d); \ 77 word __w = SMC_inw(edev, (r)&~1); \ 78 __w &= ((r)&1) ? 0x00FF : 0xFF00; \ 79 __w |= ((r)&1) ? __d<<8 : __d; \ 80 SMC_outw(edev, __w, (r)&~1); \ 81 }) 82 83 #define SMC_outsl(edev, r, b, l) ({ int __i; \ 84 dword *__b2; \ 85 __b2 = (dword *) b; \ 86 for (__i = 0; __i < l; __i++) { \ 87 SMC_outl(edev, *(__b2 + __i),\ 88 r); \ 89 } \ 90 }) 91 92 #define SMC_outsw(edev, r, b, l) ({ int __i; \ 93 word *__b2; \ 94 __b2 = (word *) b; \ 95 for (__i = 0; __i < l; __i++) { \ 96 SMC_outw(edev, *(__b2 + __i),\ 97 r); \ 98 } \ 99 }) 100 101 #define SMC_insl(edev, r, b, l) ({ int __i ; \ 102 dword *__b2; \ 103 __b2 = (dword *) b; \ 104 for (__i = 0; __i < l; __i++) { \ 105 *(__b2 + __i) = SMC_inl(edev,\ 106 r); \ 107 SMC_inl(edev, 0); \ 108 }; \ 109 }) 110 111 #define SMC_insw(edev, r, b, l) ({ int __i ; \ 112 word *__b2; \ 113 __b2 = (word *) b; \ 114 for (__i = 0; __i < l; __i++) { \ 115 *(__b2 + __i) = SMC_inw(edev,\ 116 r); \ 117 SMC_inw(edev, 0); \ 118 }; \ 119 }) 120 121 #define SMC_insb(edev, r, b, l) ({ int __i ; \ 122 byte *__b2; \ 123 __b2 = (byte *) b; \ 124 for (__i = 0; __i < l; __i++) { \ 125 *(__b2 + __i) = SMC_inb(edev,\ 126 r); \ 127 SMC_inb(edev, 0); \ 128 }; \ 129 }) 130 131 #else /* if not CONFIG_CPU_PXA25X */ 132 133 /* 134 * We have only 16 Bit PCMCIA access on Socket 0 135 */ 136 137 #define SMC_inw(edev, r) (*((volatile word *)((edev)->iobase+(r)))) 138 #define SMC_inb(edev, r) (((r)&1) ? SMC_inw(edev, (r)&~1)>>8 :\ 139 SMC_inw(edev, r)&0xFF) 140 141 #define SMC_outw(edev, d, r) (*((volatile word *)((edev)->iobase+(r))) = d) 142 #define SMC_outb(edev, d, r) ({ word __d = (byte)(d); \ 143 word __w = SMC_inw(edev, (r)&~1); \ 144 __w &= ((r)&1) ? 0x00FF : 0xFF00; \ 145 __w |= ((r)&1) ? __d<<8 : __d; \ 146 SMC_outw(edev, __w, (r)&~1); \ 147 }) 148 #define SMC_outsw(edev, r, b, l) ({ int __i; \ 149 word *__b2; \ 150 __b2 = (word *) b; \ 151 for (__i = 0; __i < l; __i++) { \ 152 SMC_outw(edev, *(__b2 + __i),\ 153 r); \ 154 } \ 155 }) 156 157 #define SMC_insw(edev, r, b, l) ({ int __i ; \ 158 word *__b2; \ 159 __b2 = (word *) b; \ 160 for (__i = 0; __i < l; __i++) { \ 161 *(__b2 + __i) = SMC_inw(edev,\ 162 r); \ 163 SMC_inw(edev, 0); \ 164 }; \ 165 }) 166 167 #endif 168 169 /* 170 **************************************************************************** 171 * Bank Select Field 172 **************************************************************************** 173 */ 174 #define LAN91C96_BANK_SELECT 14 /* Bank Select Register */ 175 #define LAN91C96_BANKSELECT (0x3UC << 0) 176 #define BANK0 0x00 177 #define BANK1 0x01 178 #define BANK2 0x02 179 #define BANK3 0x03 180 #define BANK4 0x04 181 182 /* 183 **************************************************************************** 184 * EEPROM Addresses. 185 **************************************************************************** 186 */ 187 #define EEPROM_MAC_OFFSET_1 0x6020 188 #define EEPROM_MAC_OFFSET_2 0x6021 189 #define EEPROM_MAC_OFFSET_3 0x6022 190 191 /* 192 **************************************************************************** 193 * Bank 0 Register Map in I/O Space 194 **************************************************************************** 195 */ 196 #define LAN91C96_TCR 0 /* Transmit Control Register */ 197 #define LAN91C96_EPH_STATUS 2 /* EPH Status Register */ 198 #define LAN91C96_RCR 4 /* Receive Control Register */ 199 #define LAN91C96_COUNTER 6 /* Counter Register */ 200 #define LAN91C96_MIR 8 /* Memory Information Register */ 201 #define LAN91C96_MCR 10 /* Memory Configuration Register */ 202 203 /* 204 **************************************************************************** 205 * Transmit Control Register - Bank 0 - Offset 0 206 **************************************************************************** 207 */ 208 #define LAN91C96_TCR_TXENA (0x1U << 0) 209 #define LAN91C96_TCR_LOOP (0x1U << 1) 210 #define LAN91C96_TCR_FORCOL (0x1U << 2) 211 #define LAN91C96_TCR_TXP_EN (0x1U << 3) 212 #define LAN91C96_TCR_PAD_EN (0x1U << 7) 213 #define LAN91C96_TCR_NOCRC (0x1U << 8) 214 #define LAN91C96_TCR_MON_CSN (0x1U << 10) 215 #define LAN91C96_TCR_FDUPLX (0x1U << 11) 216 #define LAN91C96_TCR_STP_SQET (0x1U << 12) 217 #define LAN91C96_TCR_EPH_LOOP (0x1U << 13) 218 #define LAN91C96_TCR_ETEN_TYPE (0x1U << 14) 219 #define LAN91C96_TCR_FDSE (0x1U << 15) 220 221 /* 222 **************************************************************************** 223 * EPH Status Register - Bank 0 - Offset 2 224 **************************************************************************** 225 */ 226 #define LAN91C96_EPHSR_TX_SUC (0x1U << 0) 227 #define LAN91C96_EPHSR_SNGL_COL (0x1U << 1) 228 #define LAN91C96_EPHSR_MUL_COL (0x1U << 2) 229 #define LAN91C96_EPHSR_LTX_MULT (0x1U << 3) 230 #define LAN91C96_EPHSR_16COL (0x1U << 4) 231 #define LAN91C96_EPHSR_SQET (0x1U << 5) 232 #define LAN91C96_EPHSR_LTX_BRD (0x1U << 6) 233 #define LAN91C96_EPHSR_TX_DEFR (0x1U << 7) 234 #define LAN91C96_EPHSR_WAKEUP (0x1U << 8) 235 #define LAN91C96_EPHSR_LATCOL (0x1U << 9) 236 #define LAN91C96_EPHSR_LOST_CARR (0x1U << 10) 237 #define LAN91C96_EPHSR_EXC_DEF (0x1U << 11) 238 #define LAN91C96_EPHSR_CTR_ROL (0x1U << 12) 239 240 #define LAN91C96_EPHSR_LINK_OK (0x1U << 14) 241 #define LAN91C96_EPHSR_TX_UNRN (0x1U << 15) 242 243 #define LAN91C96_EPHSR_ERRORS (LAN91C96_EPHSR_SNGL_COL | \ 244 LAN91C96_EPHSR_MUL_COL | \ 245 LAN91C96_EPHSR_16COL | \ 246 LAN91C96_EPHSR_SQET | \ 247 LAN91C96_EPHSR_TX_DEFR | \ 248 LAN91C96_EPHSR_LATCOL | \ 249 LAN91C96_EPHSR_LOST_CARR | \ 250 LAN91C96_EPHSR_EXC_DEF | \ 251 LAN91C96_EPHSR_LINK_OK | \ 252 LAN91C96_EPHSR_TX_UNRN) 253 254 /* 255 **************************************************************************** 256 * Receive Control Register - Bank 0 - Offset 4 257 **************************************************************************** 258 */ 259 #define LAN91C96_RCR_RX_ABORT (0x1U << 0) 260 #define LAN91C96_RCR_PRMS (0x1U << 1) 261 #define LAN91C96_RCR_ALMUL (0x1U << 2) 262 #define LAN91C96_RCR_RXEN (0x1U << 8) 263 #define LAN91C96_RCR_STRIP_CRC (0x1U << 9) 264 #define LAN91C96_RCR_FILT_CAR (0x1U << 14) 265 #define LAN91C96_RCR_SOFT_RST (0x1U << 15) 266 267 /* 268 **************************************************************************** 269 * Counter Register - Bank 0 - Offset 6 270 **************************************************************************** 271 */ 272 #define LAN91C96_ECR_SNGL_COL (0xFU << 0) 273 #define LAN91C96_ECR_MULT_COL (0xFU << 5) 274 #define LAN91C96_ECR_DEF_TX (0xFU << 8) 275 #define LAN91C96_ECR_EXC_DEF_TX (0xFU << 12) 276 277 /* 278 **************************************************************************** 279 * Memory Information Register - Bank 0 - OFfset 8 280 **************************************************************************** 281 */ 282 #define LAN91C96_MIR_SIZE (0x18 << 0) /* 6144 bytes */ 283 284 /* 285 **************************************************************************** 286 * Memory Configuration Register - Bank 0 - Offset 10 287 **************************************************************************** 288 */ 289 #define LAN91C96_MCR_MEM_RES (0xFFU << 0) 290 #define LAN91C96_MCR_MEM_MULT (0x3U << 9) 291 #define LAN91C96_MCR_HIGH_ID (0x3U << 12) 292 293 #define LAN91C96_MCR_TRANSMIT_PAGES 0x6 294 295 /* 296 **************************************************************************** 297 * Bank 1 Register Map in I/O Space 298 **************************************************************************** 299 */ 300 #define LAN91C96_CONFIG 0 /* Configuration Register */ 301 #define LAN91C96_BASE 2 /* Base Address Register */ 302 #define LAN91C96_IA0 4 /* Individual Address Register - 0 */ 303 #define LAN91C96_IA1 5 /* Individual Address Register - 1 */ 304 #define LAN91C96_IA2 6 /* Individual Address Register - 2 */ 305 #define LAN91C96_IA3 7 /* Individual Address Register - 3 */ 306 #define LAN91C96_IA4 8 /* Individual Address Register - 4 */ 307 #define LAN91C96_IA5 9 /* Individual Address Register - 5 */ 308 #define LAN91C96_GEN_PURPOSE 10 /* General Address Registers */ 309 #define LAN91C96_CONTROL 12 /* Control Register */ 310 311 /* 312 **************************************************************************** 313 * Configuration Register - Bank 1 - Offset 0 314 **************************************************************************** 315 */ 316 #define LAN91C96_CR_INT_SEL0 (0x1U << 1) 317 #define LAN91C96_CR_INT_SEL1 (0x1U << 2) 318 #define LAN91C96_CR_RES (0x3U << 3) 319 #define LAN91C96_CR_DIS_LINK (0x1U << 6) 320 #define LAN91C96_CR_16BIT (0x1U << 7) 321 #define LAN91C96_CR_AUI_SELECT (0x1U << 8) 322 #define LAN91C96_CR_SET_SQLCH (0x1U << 9) 323 #define LAN91C96_CR_FULL_STEP (0x1U << 10) 324 #define LAN91C96_CR_NO_WAIT (0x1U << 12) 325 326 /* 327 **************************************************************************** 328 * Base Address Register - Bank 1 - Offset 2 329 **************************************************************************** 330 */ 331 #define LAN91C96_BAR_RA_BITS (0x27U << 0) 332 #define LAN91C96_BAR_ROM_SIZE (0x1U << 6) 333 #define LAN91C96_BAR_A_BITS (0xFFU << 8) 334 335 /* 336 **************************************************************************** 337 * Control Register - Bank 1 - Offset 12 338 **************************************************************************** 339 */ 340 #define LAN91C96_CTR_STORE (0x1U << 0) 341 #define LAN91C96_CTR_RELOAD (0x1U << 1) 342 #define LAN91C96_CTR_EEPROM (0x1U << 2) 343 #define LAN91C96_CTR_TE_ENABLE (0x1U << 5) 344 #define LAN91C96_CTR_CR_ENABLE (0x1U << 6) 345 #define LAN91C96_CTR_LE_ENABLE (0x1U << 7) 346 #define LAN91C96_CTR_BIT_8 (0x1U << 8) 347 #define LAN91C96_CTR_AUTO_RELEASE (0x1U << 11) 348 #define LAN91C96_CTR_WAKEUP_EN (0x1U << 12) 349 #define LAN91C96_CTR_PWRDN (0x1U << 13) 350 #define LAN91C96_CTR_RCV_BAD (0x1U << 14) 351 352 /* 353 **************************************************************************** 354 * Bank 2 Register Map in I/O Space 355 **************************************************************************** 356 */ 357 #define LAN91C96_MMU 0 /* MMU Command Register */ 358 #define LAN91C96_AUTO_TX_START 1 /* Auto Tx Start Register */ 359 #define LAN91C96_PNR 2 /* Packet Number Register */ 360 #define LAN91C96_ARR 3 /* Allocation Result Register */ 361 #define LAN91C96_FIFO 4 /* FIFO Ports Register */ 362 #define LAN91C96_POINTER 6 /* Pointer Register */ 363 #define LAN91C96_DATA_HIGH 8 /* Data High Register */ 364 #define LAN91C96_DATA_LOW 10 /* Data Low Register */ 365 #define LAN91C96_INT_STATS 12 /* Interrupt Status Register - RO */ 366 #define LAN91C96_INT_ACK 12 /* Interrupt Acknowledge Register -WO */ 367 #define LAN91C96_INT_MASK 13 /* Interrupt Mask Register */ 368 369 /* 370 **************************************************************************** 371 * MMU Command Register - Bank 2 - Offset 0 372 **************************************************************************** 373 */ 374 #define LAN91C96_MMUCR_NO_BUSY (0x1U << 0) 375 #define LAN91C96_MMUCR_N1 (0x1U << 1) 376 #define LAN91C96_MMUCR_N2 (0x1U << 2) 377 #define LAN91C96_MMUCR_COMMAND (0xFU << 4) 378 #define LAN91C96_MMUCR_ALLOC_TX (0x2U << 4) /* WXYZ = 0010 */ 379 #define LAN91C96_MMUCR_RESET_MMU (0x4U << 4) /* WXYZ = 0100 */ 380 #define LAN91C96_MMUCR_REMOVE_RX (0x6U << 4) /* WXYZ = 0110 */ 381 #define LAN91C96_MMUCR_REMOVE_TX (0x7U << 4) /* WXYZ = 0111 */ 382 #define LAN91C96_MMUCR_RELEASE_RX (0x8U << 4) /* WXYZ = 1000 */ 383 #define LAN91C96_MMUCR_RELEASE_TX (0xAU << 4) /* WXYZ = 1010 */ 384 #define LAN91C96_MMUCR_ENQUEUE (0xCU << 4) /* WXYZ = 1100 */ 385 #define LAN91C96_MMUCR_RESET_TX (0xEU << 4) /* WXYZ = 1110 */ 386 387 /* 388 **************************************************************************** 389 * Auto Tx Start Register - Bank 2 - Offset 1 390 **************************************************************************** 391 */ 392 #define LAN91C96_AUTOTX (0xFFU << 0) 393 394 /* 395 **************************************************************************** 396 * Packet Number Register - Bank 2 - Offset 2 397 **************************************************************************** 398 */ 399 #define LAN91C96_PNR_TX (0x1FU << 0) 400 401 /* 402 **************************************************************************** 403 * Allocation Result Register - Bank 2 - Offset 3 404 **************************************************************************** 405 */ 406 #define LAN91C96_ARR_ALLOC_PN (0x7FU << 0) 407 #define LAN91C96_ARR_FAILED (0x1U << 7) 408 409 /* 410 **************************************************************************** 411 * FIFO Ports Register - Bank 2 - Offset 4 412 **************************************************************************** 413 */ 414 #define LAN91C96_FIFO_TX_DONE_PN (0x1FU << 0) 415 #define LAN91C96_FIFO_TEMPTY (0x1U << 7) 416 #define LAN91C96_FIFO_RX_DONE_PN (0x1FU << 8) 417 #define LAN91C96_FIFO_RXEMPTY (0x1U << 15) 418 419 /* 420 **************************************************************************** 421 * Pointer Register - Bank 2 - Offset 6 422 **************************************************************************** 423 */ 424 #define LAN91C96_PTR_LOW (0xFFU << 0) 425 #define LAN91C96_PTR_HIGH (0x7U << 8) 426 #define LAN91C96_PTR_AUTO_TX (0x1U << 11) 427 #define LAN91C96_PTR_ETEN (0x1U << 12) 428 #define LAN91C96_PTR_READ (0x1U << 13) 429 #define LAN91C96_PTR_AUTO_INCR (0x1U << 14) 430 #define LAN91C96_PTR_RCV (0x1U << 15) 431 432 #define LAN91C96_PTR_RX_FRAME (LAN91C96_PTR_RCV | \ 433 LAN91C96_PTR_AUTO_INCR | \ 434 LAN91C96_PTR_READ) 435 436 /* 437 **************************************************************************** 438 * Data Register - Bank 2 - Offset 8 439 **************************************************************************** 440 */ 441 #define LAN91C96_CONTROL_CRC (0x1U << 4) /* CRC bit */ 442 #define LAN91C96_CONTROL_ODD (0x1U << 5) /* ODD bit */ 443 444 /* 445 **************************************************************************** 446 * Interrupt Status Register - Bank 2 - Offset 12 447 **************************************************************************** 448 */ 449 #define LAN91C96_IST_RCV_INT (0x1U << 0) 450 #define LAN91C96_IST_TX_INT (0x1U << 1) 451 #define LAN91C96_IST_TX_EMPTY_INT (0x1U << 2) 452 #define LAN91C96_IST_ALLOC_INT (0x1U << 3) 453 #define LAN91C96_IST_RX_OVRN_INT (0x1U << 4) 454 #define LAN91C96_IST_EPH_INT (0x1U << 5) 455 #define LAN91C96_IST_ERCV_INT (0x1U << 6) 456 #define LAN91C96_IST_RX_IDLE_INT (0x1U << 7) 457 458 /* 459 **************************************************************************** 460 * Interrupt Acknowledge Register - Bank 2 - Offset 12 461 **************************************************************************** 462 */ 463 #define LAN91C96_ACK_TX_INT (0x1U << 1) 464 #define LAN91C96_ACK_TX_EMPTY_INT (0x1U << 2) 465 #define LAN91C96_ACK_RX_OVRN_INT (0x1U << 4) 466 #define LAN91C96_ACK_ERCV_INT (0x1U << 6) 467 468 /* 469 **************************************************************************** 470 * Interrupt Mask Register - Bank 2 - Offset 13 471 **************************************************************************** 472 */ 473 #define LAN91C96_MSK_RCV_INT (0x1U << 0) 474 #define LAN91C96_MSK_TX_INT (0x1U << 1) 475 #define LAN91C96_MSK_TX_EMPTY_INT (0x1U << 2) 476 #define LAN91C96_MSK_ALLOC_INT (0x1U << 3) 477 #define LAN91C96_MSK_RX_OVRN_INT (0x1U << 4) 478 #define LAN91C96_MSK_EPH_INT (0x1U << 5) 479 #define LAN91C96_MSK_ERCV_INT (0x1U << 6) 480 #define LAN91C96_MSK_TX_IDLE_INT (0x1U << 7) 481 482 /* 483 **************************************************************************** 484 * Bank 3 Register Map in I/O Space 485 ************************************************************************** 486 */ 487 #define LAN91C96_MGMT_MDO (0x1U << 0) 488 #define LAN91C96_MGMT_MDI (0x1U << 1) 489 #define LAN91C96_MGMT_MCLK (0x1U << 2) 490 #define LAN91C96_MGMT_MDOE (0x1U << 3) 491 #define LAN91C96_MGMT_LOW_ID (0x3U << 4) 492 #define LAN91C96_MGMT_IOS0 (0x1U << 8) 493 #define LAN91C96_MGMT_IOS1 (0x1U << 9) 494 #define LAN91C96_MGMT_IOS2 (0x1U << 10) 495 #define LAN91C96_MGMT_nXNDEC (0x1U << 11) 496 #define LAN91C96_MGMT_HIGH_ID (0x3U << 12) 497 498 /* 499 **************************************************************************** 500 * Revision Register - Bank 3 - Offset 10 501 **************************************************************************** 502 */ 503 #define LAN91C96_REV_REVID (0xFU << 0) 504 #define LAN91C96_REV_CHIPID (0xFU << 4) 505 506 /* 507 **************************************************************************** 508 * Early RCV Register - Bank 3 - Offset 12 509 **************************************************************************** 510 */ 511 #define LAN91C96_ERCV_THRESHOLD (0x1FU << 0) 512 #define LAN91C96_ERCV_RCV_DISCRD (0x1U << 7) 513 514 /* 515 **************************************************************************** 516 * PCMCIA Configuration Registers 517 **************************************************************************** 518 */ 519 #define LAN91C96_ECOR 0x8000 /* Ethernet Configuration Register */ 520 #define LAN91C96_ECSR 0x8002 /* Ethernet Configuration and Status */ 521 522 /* 523 **************************************************************************** 524 * PCMCIA Ethernet Configuration Option Register (ECOR) 525 **************************************************************************** 526 */ 527 #define LAN91C96_ECOR_ENABLE (0x1U << 0) 528 #define LAN91C96_ECOR_WR_ATTRIB (0x1U << 2) 529 #define LAN91C96_ECOR_LEVEL_REQ (0x1U << 6) 530 #define LAN91C96_ECOR_SRESET (0x1U << 7) 531 532 /* 533 **************************************************************************** 534 * PCMCIA Ethernet Configuration and Status Register (ECSR) 535 **************************************************************************** 536 */ 537 #define LAN91C96_ECSR_INTR (0x1U << 1) 538 #define LAN91C96_ECSR_PWRDWN (0x1U << 2) 539 #define LAN91C96_ECSR_IOIS8 (0x1U << 5) 540 541 /* 542 **************************************************************************** 543 * Receive Frame Status Word - See page 38 of the LAN91C96 specification. 544 **************************************************************************** 545 */ 546 #define LAN91C96_TOO_SHORT (0x1U << 10) 547 #define LAN91C96_TOO_LONG (0x1U << 11) 548 #define LAN91C96_ODD_FRM (0x1U << 12) 549 #define LAN91C96_BAD_CRC (0x1U << 13) 550 #define LAN91C96_BROD_CAST (0x1U << 14) 551 #define LAN91C96_ALGN_ERR (0x1U << 15) 552 553 #define FRAME_FILTER (LAN91C96_TOO_SHORT | LAN91C96_TOO_LONG | LAN91C96_BAD_CRC | LAN91C96_ALGN_ERR) 554 555 /* 556 **************************************************************************** 557 * Default MAC Address 558 **************************************************************************** 559 */ 560 #define MAC_DEF_HI 0x0800 561 #define MAC_DEF_MED 0x3333 562 #define MAC_DEF_LO 0x0100 563 564 /* 565 **************************************************************************** 566 * Default I/O Signature - 0x33 567 **************************************************************************** 568 */ 569 #define LAN91C96_LOW_SIGNATURE (0x33U << 0) 570 #define LAN91C96_HIGH_SIGNATURE (0x33U << 8) 571 #define LAN91C96_SIGNATURE (LAN91C96_HIGH_SIGNATURE | LAN91C96_LOW_SIGNATURE) 572 573 #define LAN91C96_MAX_PAGES 6 /* Maximum number of 256 pages. */ 574 #define ETHERNET_MAX_LENGTH 1514 575 576 577 /*------------------------------------------------------------------------- 578 * I define some macros to make it easier to do somewhat common 579 * or slightly complicated, repeated tasks. 580 *------------------------------------------------------------------------- 581 */ 582 583 /* select a register bank, 0 to 3 */ 584 585 #define SMC_SELECT_BANK(edev, x) { SMC_outw(edev, x, LAN91C96_BANK_SELECT); } 586 587 /* this enables an interrupt in the interrupt mask register */ 588 #define SMC_ENABLE_INT(edev, x) {\ 589 unsigned char mask;\ 590 SMC_SELECT_BANK(edev, 2);\ 591 mask = SMC_inb(edev, LAN91C96_INT_MASK);\ 592 mask |= (x);\ 593 SMC_outb(edev, mask, LAN91C96_INT_MASK); \ 594 } 595 596 /* this disables an interrupt from the interrupt mask register */ 597 598 #define SMC_DISABLE_INT(edev, x) {\ 599 unsigned char mask;\ 600 SMC_SELECT_BANK(edev, 2);\ 601 mask = SMC_inb(edev, LAN91C96_INT_MASK);\ 602 mask &= ~(x);\ 603 SMC_outb(edev, mask, LAN91C96_INT_MASK); \ 604 } 605 606 /*---------------------------------------------------------------------- 607 * Define the interrupts that I want to receive from the card 608 * 609 * I want: 610 * LAN91C96_IST_EPH_INT, for nasty errors 611 * LAN91C96_IST_RCV_INT, for happy received packets 612 * LAN91C96_IST_RX_OVRN_INT, because I have to kick the receiver 613 *------------------------------------------------------------------------- 614 */ 615 #define SMC_INTERRUPT_MASK (LAN91C96_IST_EPH_INT | LAN91C96_IST_RX_OVRN_INT | LAN91C96_IST_RCV_INT) 616 617 #endif /* _LAN91C96_H_ */ 618