1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 22439e4bfSJean-Christophe PLAGNIOL-VILLARD /*------------------------------------------------------------------------ 32439e4bfSJean-Christophe PLAGNIOL-VILLARD * lan91c96.h 42439e4bfSJean-Christophe PLAGNIOL-VILLARD * 52439e4bfSJean-Christophe PLAGNIOL-VILLARD * (C) Copyright 2002 62439e4bfSJean-Christophe PLAGNIOL-VILLARD * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 72439e4bfSJean-Christophe PLAGNIOL-VILLARD * Rolf Offermanns <rof@sysgo.de> 82439e4bfSJean-Christophe PLAGNIOL-VILLARD * Copyright (C) 2001 Standard Microsystems Corporation (SMSC) 92439e4bfSJean-Christophe PLAGNIOL-VILLARD * Developed by Simple Network Magic Corporation (SNMC) 102439e4bfSJean-Christophe PLAGNIOL-VILLARD * Copyright (C) 1996 by Erik Stahlman (ES) 112439e4bfSJean-Christophe PLAGNIOL-VILLARD * 122439e4bfSJean-Christophe PLAGNIOL-VILLARD * This file contains register information and access macros for 132439e4bfSJean-Christophe PLAGNIOL-VILLARD * the LAN91C96 single chip ethernet controller. It is a modified 142439e4bfSJean-Christophe PLAGNIOL-VILLARD * version of the smc9111.h file. 152439e4bfSJean-Christophe PLAGNIOL-VILLARD * 162439e4bfSJean-Christophe PLAGNIOL-VILLARD * Information contained in this file was obtained from the LAN91C96 172439e4bfSJean-Christophe PLAGNIOL-VILLARD * manual from SMC. To get a copy, if you really want one, you can find 182439e4bfSJean-Christophe PLAGNIOL-VILLARD * information under www.smsc.com. 192439e4bfSJean-Christophe PLAGNIOL-VILLARD * 202439e4bfSJean-Christophe PLAGNIOL-VILLARD * Authors 212439e4bfSJean-Christophe PLAGNIOL-VILLARD * Erik Stahlman ( erik@vt.edu ) 222439e4bfSJean-Christophe PLAGNIOL-VILLARD * Daris A Nevil ( dnevil@snmc.com ) 232439e4bfSJean-Christophe PLAGNIOL-VILLARD * 242439e4bfSJean-Christophe PLAGNIOL-VILLARD * History 252439e4bfSJean-Christophe PLAGNIOL-VILLARD * 04/30/03 Mathijs Haarman Modified smc91111.h (u-boot version) 262439e4bfSJean-Christophe PLAGNIOL-VILLARD * for lan91c96 272439e4bfSJean-Christophe PLAGNIOL-VILLARD *------------------------------------------------------------------------- 282439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 292439e4bfSJean-Christophe PLAGNIOL-VILLARD #ifndef _LAN91C96_H_ 302439e4bfSJean-Christophe PLAGNIOL-VILLARD #define _LAN91C96_H_ 312439e4bfSJean-Christophe PLAGNIOL-VILLARD 322439e4bfSJean-Christophe PLAGNIOL-VILLARD #include <asm/types.h> 332439e4bfSJean-Christophe PLAGNIOL-VILLARD #include <asm/io.h> 342439e4bfSJean-Christophe PLAGNIOL-VILLARD #include <config.h> 352439e4bfSJean-Christophe PLAGNIOL-VILLARD 362439e4bfSJean-Christophe PLAGNIOL-VILLARD /* I want some simple types */ 372439e4bfSJean-Christophe PLAGNIOL-VILLARD 382439e4bfSJean-Christophe PLAGNIOL-VILLARD typedef unsigned char byte; 392439e4bfSJean-Christophe PLAGNIOL-VILLARD typedef unsigned short word; 402439e4bfSJean-Christophe PLAGNIOL-VILLARD typedef unsigned long int dword; 412439e4bfSJean-Christophe PLAGNIOL-VILLARD 422439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 432439e4bfSJean-Christophe PLAGNIOL-VILLARD * DEBUGGING LEVELS 442439e4bfSJean-Christophe PLAGNIOL-VILLARD * 452439e4bfSJean-Christophe PLAGNIOL-VILLARD * 0 for normal operation 462439e4bfSJean-Christophe PLAGNIOL-VILLARD * 1 for slightly more details 472439e4bfSJean-Christophe PLAGNIOL-VILLARD * >2 for various levels of increasingly useless information 482439e4bfSJean-Christophe PLAGNIOL-VILLARD * 2 for interrupt tracking, status flags 492439e4bfSJean-Christophe PLAGNIOL-VILLARD * 3 for packet info 502439e4bfSJean-Christophe PLAGNIOL-VILLARD * 4 for complete packet dumps 512439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 522439e4bfSJean-Christophe PLAGNIOL-VILLARD /*#define SMC_DEBUG 0 */ 532439e4bfSJean-Christophe PLAGNIOL-VILLARD 542439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Because of bank switching, the LAN91xxx uses only 16 I/O ports */ 552439e4bfSJean-Christophe PLAGNIOL-VILLARD 562439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_IO_EXTENT 16 572439e4bfSJean-Christophe PLAGNIOL-VILLARD 58abc20abaSMarek Vasut #ifdef CONFIG_CPU_PXA25X 592439e4bfSJean-Christophe PLAGNIOL-VILLARD 602439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_IO_SHIFT 0 612439e4bfSJean-Christophe PLAGNIOL-VILLARD 62b7ad4109SNishanth Menon #define SMCREG(edev, r) ((edev)->iobase+((r)<<SMC_IO_SHIFT)) 632439e4bfSJean-Christophe PLAGNIOL-VILLARD 64b7ad4109SNishanth Menon #define SMC_inl(edev, r) (*((volatile dword *)SMCREG(edev, r))) 65b7ad4109SNishanth Menon #define SMC_inw(edev, r) (*((volatile word *)SMCREG(edev, r))) 66b7ad4109SNishanth Menon #define SMC_inb(edev, p) ({ \ 672439e4bfSJean-Christophe PLAGNIOL-VILLARD unsigned int __p = p; \ 68b7ad4109SNishanth Menon unsigned int __v = SMC_inw(edev, __p & ~1); \ 692439e4bfSJean-Christophe PLAGNIOL-VILLARD if (__p & 1) __v >>= 8; \ 702439e4bfSJean-Christophe PLAGNIOL-VILLARD else __v &= 0xff; \ 712439e4bfSJean-Christophe PLAGNIOL-VILLARD __v; }) 722439e4bfSJean-Christophe PLAGNIOL-VILLARD 73b7ad4109SNishanth Menon #define SMC_outl(edev, d, r) (*((volatile dword *)SMCREG(edev, r)) = d) 74b7ad4109SNishanth Menon #define SMC_outw(edev, d, r) (*((volatile word *)SMCREG(edev, r)) = d) 75b7ad4109SNishanth Menon #define SMC_outb(edev, d, r) ({ word __d = (byte)(d); \ 76b7ad4109SNishanth Menon word __w = SMC_inw(edev, (r)&~1); \ 772439e4bfSJean-Christophe PLAGNIOL-VILLARD __w &= ((r)&1) ? 0x00FF : 0xFF00; \ 782439e4bfSJean-Christophe PLAGNIOL-VILLARD __w |= ((r)&1) ? __d<<8 : __d; \ 79b7ad4109SNishanth Menon SMC_outw(edev, __w, (r)&~1); \ 802439e4bfSJean-Christophe PLAGNIOL-VILLARD }) 812439e4bfSJean-Christophe PLAGNIOL-VILLARD 82b7ad4109SNishanth Menon #define SMC_outsl(edev, r, b, l) ({ int __i; \ 832439e4bfSJean-Christophe PLAGNIOL-VILLARD dword *__b2; \ 842439e4bfSJean-Christophe PLAGNIOL-VILLARD __b2 = (dword *) b; \ 852439e4bfSJean-Christophe PLAGNIOL-VILLARD for (__i = 0; __i < l; __i++) { \ 86b7ad4109SNishanth Menon SMC_outl(edev, *(__b2 + __i),\ 87b7ad4109SNishanth Menon r); \ 882439e4bfSJean-Christophe PLAGNIOL-VILLARD } \ 892439e4bfSJean-Christophe PLAGNIOL-VILLARD }) 902439e4bfSJean-Christophe PLAGNIOL-VILLARD 91b7ad4109SNishanth Menon #define SMC_outsw(edev, r, b, l) ({ int __i; \ 922439e4bfSJean-Christophe PLAGNIOL-VILLARD word *__b2; \ 932439e4bfSJean-Christophe PLAGNIOL-VILLARD __b2 = (word *) b; \ 942439e4bfSJean-Christophe PLAGNIOL-VILLARD for (__i = 0; __i < l; __i++) { \ 95b7ad4109SNishanth Menon SMC_outw(edev, *(__b2 + __i),\ 96b7ad4109SNishanth Menon r); \ 972439e4bfSJean-Christophe PLAGNIOL-VILLARD } \ 982439e4bfSJean-Christophe PLAGNIOL-VILLARD }) 992439e4bfSJean-Christophe PLAGNIOL-VILLARD 100b7ad4109SNishanth Menon #define SMC_insl(edev, r, b, l) ({ int __i ; \ 1012439e4bfSJean-Christophe PLAGNIOL-VILLARD dword *__b2; \ 1022439e4bfSJean-Christophe PLAGNIOL-VILLARD __b2 = (dword *) b; \ 1032439e4bfSJean-Christophe PLAGNIOL-VILLARD for (__i = 0; __i < l; __i++) { \ 104b7ad4109SNishanth Menon *(__b2 + __i) = SMC_inl(edev,\ 105b7ad4109SNishanth Menon r); \ 106b7ad4109SNishanth Menon SMC_inl(edev, 0); \ 1072439e4bfSJean-Christophe PLAGNIOL-VILLARD }; \ 1082439e4bfSJean-Christophe PLAGNIOL-VILLARD }) 1092439e4bfSJean-Christophe PLAGNIOL-VILLARD 110b7ad4109SNishanth Menon #define SMC_insw(edev, r, b, l) ({ int __i ; \ 1112439e4bfSJean-Christophe PLAGNIOL-VILLARD word *__b2; \ 1122439e4bfSJean-Christophe PLAGNIOL-VILLARD __b2 = (word *) b; \ 1132439e4bfSJean-Christophe PLAGNIOL-VILLARD for (__i = 0; __i < l; __i++) { \ 114b7ad4109SNishanth Menon *(__b2 + __i) = SMC_inw(edev,\ 115b7ad4109SNishanth Menon r); \ 116b7ad4109SNishanth Menon SMC_inw(edev, 0); \ 1172439e4bfSJean-Christophe PLAGNIOL-VILLARD }; \ 1182439e4bfSJean-Christophe PLAGNIOL-VILLARD }) 1192439e4bfSJean-Christophe PLAGNIOL-VILLARD 120b7ad4109SNishanth Menon #define SMC_insb(edev, r, b, l) ({ int __i ; \ 1212439e4bfSJean-Christophe PLAGNIOL-VILLARD byte *__b2; \ 1222439e4bfSJean-Christophe PLAGNIOL-VILLARD __b2 = (byte *) b; \ 1232439e4bfSJean-Christophe PLAGNIOL-VILLARD for (__i = 0; __i < l; __i++) { \ 124b7ad4109SNishanth Menon *(__b2 + __i) = SMC_inb(edev,\ 125b7ad4109SNishanth Menon r); \ 126b7ad4109SNishanth Menon SMC_inb(edev, 0); \ 1272439e4bfSJean-Christophe PLAGNIOL-VILLARD }; \ 1282439e4bfSJean-Christophe PLAGNIOL-VILLARD }) 1292439e4bfSJean-Christophe PLAGNIOL-VILLARD 130abc20abaSMarek Vasut #else /* if not CONFIG_CPU_PXA25X */ 1312439e4bfSJean-Christophe PLAGNIOL-VILLARD 1322439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 1332439e4bfSJean-Christophe PLAGNIOL-VILLARD * We have only 16 Bit PCMCIA access on Socket 0 1342439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 1352439e4bfSJean-Christophe PLAGNIOL-VILLARD 136b7ad4109SNishanth Menon #define SMC_inw(edev, r) (*((volatile word *)((edev)->iobase+(r)))) 137b7ad4109SNishanth Menon #define SMC_inb(edev, r) (((r)&1) ? SMC_inw(edev, (r)&~1)>>8 :\ 138b7ad4109SNishanth Menon SMC_inw(edev, r)&0xFF) 1392439e4bfSJean-Christophe PLAGNIOL-VILLARD 140b7ad4109SNishanth Menon #define SMC_outw(edev, d, r) (*((volatile word *)((edev)->iobase+(r))) = d) 141b7ad4109SNishanth Menon #define SMC_outb(edev, d, r) ({ word __d = (byte)(d); \ 142b7ad4109SNishanth Menon word __w = SMC_inw(edev, (r)&~1); \ 1432439e4bfSJean-Christophe PLAGNIOL-VILLARD __w &= ((r)&1) ? 0x00FF : 0xFF00; \ 1442439e4bfSJean-Christophe PLAGNIOL-VILLARD __w |= ((r)&1) ? __d<<8 : __d; \ 145b7ad4109SNishanth Menon SMC_outw(edev, __w, (r)&~1); \ 1462439e4bfSJean-Christophe PLAGNIOL-VILLARD }) 147b7ad4109SNishanth Menon #define SMC_outsw(edev, r, b, l) ({ int __i; \ 1482439e4bfSJean-Christophe PLAGNIOL-VILLARD word *__b2; \ 1492439e4bfSJean-Christophe PLAGNIOL-VILLARD __b2 = (word *) b; \ 1502439e4bfSJean-Christophe PLAGNIOL-VILLARD for (__i = 0; __i < l; __i++) { \ 151b7ad4109SNishanth Menon SMC_outw(edev, *(__b2 + __i),\ 152b7ad4109SNishanth Menon r); \ 1532439e4bfSJean-Christophe PLAGNIOL-VILLARD } \ 1542439e4bfSJean-Christophe PLAGNIOL-VILLARD }) 1552439e4bfSJean-Christophe PLAGNIOL-VILLARD 156b7ad4109SNishanth Menon #define SMC_insw(edev, r, b, l) ({ int __i ; \ 1572439e4bfSJean-Christophe PLAGNIOL-VILLARD word *__b2; \ 1582439e4bfSJean-Christophe PLAGNIOL-VILLARD __b2 = (word *) b; \ 1592439e4bfSJean-Christophe PLAGNIOL-VILLARD for (__i = 0; __i < l; __i++) { \ 160b7ad4109SNishanth Menon *(__b2 + __i) = SMC_inw(edev,\ 161b7ad4109SNishanth Menon r); \ 162b7ad4109SNishanth Menon SMC_inw(edev, 0); \ 1632439e4bfSJean-Christophe PLAGNIOL-VILLARD }; \ 1642439e4bfSJean-Christophe PLAGNIOL-VILLARD }) 1652439e4bfSJean-Christophe PLAGNIOL-VILLARD 1662439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif 1672439e4bfSJean-Christophe PLAGNIOL-VILLARD 1682439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 1692439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 1702439e4bfSJean-Christophe PLAGNIOL-VILLARD * Bank Select Field 1712439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 1722439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 1732439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_BANK_SELECT 14 /* Bank Select Register */ 1742439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_BANKSELECT (0x3UC << 0) 1752439e4bfSJean-Christophe PLAGNIOL-VILLARD #define BANK0 0x00 1762439e4bfSJean-Christophe PLAGNIOL-VILLARD #define BANK1 0x01 1772439e4bfSJean-Christophe PLAGNIOL-VILLARD #define BANK2 0x02 1782439e4bfSJean-Christophe PLAGNIOL-VILLARD #define BANK3 0x03 1792439e4bfSJean-Christophe PLAGNIOL-VILLARD #define BANK4 0x04 1802439e4bfSJean-Christophe PLAGNIOL-VILLARD 1812439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 1822439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 1832439e4bfSJean-Christophe PLAGNIOL-VILLARD * EEPROM Addresses. 1842439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 1852439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 1862439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EEPROM_MAC_OFFSET_1 0x6020 1872439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EEPROM_MAC_OFFSET_2 0x6021 1882439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EEPROM_MAC_OFFSET_3 0x6022 1892439e4bfSJean-Christophe PLAGNIOL-VILLARD 1902439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 1912439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 1922439e4bfSJean-Christophe PLAGNIOL-VILLARD * Bank 0 Register Map in I/O Space 1932439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 1942439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 1952439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_TCR 0 /* Transmit Control Register */ 1962439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_EPH_STATUS 2 /* EPH Status Register */ 1972439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_RCR 4 /* Receive Control Register */ 1982439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_COUNTER 6 /* Counter Register */ 1992439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MIR 8 /* Memory Information Register */ 2002439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MCR 10 /* Memory Configuration Register */ 2012439e4bfSJean-Christophe PLAGNIOL-VILLARD 2022439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 2032439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 2042439e4bfSJean-Christophe PLAGNIOL-VILLARD * Transmit Control Register - Bank 0 - Offset 0 2052439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 2062439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 2072439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_TCR_TXENA (0x1U << 0) 2082439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_TCR_LOOP (0x1U << 1) 2092439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_TCR_FORCOL (0x1U << 2) 2102439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_TCR_TXP_EN (0x1U << 3) 2112439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_TCR_PAD_EN (0x1U << 7) 2122439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_TCR_NOCRC (0x1U << 8) 2132439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_TCR_MON_CSN (0x1U << 10) 2142439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_TCR_FDUPLX (0x1U << 11) 2152439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_TCR_STP_SQET (0x1U << 12) 2162439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_TCR_EPH_LOOP (0x1U << 13) 2172439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_TCR_ETEN_TYPE (0x1U << 14) 2182439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_TCR_FDSE (0x1U << 15) 2192439e4bfSJean-Christophe PLAGNIOL-VILLARD 2202439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 2212439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 2222439e4bfSJean-Christophe PLAGNIOL-VILLARD * EPH Status Register - Bank 0 - Offset 2 2232439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 2242439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 2252439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_EPHSR_TX_SUC (0x1U << 0) 2262439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_EPHSR_SNGL_COL (0x1U << 1) 2272439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_EPHSR_MUL_COL (0x1U << 2) 2282439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_EPHSR_LTX_MULT (0x1U << 3) 2292439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_EPHSR_16COL (0x1U << 4) 2302439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_EPHSR_SQET (0x1U << 5) 2312439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_EPHSR_LTX_BRD (0x1U << 6) 2322439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_EPHSR_TX_DEFR (0x1U << 7) 2332439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_EPHSR_WAKEUP (0x1U << 8) 2342439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_EPHSR_LATCOL (0x1U << 9) 2352439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_EPHSR_LOST_CARR (0x1U << 10) 2362439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_EPHSR_EXC_DEF (0x1U << 11) 2372439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_EPHSR_CTR_ROL (0x1U << 12) 2382439e4bfSJean-Christophe PLAGNIOL-VILLARD 2392439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_EPHSR_LINK_OK (0x1U << 14) 2402439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_EPHSR_TX_UNRN (0x1U << 15) 2412439e4bfSJean-Christophe PLAGNIOL-VILLARD 2422439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_EPHSR_ERRORS (LAN91C96_EPHSR_SNGL_COL | \ 2432439e4bfSJean-Christophe PLAGNIOL-VILLARD LAN91C96_EPHSR_MUL_COL | \ 2442439e4bfSJean-Christophe PLAGNIOL-VILLARD LAN91C96_EPHSR_16COL | \ 2452439e4bfSJean-Christophe PLAGNIOL-VILLARD LAN91C96_EPHSR_SQET | \ 2462439e4bfSJean-Christophe PLAGNIOL-VILLARD LAN91C96_EPHSR_TX_DEFR | \ 2472439e4bfSJean-Christophe PLAGNIOL-VILLARD LAN91C96_EPHSR_LATCOL | \ 2482439e4bfSJean-Christophe PLAGNIOL-VILLARD LAN91C96_EPHSR_LOST_CARR | \ 2492439e4bfSJean-Christophe PLAGNIOL-VILLARD LAN91C96_EPHSR_EXC_DEF | \ 2502439e4bfSJean-Christophe PLAGNIOL-VILLARD LAN91C96_EPHSR_LINK_OK | \ 2512439e4bfSJean-Christophe PLAGNIOL-VILLARD LAN91C96_EPHSR_TX_UNRN) 2522439e4bfSJean-Christophe PLAGNIOL-VILLARD 2532439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 2542439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 2552439e4bfSJean-Christophe PLAGNIOL-VILLARD * Receive Control Register - Bank 0 - Offset 4 2562439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 2572439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 2582439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_RCR_RX_ABORT (0x1U << 0) 2592439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_RCR_PRMS (0x1U << 1) 2602439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_RCR_ALMUL (0x1U << 2) 2612439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_RCR_RXEN (0x1U << 8) 2622439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_RCR_STRIP_CRC (0x1U << 9) 2632439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_RCR_FILT_CAR (0x1U << 14) 2642439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_RCR_SOFT_RST (0x1U << 15) 2652439e4bfSJean-Christophe PLAGNIOL-VILLARD 2662439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 2672439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 2682439e4bfSJean-Christophe PLAGNIOL-VILLARD * Counter Register - Bank 0 - Offset 6 2692439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 2702439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 2712439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_ECR_SNGL_COL (0xFU << 0) 2722439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_ECR_MULT_COL (0xFU << 5) 2732439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_ECR_DEF_TX (0xFU << 8) 2742439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_ECR_EXC_DEF_TX (0xFU << 12) 2752439e4bfSJean-Christophe PLAGNIOL-VILLARD 2762439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 2772439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 2782439e4bfSJean-Christophe PLAGNIOL-VILLARD * Memory Information Register - Bank 0 - OFfset 8 2792439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 2802439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 2812439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MIR_SIZE (0x18 << 0) /* 6144 bytes */ 2822439e4bfSJean-Christophe PLAGNIOL-VILLARD 2832439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 2842439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 2852439e4bfSJean-Christophe PLAGNIOL-VILLARD * Memory Configuration Register - Bank 0 - Offset 10 2862439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 2872439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 2882439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MCR_MEM_RES (0xFFU << 0) 2892439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MCR_MEM_MULT (0x3U << 9) 2902439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MCR_HIGH_ID (0x3U << 12) 2912439e4bfSJean-Christophe PLAGNIOL-VILLARD 2922439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MCR_TRANSMIT_PAGES 0x6 2932439e4bfSJean-Christophe PLAGNIOL-VILLARD 2942439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 2952439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 2962439e4bfSJean-Christophe PLAGNIOL-VILLARD * Bank 1 Register Map in I/O Space 2972439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 2982439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 2992439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_CONFIG 0 /* Configuration Register */ 3002439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_BASE 2 /* Base Address Register */ 3012439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_IA0 4 /* Individual Address Register - 0 */ 3022439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_IA1 5 /* Individual Address Register - 1 */ 3032439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_IA2 6 /* Individual Address Register - 2 */ 3042439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_IA3 7 /* Individual Address Register - 3 */ 3052439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_IA4 8 /* Individual Address Register - 4 */ 3062439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_IA5 9 /* Individual Address Register - 5 */ 3072439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_GEN_PURPOSE 10 /* General Address Registers */ 3082439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_CONTROL 12 /* Control Register */ 3092439e4bfSJean-Christophe PLAGNIOL-VILLARD 3102439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 3112439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 3122439e4bfSJean-Christophe PLAGNIOL-VILLARD * Configuration Register - Bank 1 - Offset 0 3132439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 3142439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 3152439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_CR_INT_SEL0 (0x1U << 1) 3162439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_CR_INT_SEL1 (0x1U << 2) 3172439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_CR_RES (0x3U << 3) 3182439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_CR_DIS_LINK (0x1U << 6) 3192439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_CR_16BIT (0x1U << 7) 3202439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_CR_AUI_SELECT (0x1U << 8) 3212439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_CR_SET_SQLCH (0x1U << 9) 3222439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_CR_FULL_STEP (0x1U << 10) 3232439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_CR_NO_WAIT (0x1U << 12) 3242439e4bfSJean-Christophe PLAGNIOL-VILLARD 3252439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 3262439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 3272439e4bfSJean-Christophe PLAGNIOL-VILLARD * Base Address Register - Bank 1 - Offset 2 3282439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 3292439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 3302439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_BAR_RA_BITS (0x27U << 0) 3312439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_BAR_ROM_SIZE (0x1U << 6) 3322439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_BAR_A_BITS (0xFFU << 8) 3332439e4bfSJean-Christophe PLAGNIOL-VILLARD 3342439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 3352439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 3362439e4bfSJean-Christophe PLAGNIOL-VILLARD * Control Register - Bank 1 - Offset 12 3372439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 3382439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 3392439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_CTR_STORE (0x1U << 0) 3402439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_CTR_RELOAD (0x1U << 1) 3412439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_CTR_EEPROM (0x1U << 2) 3422439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_CTR_TE_ENABLE (0x1U << 5) 3432439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_CTR_CR_ENABLE (0x1U << 6) 3442439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_CTR_LE_ENABLE (0x1U << 7) 3452439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_CTR_BIT_8 (0x1U << 8) 3462439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_CTR_AUTO_RELEASE (0x1U << 11) 3472439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_CTR_WAKEUP_EN (0x1U << 12) 3482439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_CTR_PWRDN (0x1U << 13) 3492439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_CTR_RCV_BAD (0x1U << 14) 3502439e4bfSJean-Christophe PLAGNIOL-VILLARD 3512439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 3522439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 3532439e4bfSJean-Christophe PLAGNIOL-VILLARD * Bank 2 Register Map in I/O Space 3542439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 3552439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 3562439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MMU 0 /* MMU Command Register */ 3572439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_AUTO_TX_START 1 /* Auto Tx Start Register */ 3582439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_PNR 2 /* Packet Number Register */ 3592439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_ARR 3 /* Allocation Result Register */ 3602439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_FIFO 4 /* FIFO Ports Register */ 3612439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_POINTER 6 /* Pointer Register */ 3622439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_DATA_HIGH 8 /* Data High Register */ 3632439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_DATA_LOW 10 /* Data Low Register */ 3642439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_INT_STATS 12 /* Interrupt Status Register - RO */ 3652439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_INT_ACK 12 /* Interrupt Acknowledge Register -WO */ 3662439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_INT_MASK 13 /* Interrupt Mask Register */ 3672439e4bfSJean-Christophe PLAGNIOL-VILLARD 3682439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 3692439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 3702439e4bfSJean-Christophe PLAGNIOL-VILLARD * MMU Command Register - Bank 2 - Offset 0 3712439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 3722439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 3732439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MMUCR_NO_BUSY (0x1U << 0) 3742439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MMUCR_N1 (0x1U << 1) 3752439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MMUCR_N2 (0x1U << 2) 3762439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MMUCR_COMMAND (0xFU << 4) 3772439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MMUCR_ALLOC_TX (0x2U << 4) /* WXYZ = 0010 */ 3782439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MMUCR_RESET_MMU (0x4U << 4) /* WXYZ = 0100 */ 3792439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MMUCR_REMOVE_RX (0x6U << 4) /* WXYZ = 0110 */ 3802439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MMUCR_REMOVE_TX (0x7U << 4) /* WXYZ = 0111 */ 3812439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MMUCR_RELEASE_RX (0x8U << 4) /* WXYZ = 1000 */ 3822439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MMUCR_RELEASE_TX (0xAU << 4) /* WXYZ = 1010 */ 3832439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MMUCR_ENQUEUE (0xCU << 4) /* WXYZ = 1100 */ 3842439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MMUCR_RESET_TX (0xEU << 4) /* WXYZ = 1110 */ 3852439e4bfSJean-Christophe PLAGNIOL-VILLARD 3862439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 3872439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 3882439e4bfSJean-Christophe PLAGNIOL-VILLARD * Auto Tx Start Register - Bank 2 - Offset 1 3892439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 3902439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 3912439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_AUTOTX (0xFFU << 0) 3922439e4bfSJean-Christophe PLAGNIOL-VILLARD 3932439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 3942439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 3952439e4bfSJean-Christophe PLAGNIOL-VILLARD * Packet Number Register - Bank 2 - Offset 2 3962439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 3972439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 3982439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_PNR_TX (0x1FU << 0) 3992439e4bfSJean-Christophe PLAGNIOL-VILLARD 4002439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 4012439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 4022439e4bfSJean-Christophe PLAGNIOL-VILLARD * Allocation Result Register - Bank 2 - Offset 3 4032439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 4042439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 4052439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_ARR_ALLOC_PN (0x7FU << 0) 4062439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_ARR_FAILED (0x1U << 7) 4072439e4bfSJean-Christophe PLAGNIOL-VILLARD 4082439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 4092439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 4102439e4bfSJean-Christophe PLAGNIOL-VILLARD * FIFO Ports Register - Bank 2 - Offset 4 4112439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 4122439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 4132439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_FIFO_TX_DONE_PN (0x1FU << 0) 4142439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_FIFO_TEMPTY (0x1U << 7) 4152439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_FIFO_RX_DONE_PN (0x1FU << 8) 4162439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_FIFO_RXEMPTY (0x1U << 15) 4172439e4bfSJean-Christophe PLAGNIOL-VILLARD 4182439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 4192439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 4202439e4bfSJean-Christophe PLAGNIOL-VILLARD * Pointer Register - Bank 2 - Offset 6 4212439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 4222439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 4232439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_PTR_LOW (0xFFU << 0) 4242439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_PTR_HIGH (0x7U << 8) 4252439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_PTR_AUTO_TX (0x1U << 11) 4262439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_PTR_ETEN (0x1U << 12) 4272439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_PTR_READ (0x1U << 13) 4282439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_PTR_AUTO_INCR (0x1U << 14) 4292439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_PTR_RCV (0x1U << 15) 4302439e4bfSJean-Christophe PLAGNIOL-VILLARD 4312439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_PTR_RX_FRAME (LAN91C96_PTR_RCV | \ 4322439e4bfSJean-Christophe PLAGNIOL-VILLARD LAN91C96_PTR_AUTO_INCR | \ 4332439e4bfSJean-Christophe PLAGNIOL-VILLARD LAN91C96_PTR_READ) 4342439e4bfSJean-Christophe PLAGNIOL-VILLARD 4352439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 4362439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 4372439e4bfSJean-Christophe PLAGNIOL-VILLARD * Data Register - Bank 2 - Offset 8 4382439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 4392439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 4402439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_CONTROL_CRC (0x1U << 4) /* CRC bit */ 4412439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_CONTROL_ODD (0x1U << 5) /* ODD bit */ 4422439e4bfSJean-Christophe PLAGNIOL-VILLARD 4432439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 4442439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 4452439e4bfSJean-Christophe PLAGNIOL-VILLARD * Interrupt Status Register - Bank 2 - Offset 12 4462439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 4472439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 4482439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_IST_RCV_INT (0x1U << 0) 4492439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_IST_TX_INT (0x1U << 1) 4502439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_IST_TX_EMPTY_INT (0x1U << 2) 4512439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_IST_ALLOC_INT (0x1U << 3) 4522439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_IST_RX_OVRN_INT (0x1U << 4) 4532439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_IST_EPH_INT (0x1U << 5) 4542439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_IST_ERCV_INT (0x1U << 6) 4552439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_IST_RX_IDLE_INT (0x1U << 7) 4562439e4bfSJean-Christophe PLAGNIOL-VILLARD 4572439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 4582439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 4592439e4bfSJean-Christophe PLAGNIOL-VILLARD * Interrupt Acknowledge Register - Bank 2 - Offset 12 4602439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 4612439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 4622439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_ACK_TX_INT (0x1U << 1) 4632439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_ACK_TX_EMPTY_INT (0x1U << 2) 4642439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_ACK_RX_OVRN_INT (0x1U << 4) 4652439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_ACK_ERCV_INT (0x1U << 6) 4662439e4bfSJean-Christophe PLAGNIOL-VILLARD 4672439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 4682439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 4692439e4bfSJean-Christophe PLAGNIOL-VILLARD * Interrupt Mask Register - Bank 2 - Offset 13 4702439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 4712439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 4722439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MSK_RCV_INT (0x1U << 0) 4732439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MSK_TX_INT (0x1U << 1) 4742439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MSK_TX_EMPTY_INT (0x1U << 2) 4752439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MSK_ALLOC_INT (0x1U << 3) 4762439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MSK_RX_OVRN_INT (0x1U << 4) 4772439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MSK_EPH_INT (0x1U << 5) 4782439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MSK_ERCV_INT (0x1U << 6) 4792439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MSK_TX_IDLE_INT (0x1U << 7) 4802439e4bfSJean-Christophe PLAGNIOL-VILLARD 4812439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 4822439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 4832439e4bfSJean-Christophe PLAGNIOL-VILLARD * Bank 3 Register Map in I/O Space 4842439e4bfSJean-Christophe PLAGNIOL-VILLARD ************************************************************************** 4852439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 4862439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MGMT_MDO (0x1U << 0) 4872439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MGMT_MDI (0x1U << 1) 4882439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MGMT_MCLK (0x1U << 2) 4892439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MGMT_MDOE (0x1U << 3) 4902439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MGMT_LOW_ID (0x3U << 4) 4912439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MGMT_IOS0 (0x1U << 8) 4922439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MGMT_IOS1 (0x1U << 9) 4932439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MGMT_IOS2 (0x1U << 10) 4942439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MGMT_nXNDEC (0x1U << 11) 4952439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MGMT_HIGH_ID (0x3U << 12) 4962439e4bfSJean-Christophe PLAGNIOL-VILLARD 4972439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 4982439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 4992439e4bfSJean-Christophe PLAGNIOL-VILLARD * Revision Register - Bank 3 - Offset 10 5002439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 5012439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 5022439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_REV_REVID (0xFU << 0) 5032439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_REV_CHIPID (0xFU << 4) 5042439e4bfSJean-Christophe PLAGNIOL-VILLARD 5052439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 5062439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 5072439e4bfSJean-Christophe PLAGNIOL-VILLARD * Early RCV Register - Bank 3 - Offset 12 5082439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 5092439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 5102439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_ERCV_THRESHOLD (0x1FU << 0) 5112439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_ERCV_RCV_DISCRD (0x1U << 7) 5122439e4bfSJean-Christophe PLAGNIOL-VILLARD 5132439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 5142439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 5152439e4bfSJean-Christophe PLAGNIOL-VILLARD * PCMCIA Configuration Registers 5162439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 5172439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 5182439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_ECOR 0x8000 /* Ethernet Configuration Register */ 5192439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_ECSR 0x8002 /* Ethernet Configuration and Status */ 5202439e4bfSJean-Christophe PLAGNIOL-VILLARD 5212439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 5222439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 5232439e4bfSJean-Christophe PLAGNIOL-VILLARD * PCMCIA Ethernet Configuration Option Register (ECOR) 5242439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 5252439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 5262439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_ECOR_ENABLE (0x1U << 0) 5272439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_ECOR_WR_ATTRIB (0x1U << 2) 5282439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_ECOR_LEVEL_REQ (0x1U << 6) 5292439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_ECOR_SRESET (0x1U << 7) 5302439e4bfSJean-Christophe PLAGNIOL-VILLARD 5312439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 5322439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 5332439e4bfSJean-Christophe PLAGNIOL-VILLARD * PCMCIA Ethernet Configuration and Status Register (ECSR) 5342439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 5352439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 5362439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_ECSR_INTR (0x1U << 1) 5372439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_ECSR_PWRDWN (0x1U << 2) 5382439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_ECSR_IOIS8 (0x1U << 5) 5392439e4bfSJean-Christophe PLAGNIOL-VILLARD 5402439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 5412439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 5422439e4bfSJean-Christophe PLAGNIOL-VILLARD * Receive Frame Status Word - See page 38 of the LAN91C96 specification. 5432439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 5442439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 5452439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_TOO_SHORT (0x1U << 10) 5462439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_TOO_LONG (0x1U << 11) 5472439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_ODD_FRM (0x1U << 12) 5482439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_BAD_CRC (0x1U << 13) 5492439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_BROD_CAST (0x1U << 14) 5502439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_ALGN_ERR (0x1U << 15) 5512439e4bfSJean-Christophe PLAGNIOL-VILLARD 5522439e4bfSJean-Christophe PLAGNIOL-VILLARD #define FRAME_FILTER (LAN91C96_TOO_SHORT | LAN91C96_TOO_LONG | LAN91C96_BAD_CRC | LAN91C96_ALGN_ERR) 5532439e4bfSJean-Christophe PLAGNIOL-VILLARD 5542439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 5552439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 5562439e4bfSJean-Christophe PLAGNIOL-VILLARD * Default MAC Address 5572439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 5582439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 5592439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MAC_DEF_HI 0x0800 5602439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MAC_DEF_MED 0x3333 5612439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MAC_DEF_LO 0x0100 5622439e4bfSJean-Christophe PLAGNIOL-VILLARD 5632439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 5642439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 5652439e4bfSJean-Christophe PLAGNIOL-VILLARD * Default I/O Signature - 0x33 5662439e4bfSJean-Christophe PLAGNIOL-VILLARD **************************************************************************** 5672439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 5682439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_LOW_SIGNATURE (0x33U << 0) 5692439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_HIGH_SIGNATURE (0x33U << 8) 5702439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_SIGNATURE (LAN91C96_HIGH_SIGNATURE | LAN91C96_LOW_SIGNATURE) 5712439e4bfSJean-Christophe PLAGNIOL-VILLARD 5722439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LAN91C96_MAX_PAGES 6 /* Maximum number of 256 pages. */ 5732439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ETHERNET_MAX_LENGTH 1514 5742439e4bfSJean-Christophe PLAGNIOL-VILLARD 5752439e4bfSJean-Christophe PLAGNIOL-VILLARD 5762439e4bfSJean-Christophe PLAGNIOL-VILLARD /*------------------------------------------------------------------------- 5772439e4bfSJean-Christophe PLAGNIOL-VILLARD * I define some macros to make it easier to do somewhat common 5782439e4bfSJean-Christophe PLAGNIOL-VILLARD * or slightly complicated, repeated tasks. 5792439e4bfSJean-Christophe PLAGNIOL-VILLARD *------------------------------------------------------------------------- 5802439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 5812439e4bfSJean-Christophe PLAGNIOL-VILLARD 5822439e4bfSJean-Christophe PLAGNIOL-VILLARD /* select a register bank, 0 to 3 */ 5832439e4bfSJean-Christophe PLAGNIOL-VILLARD 584b7ad4109SNishanth Menon #define SMC_SELECT_BANK(edev, x) { SMC_outw(edev, x, LAN91C96_BANK_SELECT); } 5852439e4bfSJean-Christophe PLAGNIOL-VILLARD 5862439e4bfSJean-Christophe PLAGNIOL-VILLARD /* this enables an interrupt in the interrupt mask register */ 587b7ad4109SNishanth Menon #define SMC_ENABLE_INT(edev, x) {\ 5882439e4bfSJean-Christophe PLAGNIOL-VILLARD unsigned char mask;\ 589b7ad4109SNishanth Menon SMC_SELECT_BANK(edev, 2);\ 590b7ad4109SNishanth Menon mask = SMC_inb(edev, LAN91C96_INT_MASK);\ 5912439e4bfSJean-Christophe PLAGNIOL-VILLARD mask |= (x);\ 592b7ad4109SNishanth Menon SMC_outb(edev, mask, LAN91C96_INT_MASK); \ 5932439e4bfSJean-Christophe PLAGNIOL-VILLARD } 5942439e4bfSJean-Christophe PLAGNIOL-VILLARD 5952439e4bfSJean-Christophe PLAGNIOL-VILLARD /* this disables an interrupt from the interrupt mask register */ 5962439e4bfSJean-Christophe PLAGNIOL-VILLARD 597b7ad4109SNishanth Menon #define SMC_DISABLE_INT(edev, x) {\ 5982439e4bfSJean-Christophe PLAGNIOL-VILLARD unsigned char mask;\ 599b7ad4109SNishanth Menon SMC_SELECT_BANK(edev, 2);\ 600b7ad4109SNishanth Menon mask = SMC_inb(edev, LAN91C96_INT_MASK);\ 6012439e4bfSJean-Christophe PLAGNIOL-VILLARD mask &= ~(x);\ 602b7ad4109SNishanth Menon SMC_outb(edev, mask, LAN91C96_INT_MASK); \ 6032439e4bfSJean-Christophe PLAGNIOL-VILLARD } 6042439e4bfSJean-Christophe PLAGNIOL-VILLARD 6052439e4bfSJean-Christophe PLAGNIOL-VILLARD /*---------------------------------------------------------------------- 6062439e4bfSJean-Christophe PLAGNIOL-VILLARD * Define the interrupts that I want to receive from the card 6072439e4bfSJean-Christophe PLAGNIOL-VILLARD * 6082439e4bfSJean-Christophe PLAGNIOL-VILLARD * I want: 6092439e4bfSJean-Christophe PLAGNIOL-VILLARD * LAN91C96_IST_EPH_INT, for nasty errors 6102439e4bfSJean-Christophe PLAGNIOL-VILLARD * LAN91C96_IST_RCV_INT, for happy received packets 6112439e4bfSJean-Christophe PLAGNIOL-VILLARD * LAN91C96_IST_RX_OVRN_INT, because I have to kick the receiver 6122439e4bfSJean-Christophe PLAGNIOL-VILLARD *------------------------------------------------------------------------- 6132439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 6142439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_INTERRUPT_MASK (LAN91C96_IST_EPH_INT | LAN91C96_IST_RX_OVRN_INT | LAN91C96_IST_RCV_INT) 6152439e4bfSJean-Christophe PLAGNIOL-VILLARD 6162439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif /* _LAN91C96_H_ */ 617