1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Micrel KS8851_MLL 16bit Network driver
4 * Copyright (c) 2011 Roberto Cerati <roberto.cerati@bticino.it>
5 */
6
7 #include <asm/io.h>
8 #include <common.h>
9 #include <command.h>
10 #include <malloc.h>
11 #include <net.h>
12 #include <miiphy.h>
13
14 #include "ks8851_mll.h"
15
16 #define DRIVERNAME "ks8851_mll"
17
18 #define MAX_RECV_FRAMES 32
19 #define MAX_BUF_SIZE 2048
20 #define TX_BUF_SIZE 2000
21 #define RX_BUF_SIZE 2000
22
23 static const struct chip_id chip_ids[] = {
24 {CIDER_ID, "KSZ8851"},
25 {0, NULL},
26 };
27
28 /*
29 * union ks_tx_hdr - tx header data
30 * @txb: The header as bytes
31 * @txw: The header as 16bit, little-endian words
32 *
33 * A dual representation of the tx header data to allow
34 * access to individual bytes, and to allow 16bit accesses
35 * with 16bit alignment.
36 */
37 union ks_tx_hdr {
38 u8 txb[4];
39 __le16 txw[2];
40 };
41
42 /*
43 * struct ks_net - KS8851 driver private data
44 * @net_device : The network device we're bound to
45 * @txh : temporaly buffer to save status/length.
46 * @frame_head_info : frame header information for multi-pkt rx.
47 * @statelock : Lock on this structure for tx list.
48 * @msg_enable : The message flags controlling driver output (see ethtool).
49 * @frame_cnt : number of frames received.
50 * @bus_width : i/o bus width.
51 * @irq : irq number assigned to this device.
52 * @rc_rxqcr : Cached copy of KS_RXQCR.
53 * @rc_txcr : Cached copy of KS_TXCR.
54 * @rc_ier : Cached copy of KS_IER.
55 * @sharedbus : Multipex(addr and data bus) mode indicator.
56 * @cmd_reg_cache : command register cached.
57 * @cmd_reg_cache_int : command register cached. Used in the irq handler.
58 * @promiscuous : promiscuous mode indicator.
59 * @all_mcast : mutlicast indicator.
60 * @mcast_lst_size : size of multicast list.
61 * @mcast_lst : multicast list.
62 * @mcast_bits : multicast enabed.
63 * @mac_addr : MAC address assigned to this device.
64 * @fid : frame id.
65 * @extra_byte : number of extra byte prepended rx pkt.
66 * @enabled : indicator this device works.
67 */
68
69 /* Receive multiplex framer header info */
70 struct type_frame_head {
71 u16 sts; /* Frame status */
72 u16 len; /* Byte count */
73 } fr_h_i[MAX_RECV_FRAMES];
74
75 struct ks_net {
76 struct net_device *netdev;
77 union ks_tx_hdr txh;
78 struct type_frame_head *frame_head_info;
79 u32 msg_enable;
80 u32 frame_cnt;
81 int bus_width;
82 int irq;
83 u16 rc_rxqcr;
84 u16 rc_txcr;
85 u16 rc_ier;
86 u16 sharedbus;
87 u16 cmd_reg_cache;
88 u16 cmd_reg_cache_int;
89 u16 promiscuous;
90 u16 all_mcast;
91 u16 mcast_lst_size;
92 u8 mcast_lst[MAX_MCAST_LST][MAC_ADDR_LEN];
93 u8 mcast_bits[HW_MCAST_SIZE];
94 u8 mac_addr[6];
95 u8 fid;
96 u8 extra_byte;
97 u8 enabled;
98 } ks_str, *ks;
99
100 #define BE3 0x8000 /* Byte Enable 3 */
101 #define BE2 0x4000 /* Byte Enable 2 */
102 #define BE1 0x2000 /* Byte Enable 1 */
103 #define BE0 0x1000 /* Byte Enable 0 */
104
ks_rdreg8(struct eth_device * dev,u16 offset)105 static u8 ks_rdreg8(struct eth_device *dev, u16 offset)
106 {
107 u8 shift_bit = offset & 0x03;
108 u8 shift_data = (offset & 1) << 3;
109
110 writew(offset | (BE0 << shift_bit), dev->iobase + 2);
111
112 return (u8)(readw(dev->iobase) >> shift_data);
113 }
114
ks_rdreg16(struct eth_device * dev,u16 offset)115 static u16 ks_rdreg16(struct eth_device *dev, u16 offset)
116 {
117 writew(offset | ((BE1 | BE0) << (offset & 0x02)), dev->iobase + 2);
118
119 return readw(dev->iobase);
120 }
121
ks_wrreg8(struct eth_device * dev,u16 offset,u8 val)122 static void ks_wrreg8(struct eth_device *dev, u16 offset, u8 val)
123 {
124 u8 shift_bit = (offset & 0x03);
125 u16 value_write = (u16)(val << ((offset & 1) << 3));
126
127 writew(offset | (BE0 << shift_bit), dev->iobase + 2);
128 writew(value_write, dev->iobase);
129 }
130
ks_wrreg16(struct eth_device * dev,u16 offset,u16 val)131 static void ks_wrreg16(struct eth_device *dev, u16 offset, u16 val)
132 {
133 writew(offset | ((BE1 | BE0) << (offset & 0x02)), dev->iobase + 2);
134 writew(val, dev->iobase);
135 }
136
137 /*
138 * ks_inblk - read a block of data from QMU. This is called after sudo DMA mode
139 * enabled.
140 * @ks: The chip state
141 * @wptr: buffer address to save data
142 * @len: length in byte to read
143 */
ks_inblk(struct eth_device * dev,u16 * wptr,u32 len)144 static inline void ks_inblk(struct eth_device *dev, u16 *wptr, u32 len)
145 {
146 len >>= 1;
147
148 while (len--)
149 *wptr++ = readw(dev->iobase);
150 }
151
152 /*
153 * ks_outblk - write data to QMU. This is called after sudo DMA mode enabled.
154 * @ks: The chip information
155 * @wptr: buffer address
156 * @len: length in byte to write
157 */
ks_outblk(struct eth_device * dev,u16 * wptr,u32 len)158 static inline void ks_outblk(struct eth_device *dev, u16 *wptr, u32 len)
159 {
160 len >>= 1;
161
162 while (len--)
163 writew(*wptr++, dev->iobase);
164 }
165
ks_enable_int(struct eth_device * dev)166 static void ks_enable_int(struct eth_device *dev)
167 {
168 ks_wrreg16(dev, KS_IER, ks->rc_ier);
169 }
170
ks_set_powermode(struct eth_device * dev,unsigned pwrmode)171 static void ks_set_powermode(struct eth_device *dev, unsigned pwrmode)
172 {
173 unsigned pmecr;
174
175 ks_rdreg16(dev, KS_GRR);
176 pmecr = ks_rdreg16(dev, KS_PMECR);
177 pmecr &= ~PMECR_PM_MASK;
178 pmecr |= pwrmode;
179
180 ks_wrreg16(dev, KS_PMECR, pmecr);
181 }
182
183 /*
184 * ks_read_config - read chip configuration of bus width.
185 * @ks: The chip information
186 */
ks_read_config(struct eth_device * dev)187 static void ks_read_config(struct eth_device *dev)
188 {
189 u16 reg_data = 0;
190
191 /* Regardless of bus width, 8 bit read should always work. */
192 reg_data = ks_rdreg8(dev, KS_CCR) & 0x00FF;
193 reg_data |= ks_rdreg8(dev, KS_CCR + 1) << 8;
194
195 /* addr/data bus are multiplexed */
196 ks->sharedbus = (reg_data & CCR_SHARED) == CCR_SHARED;
197
198 /*
199 * There are garbage data when reading data from QMU,
200 * depending on bus-width.
201 */
202 if (reg_data & CCR_8BIT) {
203 ks->bus_width = ENUM_BUS_8BIT;
204 ks->extra_byte = 1;
205 } else if (reg_data & CCR_16BIT) {
206 ks->bus_width = ENUM_BUS_16BIT;
207 ks->extra_byte = 2;
208 } else {
209 ks->bus_width = ENUM_BUS_32BIT;
210 ks->extra_byte = 4;
211 }
212 }
213
214 /*
215 * ks_soft_reset - issue one of the soft reset to the device
216 * @ks: The device state.
217 * @op: The bit(s) to set in the GRR
218 *
219 * Issue the relevant soft-reset command to the device's GRR register
220 * specified by @op.
221 *
222 * Note, the delays are in there as a caution to ensure that the reset
223 * has time to take effect and then complete. Since the datasheet does
224 * not currently specify the exact sequence, we have chosen something
225 * that seems to work with our device.
226 */
ks_soft_reset(struct eth_device * dev,unsigned op)227 static void ks_soft_reset(struct eth_device *dev, unsigned op)
228 {
229 /* Disable interrupt first */
230 ks_wrreg16(dev, KS_IER, 0x0000);
231 ks_wrreg16(dev, KS_GRR, op);
232 mdelay(10); /* wait a short time to effect reset */
233 ks_wrreg16(dev, KS_GRR, 0);
234 mdelay(1); /* wait for condition to clear */
235 }
236
ks_enable_qmu(struct eth_device * dev)237 void ks_enable_qmu(struct eth_device *dev)
238 {
239 u16 w;
240
241 w = ks_rdreg16(dev, KS_TXCR);
242
243 /* Enables QMU Transmit (TXCR). */
244 ks_wrreg16(dev, KS_TXCR, w | TXCR_TXE);
245
246 /* Enable RX Frame Count Threshold and Auto-Dequeue RXQ Frame */
247 w = ks_rdreg16(dev, KS_RXQCR);
248 ks_wrreg16(dev, KS_RXQCR, w | RXQCR_RXFCTE);
249
250 /* Enables QMU Receive (RXCR1). */
251 w = ks_rdreg16(dev, KS_RXCR1);
252 ks_wrreg16(dev, KS_RXCR1, w | RXCR1_RXE);
253 }
254
ks_disable_qmu(struct eth_device * dev)255 static void ks_disable_qmu(struct eth_device *dev)
256 {
257 u16 w;
258
259 w = ks_rdreg16(dev, KS_TXCR);
260
261 /* Disables QMU Transmit (TXCR). */
262 w &= ~TXCR_TXE;
263 ks_wrreg16(dev, KS_TXCR, w);
264
265 /* Disables QMU Receive (RXCR1). */
266 w = ks_rdreg16(dev, KS_RXCR1);
267 w &= ~RXCR1_RXE;
268 ks_wrreg16(dev, KS_RXCR1, w);
269 }
270
ks_read_qmu(struct eth_device * dev,u16 * buf,u32 len)271 static inline void ks_read_qmu(struct eth_device *dev, u16 *buf, u32 len)
272 {
273 u32 r = ks->extra_byte & 0x1;
274 u32 w = ks->extra_byte - r;
275
276 /* 1. set sudo DMA mode */
277 ks_wrreg16(dev, KS_RXFDPR, RXFDPR_RXFPAI);
278 ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff);
279
280 /*
281 * 2. read prepend data
282 *
283 * read 4 + extra bytes and discard them.
284 * extra bytes for dummy, 2 for status, 2 for len
285 */
286
287 if (r)
288 ks_rdreg8(dev, 0);
289
290 ks_inblk(dev, buf, w + 2 + 2);
291
292 /* 3. read pkt data */
293 ks_inblk(dev, buf, ALIGN(len, 4));
294
295 /* 4. reset sudo DMA Mode */
296 ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr & ~RXQCR_SDA) & 0xff);
297 }
298
ks_rcv(struct eth_device * dev,uchar ** pv_data)299 static void ks_rcv(struct eth_device *dev, uchar **pv_data)
300 {
301 struct type_frame_head *frame_hdr = ks->frame_head_info;
302 int i;
303
304 ks->frame_cnt = ks_rdreg16(dev, KS_RXFCTR) >> 8;
305
306 /* read all header information */
307 for (i = 0; i < ks->frame_cnt; i++) {
308 /* Checking Received packet status */
309 frame_hdr->sts = ks_rdreg16(dev, KS_RXFHSR);
310 /* Get packet len from hardware */
311 frame_hdr->len = ks_rdreg16(dev, KS_RXFHBCR);
312 frame_hdr++;
313 }
314
315 frame_hdr = ks->frame_head_info;
316 while (ks->frame_cnt--) {
317 if ((frame_hdr->sts & RXFSHR_RXFV) &&
318 (frame_hdr->len < RX_BUF_SIZE) &&
319 frame_hdr->len) {
320 /* read data block including CRC 4 bytes */
321 ks_read_qmu(dev, (u16 *)(*pv_data), frame_hdr->len);
322
323 /* net_rx_packets buffer size is ok (*pv_data) */
324 net_process_received_packet(*pv_data, frame_hdr->len);
325 pv_data++;
326 } else {
327 ks_wrreg16(dev, KS_RXQCR, (ks->rc_rxqcr | RXQCR_RRXEF));
328 printf(DRIVERNAME ": bad packet\n");
329 }
330 frame_hdr++;
331 }
332 }
333
334 /*
335 * ks_read_selftest - read the selftest memory info.
336 * @ks: The device state
337 *
338 * Read and check the TX/RX memory selftest information.
339 */
ks_read_selftest(struct eth_device * dev)340 static int ks_read_selftest(struct eth_device *dev)
341 {
342 u16 both_done = MBIR_TXMBF | MBIR_RXMBF;
343 u16 mbir;
344 int ret = 0;
345
346 mbir = ks_rdreg16(dev, KS_MBIR);
347
348 if ((mbir & both_done) != both_done) {
349 printf(DRIVERNAME ": Memory selftest not finished\n");
350 return 0;
351 }
352
353 if (mbir & MBIR_TXMBFA) {
354 printf(DRIVERNAME ": TX memory selftest fails\n");
355 ret |= 1;
356 }
357
358 if (mbir & MBIR_RXMBFA) {
359 printf(DRIVERNAME ": RX memory selftest fails\n");
360 ret |= 2;
361 }
362
363 debug(DRIVERNAME ": the selftest passes\n");
364
365 return ret;
366 }
367
ks_setup(struct eth_device * dev)368 static void ks_setup(struct eth_device *dev)
369 {
370 u16 w;
371
372 /* Setup Transmit Frame Data Pointer Auto-Increment (TXFDPR) */
373 ks_wrreg16(dev, KS_TXFDPR, TXFDPR_TXFPAI);
374
375 /* Setup Receive Frame Data Pointer Auto-Increment */
376 ks_wrreg16(dev, KS_RXFDPR, RXFDPR_RXFPAI);
377
378 /* Setup Receive Frame Threshold - 1 frame (RXFCTFC) */
379 ks_wrreg16(dev, KS_RXFCTR, 1 & RXFCTR_THRESHOLD_MASK);
380
381 /* Setup RxQ Command Control (RXQCR) */
382 ks->rc_rxqcr = RXQCR_CMD_CNTL;
383 ks_wrreg16(dev, KS_RXQCR, ks->rc_rxqcr);
384
385 /*
386 * set the force mode to half duplex, default is full duplex
387 * because if the auto-negotiation fails, most switch uses
388 * half-duplex.
389 */
390 w = ks_rdreg16(dev, KS_P1MBCR);
391 w &= ~P1MBCR_FORCE_FDX;
392 ks_wrreg16(dev, KS_P1MBCR, w);
393
394 w = TXCR_TXFCE | TXCR_TXPE | TXCR_TXCRC | TXCR_TCGIP;
395 ks_wrreg16(dev, KS_TXCR, w);
396
397 w = RXCR1_RXFCE | RXCR1_RXBE | RXCR1_RXUE | RXCR1_RXME | RXCR1_RXIPFCC;
398
399 /* Normal mode */
400 w |= RXCR1_RXPAFMA;
401
402 ks_wrreg16(dev, KS_RXCR1, w);
403 }
404
ks_setup_int(struct eth_device * dev)405 static void ks_setup_int(struct eth_device *dev)
406 {
407 ks->rc_ier = 0x00;
408
409 /* Clear the interrupts status of the hardware. */
410 ks_wrreg16(dev, KS_ISR, 0xffff);
411
412 /* Enables the interrupts of the hardware. */
413 ks->rc_ier = (IRQ_LCI | IRQ_TXI | IRQ_RXI);
414 }
415
ks8851_mll_detect_chip(struct eth_device * dev)416 static int ks8851_mll_detect_chip(struct eth_device *dev)
417 {
418 unsigned short val, i;
419
420 ks_read_config(dev);
421
422 val = ks_rdreg16(dev, KS_CIDER);
423
424 if (val == 0xffff) {
425 /* Special case -- no chip present */
426 printf(DRIVERNAME ": is chip mounted ?\n");
427 return -1;
428 } else if ((val & 0xfff0) != CIDER_ID) {
429 printf(DRIVERNAME ": Invalid chip id 0x%04x\n", val);
430 return -1;
431 }
432
433 debug("Read back KS8851 id 0x%x\n", val);
434
435 /* only one entry in the table */
436 val &= 0xfff0;
437 for (i = 0; chip_ids[i].id != 0; i++) {
438 if (chip_ids[i].id == val)
439 break;
440 }
441 if (!chip_ids[i].id) {
442 printf(DRIVERNAME ": Unknown chip ID %04x\n", val);
443 return -1;
444 }
445
446 dev->priv = (void *)&chip_ids[i];
447
448 return 0;
449 }
450
ks8851_mll_reset(struct eth_device * dev)451 static void ks8851_mll_reset(struct eth_device *dev)
452 {
453 /* wake up powermode to normal mode */
454 ks_set_powermode(dev, PMECR_PM_NORMAL);
455 mdelay(1); /* wait for normal mode to take effect */
456
457 /* Disable interrupt and reset */
458 ks_soft_reset(dev, GRR_GSR);
459
460 /* turn off the IRQs and ack any outstanding */
461 ks_wrreg16(dev, KS_IER, 0x0000);
462 ks_wrreg16(dev, KS_ISR, 0xffff);
463
464 /* shutdown RX/TX QMU */
465 ks_disable_qmu(dev);
466 }
467
ks8851_mll_phy_configure(struct eth_device * dev)468 static void ks8851_mll_phy_configure(struct eth_device *dev)
469 {
470 u16 data;
471
472 ks_setup(dev);
473 ks_setup_int(dev);
474
475 /* Probing the phy */
476 data = ks_rdreg16(dev, KS_OBCR);
477 ks_wrreg16(dev, KS_OBCR, data | OBCR_ODS_16MA);
478
479 debug(DRIVERNAME ": phy initialized\n");
480 }
481
ks8851_mll_enable(struct eth_device * dev)482 static void ks8851_mll_enable(struct eth_device *dev)
483 {
484 ks_wrreg16(dev, KS_ISR, 0xffff);
485 ks_enable_int(dev);
486 ks_enable_qmu(dev);
487 }
488
ks8851_mll_init(struct eth_device * dev,bd_t * bd)489 static int ks8851_mll_init(struct eth_device *dev, bd_t *bd)
490 {
491 struct chip_id *id = dev->priv;
492
493 debug(DRIVERNAME ": detected %s controller\n", id->name);
494
495 if (ks_read_selftest(dev)) {
496 printf(DRIVERNAME ": Selftest failed\n");
497 return -1;
498 }
499
500 ks8851_mll_reset(dev);
501
502 /* Configure the PHY, initialize the link state */
503 ks8851_mll_phy_configure(dev);
504
505 /* static allocation of private informations */
506 ks->frame_head_info = fr_h_i;
507
508 /* Turn on Tx + Rx */
509 ks8851_mll_enable(dev);
510
511 return 0;
512 }
513
ks_write_qmu(struct eth_device * dev,u8 * pdata,u16 len)514 static void ks_write_qmu(struct eth_device *dev, u8 *pdata, u16 len)
515 {
516 /* start header at txb[0] to align txw entries */
517 ks->txh.txw[0] = 0;
518 ks->txh.txw[1] = cpu_to_le16(len);
519
520 /* 1. set sudo-DMA mode */
521 ks_wrreg16(dev, KS_TXFDPR, TXFDPR_TXFPAI);
522 ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff);
523 /* 2. write status/lenth info */
524 ks_outblk(dev, ks->txh.txw, 4);
525 /* 3. write pkt data */
526 ks_outblk(dev, (u16 *)pdata, ALIGN(len, 4));
527 /* 4. reset sudo-DMA mode */
528 ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr & ~RXQCR_SDA) & 0xff);
529 /* 5. Enqueue Tx(move the pkt from TX buffer into TXQ) */
530 ks_wrreg16(dev, KS_TXQCR, TXQCR_METFE);
531 /* 6. wait until TXQCR_METFE is auto-cleared */
532 do { } while (ks_rdreg16(dev, KS_TXQCR) & TXQCR_METFE);
533 }
534
ks8851_mll_send(struct eth_device * dev,void * packet,int length)535 static int ks8851_mll_send(struct eth_device *dev, void *packet, int length)
536 {
537 u8 *data = (u8 *)packet;
538 u16 tmplen = (u16)length;
539 u16 retv;
540
541 /*
542 * Extra space are required:
543 * 4 byte for alignment, 4 for status/length, 4 for CRC
544 */
545 retv = ks_rdreg16(dev, KS_TXMIR) & 0x1fff;
546 if (retv >= tmplen + 12) {
547 ks_write_qmu(dev, data, tmplen);
548 return 0;
549 } else {
550 printf(DRIVERNAME ": failed to send packet: No buffer\n");
551 return -1;
552 }
553 }
554
ks8851_mll_halt(struct eth_device * dev)555 static void ks8851_mll_halt(struct eth_device *dev)
556 {
557 ks8851_mll_reset(dev);
558 }
559
560 /*
561 * Maximum receive ring size; that is, the number of packets
562 * we can buffer before overflow happens. Basically, this just
563 * needs to be enough to prevent a packet being discarded while
564 * we are processing the previous one.
565 */
ks8851_mll_recv(struct eth_device * dev)566 static int ks8851_mll_recv(struct eth_device *dev)
567 {
568 u16 status;
569
570 status = ks_rdreg16(dev, KS_ISR);
571
572 ks_wrreg16(dev, KS_ISR, status);
573
574 if ((status & IRQ_RXI))
575 ks_rcv(dev, (uchar **)net_rx_packets);
576
577 if ((status & IRQ_LDI)) {
578 u16 pmecr = ks_rdreg16(dev, KS_PMECR);
579 pmecr &= ~PMECR_WKEVT_MASK;
580 ks_wrreg16(dev, KS_PMECR, pmecr | PMECR_WKEVT_LINK);
581 }
582
583 return 0;
584 }
585
ks8851_mll_write_hwaddr(struct eth_device * dev)586 static int ks8851_mll_write_hwaddr(struct eth_device *dev)
587 {
588 u16 addrl, addrm, addrh;
589
590 addrh = (dev->enetaddr[0] << 8) | dev->enetaddr[1];
591 addrm = (dev->enetaddr[2] << 8) | dev->enetaddr[3];
592 addrl = (dev->enetaddr[4] << 8) | dev->enetaddr[5];
593
594 ks_wrreg16(dev, KS_MARH, addrh);
595 ks_wrreg16(dev, KS_MARM, addrm);
596 ks_wrreg16(dev, KS_MARL, addrl);
597
598 return 0;
599 }
600
ks8851_mll_initialize(u8 dev_num,int base_addr)601 int ks8851_mll_initialize(u8 dev_num, int base_addr)
602 {
603 struct eth_device *dev;
604
605 dev = malloc(sizeof(*dev));
606 if (!dev) {
607 printf("Error: Failed to allocate memory\n");
608 return -1;
609 }
610 memset(dev, 0, sizeof(*dev));
611
612 dev->iobase = base_addr;
613
614 ks = &ks_str;
615
616 /* Try to detect chip. Will fail if not present. */
617 if (ks8851_mll_detect_chip(dev)) {
618 free(dev);
619 return -1;
620 }
621
622 dev->init = ks8851_mll_init;
623 dev->halt = ks8851_mll_halt;
624 dev->send = ks8851_mll_send;
625 dev->recv = ks8851_mll_recv;
626 dev->write_hwaddr = ks8851_mll_write_hwaddr;
627 sprintf(dev->name, "%s-%hu", DRIVERNAME, dev_num);
628
629 eth_register(dev);
630
631 return 0;
632 }
633