1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Faraday 10/100Mbps Ethernet Controller 4 * 5 * (C) Copyright 2013 Faraday Technology 6 * Dante Su <dantesu@faraday-tech.com> 7 */ 8 9 #ifndef _FTMAC110_H 10 #define _FTMAC110_H 11 12 struct ftmac110_regs { 13 uint32_t isr; /* 0x00: Interrups Status Register */ 14 uint32_t imr; /* 0x04: Interrupt Mask Register */ 15 uint32_t mac[2]; /* 0x08: MAC Address */ 16 uint32_t mht[2]; /* 0x10: Multicast Hash Table Register */ 17 uint32_t txpd; /* 0x18: Tx Poll Demand Register */ 18 uint32_t rxpd; /* 0x1c: Rx Poll Demand Register */ 19 uint32_t txba; /* 0x20: Tx Ring Base Address Register */ 20 uint32_t rxba; /* 0x24: Rx Ring Base Address Register */ 21 uint32_t itc; /* 0x28: Interrupt Timer Control Register */ 22 uint32_t aptc; /* 0x2C: Automatic Polling Timer Control Register */ 23 uint32_t dblac; /* 0x30: DMA Burst Length&Arbitration Control */ 24 uint32_t revr; /* 0x34: Revision Register */ 25 uint32_t fear; /* 0x38: Feature Register */ 26 uint32_t rsvd[19]; 27 uint32_t maccr; /* 0x88: MAC Control Register */ 28 uint32_t macsr; /* 0x8C: MAC Status Register */ 29 uint32_t phycr; /* 0x90: PHY Control Register */ 30 uint32_t phydr; /* 0x94: PHY Data Register */ 31 uint32_t fcr; /* 0x98: Flow Control Register */ 32 uint32_t bpr; /* 0x9C: Back Pressure Register */ 33 }; 34 35 /* 36 * Interrupt status/mask register(ISR/IMR) bits 37 */ 38 #define ISR_ALL 0x3ff 39 #define ISR_PHYSTCHG (1 << 9) /* phy status change */ 40 #define ISR_AHBERR (1 << 8) /* bus error */ 41 #define ISR_RXLOST (1 << 7) /* rx lost */ 42 #define ISR_RXFIFO (1 << 6) /* rx to fifo */ 43 #define ISR_TXLOST (1 << 5) /* tx lost */ 44 #define ISR_TXOK (1 << 4) /* tx to ethernet */ 45 #define ISR_NOTXBUF (1 << 3) /* out of tx buffer */ 46 #define ISR_TXFIFO (1 << 2) /* tx to fifo */ 47 #define ISR_NORXBUF (1 << 1) /* out of rx buffer */ 48 #define ISR_RXOK (1 << 0) /* rx to buffer */ 49 50 /* 51 * MACCR control bits 52 */ 53 #define MACCR_100M (1 << 18) /* 100Mbps mode */ 54 #define MACCR_RXBCST (1 << 17) /* rx broadcast packet */ 55 #define MACCR_RXMCST (1 << 16) /* rx multicast packet */ 56 #define MACCR_FD (1 << 15) /* full duplex */ 57 #define MACCR_CRCAPD (1 << 14) /* tx crc append */ 58 #define MACCR_RXALL (1 << 12) /* rx all packets */ 59 #define MACCR_RXFTL (1 << 11) /* rx packet even it's > 1518 byte */ 60 #define MACCR_RXRUNT (1 << 10) /* rx packet even it's < 64 byte */ 61 #define MACCR_RXMCSTHT (1 << 9) /* rx multicast hash table */ 62 #define MACCR_RXEN (1 << 8) /* rx enable */ 63 #define MACCR_RXINHDTX (1 << 6) /* rx in half duplex tx */ 64 #define MACCR_TXEN (1 << 5) /* tx enable */ 65 #define MACCR_CRCDIS (1 << 4) /* tx packet even it's crc error */ 66 #define MACCR_LOOPBACK (1 << 3) /* loop-back */ 67 #define MACCR_RESET (1 << 2) /* reset */ 68 #define MACCR_RXDMAEN (1 << 1) /* rx dma enable */ 69 #define MACCR_TXDMAEN (1 << 0) /* tx dma enable */ 70 71 /* 72 * PHYCR control bits 73 */ 74 #define PHYCR_READ (1 << 26) 75 #define PHYCR_WRITE (1 << 27) 76 #define PHYCR_REG_SHIFT 21 77 #define PHYCR_ADDR_SHIFT 16 78 79 /* 80 * ITC control bits 81 */ 82 83 /* Tx Cycle Length */ 84 #define ITC_TX_CYCLONG (1 << 15) /* 100Mbps=81.92us; 10Mbps=819.2us */ 85 #define ITC_TX_CYCNORM (0 << 15) /* 100Mbps=5.12us; 10Mbps=51.2us */ 86 /* Tx Threshold: Aggregate n interrupts as 1 interrupt */ 87 #define ITC_TX_THR(n) (((n) & 0x7) << 12) 88 /* Tx Interrupt Timeout = n * Tx Cycle */ 89 #define ITC_TX_ITMO(n) (((n) & 0xf) << 8) 90 /* Rx Cycle Length */ 91 #define ITC_RX_CYCLONG (1 << 7) /* 100Mbps=81.92us; 10Mbps=819.2us */ 92 #define ITC_RX_CYCNORM (0 << 7) /* 100Mbps=5.12us; 10Mbps=51.2us */ 93 /* Rx Threshold: Aggregate n interrupts as 1 interrupt */ 94 #define ITC_RX_THR(n) (((n) & 0x7) << 4) 95 /* Rx Interrupt Timeout = n * Rx Cycle */ 96 #define ITC_RX_ITMO(n) (((n) & 0xf) << 0) 97 98 #define ITC_DEFAULT \ 99 (ITC_TX_THR(1) | ITC_TX_ITMO(0) | ITC_RX_THR(1) | ITC_RX_ITMO(0)) 100 101 /* 102 * APTC contrl bits 103 */ 104 105 /* Tx Cycle Length */ 106 #define APTC_TX_CYCLONG (1 << 12) /* 100Mbps=81.92us; 10Mbps=819.2us */ 107 #define APTC_TX_CYCNORM (0 << 12) /* 100Mbps=5.12us; 10Mbps=51.2us */ 108 /* Tx Poll Timeout = n * Tx Cycle, 0=No auto polling */ 109 #define APTC_TX_PTMO(n) (((n) & 0xf) << 8) 110 /* Rx Cycle Length */ 111 #define APTC_RX_CYCLONG (1 << 4) /* 100Mbps=81.92us; 10Mbps=819.2us */ 112 #define APTC_RX_CYCNORM (0 << 4) /* 100Mbps=5.12us; 10Mbps=51.2us */ 113 /* Rx Poll Timeout = n * Rx Cycle, 0=No auto polling */ 114 #define APTC_RX_PTMO(n) (((n) & 0xf) << 0) 115 116 #define APTC_DEFAULT (APTC_TX_PTMO(0) | APTC_RX_PTMO(1)) 117 118 /* 119 * DBLAC contrl bits 120 */ 121 #define DBLAC_BURST_MAX_ANY (0 << 14) /* un-limited */ 122 #define DBLAC_BURST_MAX_32X4 (2 << 14) /* max = 32 x 4 bytes */ 123 #define DBLAC_BURST_MAX_64X4 (3 << 14) /* max = 64 x 4 bytes */ 124 #define DBLAC_RXTHR_EN (1 << 9) /* enable rx threshold arbitration */ 125 #define DBLAC_RXTHR_HIGH(n) (((n) & 0x7) << 6) /* upper bound = n/8 fifo */ 126 #define DBLAC_RXTHR_LOW(n) (((n) & 0x7) << 3) /* lower bound = n/8 fifo */ 127 #define DBLAC_BURST_CAP16 (1 << 2) /* support burst 16 */ 128 #define DBLAC_BURST_CAP8 (1 << 1) /* support burst 8 */ 129 #define DBLAC_BURST_CAP4 (1 << 0) /* support burst 4 */ 130 131 #define DBLAC_DEFAULT \ 132 (DBLAC_RXTHR_EN | DBLAC_RXTHR_HIGH(6) | DBLAC_RXTHR_LOW(2)) 133 134 /* 135 * descriptor structure 136 */ 137 struct ftmac110_desc { 138 uint64_t ctrl; 139 uint32_t pbuf; 140 void *vbuf; 141 }; 142 143 #define FTMAC110_RXD_END ((uint64_t)1 << 63) 144 #define FTMAC110_RXD_BUFSZ(x) (((uint64_t)(x) & 0x7ff) << 32) 145 146 #define FTMAC110_RXD_OWNER ((uint64_t)1 << 31) /* owner: 1=HW, 0=SW */ 147 #define FTMAC110_RXD_FRS ((uint64_t)1 << 29) /* first pkt desc */ 148 #define FTMAC110_RXD_LRS ((uint64_t)1 << 28) /* last pkt desc */ 149 #define FTMAC110_RXD_ODDNB ((uint64_t)1 << 22) /* odd nibble */ 150 #define FTMAC110_RXD_RUNT ((uint64_t)1 << 21) /* runt pkt */ 151 #define FTMAC110_RXD_FTL ((uint64_t)1 << 20) /* frame too long */ 152 #define FTMAC110_RXD_CRC ((uint64_t)1 << 19) /* pkt crc error */ 153 #define FTMAC110_RXD_ERR ((uint64_t)1 << 18) /* bus error */ 154 #define FTMAC110_RXD_ERRMASK ((uint64_t)0x1f << 18) 155 #define FTMAC110_RXD_BCST ((uint64_t)1 << 17) /* Bcst pkt */ 156 #define FTMAC110_RXD_MCST ((uint64_t)1 << 16) /* Mcst pkt */ 157 #define FTMAC110_RXD_LEN(x) ((uint64_t)((x) & 0x7ff)) 158 159 #define FTMAC110_RXD_CLRMASK \ 160 (FTMAC110_RXD_END | FTMAC110_RXD_BUFSZ(0x7ff)) 161 162 #define FTMAC110_TXD_END ((uint64_t)1 << 63) /* end of ring */ 163 #define FTMAC110_TXD_TXIC ((uint64_t)1 << 62) /* tx done interrupt */ 164 #define FTMAC110_TXD_TX2FIC ((uint64_t)1 << 61) /* tx fifo interrupt */ 165 #define FTMAC110_TXD_FTS ((uint64_t)1 << 60) /* first pkt desc */ 166 #define FTMAC110_TXD_LTS ((uint64_t)1 << 59) /* last pkt desc */ 167 #define FTMAC110_TXD_LEN(x) ((uint64_t)((x) & 0x7ff) << 32) 168 169 #define FTMAC110_TXD_OWNER ((uint64_t)1 << 31) /* owner: 1=HW, 0=SW */ 170 #define FTMAC110_TXD_COL ((uint64_t)3) /* collision */ 171 172 #define FTMAC110_TXD_CLRMASK \ 173 (FTMAC110_TXD_END) 174 175 #endif /* FTMAC110_H */ 176