1 /* 2 * Faraday 10/100Mbps Ethernet Controller 3 * 4 * (C) Copyright 2013 Faraday Technology 5 * Dante Su <dantesu@faraday-tech.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <command.h> 12 #include <malloc.h> 13 #include <net.h> 14 #include <asm/errno.h> 15 #include <asm/io.h> 16 #include <asm/dma-mapping.h> 17 18 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 19 #include <miiphy.h> 20 #endif 21 22 #include "ftmac110.h" 23 24 #define CFG_RXDES_NUM 8 25 #define CFG_TXDES_NUM 2 26 #define CFG_XBUF_SIZE 1536 27 28 #define CFG_MDIORD_TIMEOUT (CONFIG_SYS_HZ >> 1) /* 500 ms */ 29 #define CFG_MDIOWR_TIMEOUT (CONFIG_SYS_HZ >> 1) /* 500 ms */ 30 #define CFG_LINKUP_TIMEOUT (CONFIG_SYS_HZ << 2) /* 4 sec */ 31 32 /* 33 * FTMAC110 DMA design issue 34 * 35 * Its DMA engine has a weird restriction that its Rx DMA engine 36 * accepts only 16-bits aligned address, 32-bits aligned is not 37 * acceptable. However this restriction does not apply to Tx DMA. 38 * 39 * Conclusion: 40 * (1) Tx DMA Buffer Address: 41 * 1 bytes aligned: Invalid 42 * 2 bytes aligned: O.K 43 * 4 bytes aligned: O.K (-> u-boot ZeroCopy is possible) 44 * (2) Rx DMA Buffer Address: 45 * 1 bytes aligned: Invalid 46 * 2 bytes aligned: O.K 47 * 4 bytes aligned: Invalid 48 */ 49 50 struct ftmac110_chip { 51 void __iomem *regs; 52 uint32_t imr; 53 uint32_t maccr; 54 uint32_t lnkup; 55 uint32_t phy_addr; 56 57 struct ftmac110_desc *rxd; 58 ulong rxd_dma; 59 uint32_t rxd_idx; 60 61 struct ftmac110_desc *txd; 62 ulong txd_dma; 63 uint32_t txd_idx; 64 }; 65 66 static int ftmac110_reset(struct eth_device *dev); 67 68 static uint16_t mdio_read(struct eth_device *dev, 69 uint8_t phyaddr, uint8_t phyreg) 70 { 71 struct ftmac110_chip *chip = dev->priv; 72 struct ftmac110_regs *regs = chip->regs; 73 uint32_t tmp, ts; 74 uint16_t ret = 0xffff; 75 76 tmp = PHYCR_READ 77 | (phyaddr << PHYCR_ADDR_SHIFT) 78 | (phyreg << PHYCR_REG_SHIFT); 79 80 writel(tmp, ®s->phycr); 81 82 for (ts = get_timer(0); get_timer(ts) < CFG_MDIORD_TIMEOUT; ) { 83 tmp = readl(®s->phycr); 84 if (tmp & PHYCR_READ) 85 continue; 86 break; 87 } 88 89 if (tmp & PHYCR_READ) 90 printf("ftmac110: mdio read timeout\n"); 91 else 92 ret = (uint16_t)(tmp & 0xffff); 93 94 return ret; 95 } 96 97 static void mdio_write(struct eth_device *dev, 98 uint8_t phyaddr, uint8_t phyreg, uint16_t phydata) 99 { 100 struct ftmac110_chip *chip = dev->priv; 101 struct ftmac110_regs *regs = chip->regs; 102 uint32_t tmp, ts; 103 104 tmp = PHYCR_WRITE 105 | (phyaddr << PHYCR_ADDR_SHIFT) 106 | (phyreg << PHYCR_REG_SHIFT); 107 108 writel(phydata, ®s->phydr); 109 writel(tmp, ®s->phycr); 110 111 for (ts = get_timer(0); get_timer(ts) < CFG_MDIOWR_TIMEOUT; ) { 112 if (readl(®s->phycr) & PHYCR_WRITE) 113 continue; 114 break; 115 } 116 117 if (readl(®s->phycr) & PHYCR_WRITE) 118 printf("ftmac110: mdio write timeout\n"); 119 } 120 121 static uint32_t ftmac110_phyqry(struct eth_device *dev) 122 { 123 ulong ts; 124 uint32_t maccr; 125 uint16_t pa, tmp, bmsr, bmcr; 126 struct ftmac110_chip *chip = dev->priv; 127 128 /* Default = 100Mbps Full */ 129 maccr = MACCR_100M | MACCR_FD; 130 131 /* 1. find the phy device */ 132 for (pa = 0; pa < 32; ++pa) { 133 tmp = mdio_read(dev, pa, MII_PHYSID1); 134 if (tmp == 0xFFFF || tmp == 0x0000) 135 continue; 136 chip->phy_addr = pa; 137 break; 138 } 139 if (pa >= 32) { 140 puts("ftmac110: phy device not found!\n"); 141 goto exit; 142 } 143 144 /* 2. wait until link-up & auto-negotiation complete */ 145 chip->lnkup = 0; 146 bmcr = mdio_read(dev, chip->phy_addr, MII_BMCR); 147 ts = get_timer(0); 148 do { 149 bmsr = mdio_read(dev, chip->phy_addr, MII_BMSR); 150 chip->lnkup = (bmsr & BMSR_LSTATUS) ? 1 : 0; 151 if (!chip->lnkup) 152 continue; 153 if (!(bmcr & BMCR_ANENABLE) || (bmsr & BMSR_ANEGCOMPLETE)) 154 break; 155 } while (get_timer(ts) < CFG_LINKUP_TIMEOUT); 156 if (!chip->lnkup) { 157 puts("ftmac110: link down\n"); 158 goto exit; 159 } 160 if (!(bmcr & BMCR_ANENABLE)) 161 puts("ftmac110: auto negotiation disabled\n"); 162 else if (!(bmsr & BMSR_ANEGCOMPLETE)) 163 puts("ftmac110: auto negotiation timeout\n"); 164 165 /* 3. derive MACCR */ 166 if ((bmcr & BMCR_ANENABLE) && (bmsr & BMSR_ANEGCOMPLETE)) { 167 tmp = mdio_read(dev, chip->phy_addr, MII_ADVERTISE); 168 tmp &= mdio_read(dev, chip->phy_addr, MII_LPA); 169 if (tmp & LPA_100FULL) /* 100Mbps full-duplex */ 170 maccr = MACCR_100M | MACCR_FD; 171 else if (tmp & LPA_100HALF) /* 100Mbps half-duplex */ 172 maccr = MACCR_100M; 173 else if (tmp & LPA_10FULL) /* 10Mbps full-duplex */ 174 maccr = MACCR_FD; 175 else if (tmp & LPA_10HALF) /* 10Mbps half-duplex */ 176 maccr = 0; 177 } else { 178 if (bmcr & BMCR_SPEED100) 179 maccr = MACCR_100M; 180 else 181 maccr = 0; 182 if (bmcr & BMCR_FULLDPLX) 183 maccr |= MACCR_FD; 184 } 185 186 exit: 187 printf("ftmac110: %d Mbps, %s\n", 188 (maccr & MACCR_100M) ? 100 : 10, 189 (maccr & MACCR_FD) ? "Full" : "half"); 190 return maccr; 191 } 192 193 static int ftmac110_reset(struct eth_device *dev) 194 { 195 uint8_t *a; 196 uint32_t i, maccr; 197 struct ftmac110_chip *chip = dev->priv; 198 struct ftmac110_regs *regs = chip->regs; 199 200 /* 1. MAC reset */ 201 writel(MACCR_RESET, ®s->maccr); 202 for (i = get_timer(0); get_timer(i) < 1000; ) { 203 if (readl(®s->maccr) & MACCR_RESET) 204 continue; 205 break; 206 } 207 if (readl(®s->maccr) & MACCR_RESET) { 208 printf("ftmac110: reset failed\n"); 209 return -ENXIO; 210 } 211 212 /* 1-1. Init tx ring */ 213 for (i = 0; i < CFG_TXDES_NUM; ++i) { 214 /* owned by SW */ 215 chip->txd[i].ctrl &= cpu_to_le64(FTMAC110_TXD_CLRMASK); 216 } 217 chip->txd_idx = 0; 218 219 /* 1-2. Init rx ring */ 220 for (i = 0; i < CFG_RXDES_NUM; ++i) { 221 /* owned by HW */ 222 chip->rxd[i].ctrl &= cpu_to_le64(FTMAC110_RXD_CLRMASK); 223 chip->rxd[i].ctrl |= cpu_to_le64(FTMAC110_RXD_OWNER); 224 } 225 chip->rxd_idx = 0; 226 227 /* 2. PHY status query */ 228 maccr = ftmac110_phyqry(dev); 229 230 /* 3. Fix up the MACCR value */ 231 chip->maccr = maccr | MACCR_CRCAPD | MACCR_RXALL | MACCR_RXRUNT 232 | MACCR_RXEN | MACCR_TXEN | MACCR_RXDMAEN | MACCR_TXDMAEN; 233 234 /* 4. MAC address setup */ 235 a = dev->enetaddr; 236 writel(a[1] | (a[0] << 8), ®s->mac[0]); 237 writel(a[5] | (a[4] << 8) | (a[3] << 16) 238 | (a[2] << 24), ®s->mac[1]); 239 240 /* 5. MAC registers setup */ 241 writel(chip->rxd_dma, ®s->rxba); 242 writel(chip->txd_dma, ®s->txba); 243 /* interrupt at each tx/rx */ 244 writel(ITC_DEFAULT, ®s->itc); 245 /* no tx pool, rx poll = 1 normal cycle */ 246 writel(APTC_DEFAULT, ®s->aptc); 247 /* rx threshold = [6/8 fifo, 2/8 fifo] */ 248 writel(DBLAC_DEFAULT, ®s->dblac); 249 /* disable & clear all interrupt status */ 250 chip->imr = 0; 251 writel(ISR_ALL, ®s->isr); 252 writel(chip->imr, ®s->imr); 253 /* enable mac */ 254 writel(chip->maccr, ®s->maccr); 255 256 return 0; 257 } 258 259 static int ftmac110_probe(struct eth_device *dev, bd_t *bis) 260 { 261 debug("ftmac110: probe\n"); 262 263 if (ftmac110_reset(dev)) 264 return -1; 265 266 return 0; 267 } 268 269 static void ftmac110_halt(struct eth_device *dev) 270 { 271 struct ftmac110_chip *chip = dev->priv; 272 struct ftmac110_regs *regs = chip->regs; 273 274 writel(0, ®s->imr); 275 writel(0, ®s->maccr); 276 277 debug("ftmac110: halt\n"); 278 } 279 280 static int ftmac110_send(struct eth_device *dev, void *pkt, int len) 281 { 282 struct ftmac110_chip *chip = dev->priv; 283 struct ftmac110_regs *regs = chip->regs; 284 struct ftmac110_desc *txd; 285 uint64_t ctrl; 286 287 if (!chip->lnkup) 288 return 0; 289 290 if (len <= 0 || len > CFG_XBUF_SIZE) { 291 printf("ftmac110: bad tx pkt len(%d)\n", len); 292 return 0; 293 } 294 295 len = max(60, len); 296 297 txd = &chip->txd[chip->txd_idx]; 298 ctrl = le64_to_cpu(txd->ctrl); 299 if (ctrl & FTMAC110_TXD_OWNER) { 300 /* kick-off Tx DMA */ 301 writel(0xffffffff, ®s->txpd); 302 printf("ftmac110: out of txd\n"); 303 return 0; 304 } 305 306 memcpy(txd->vbuf, (void *)pkt, len); 307 dma_map_single(txd->vbuf, len, DMA_TO_DEVICE); 308 309 /* clear control bits */ 310 ctrl &= FTMAC110_TXD_CLRMASK; 311 /* set len, fts and lts */ 312 ctrl |= FTMAC110_TXD_LEN(len) | FTMAC110_TXD_FTS | FTMAC110_TXD_LTS; 313 /* set owner bit */ 314 ctrl |= FTMAC110_TXD_OWNER; 315 /* write back to descriptor */ 316 txd->ctrl = cpu_to_le64(ctrl); 317 318 /* kick-off Tx DMA */ 319 writel(0xffffffff, ®s->txpd); 320 321 chip->txd_idx = (chip->txd_idx + 1) % CFG_TXDES_NUM; 322 323 return len; 324 } 325 326 static int ftmac110_recv(struct eth_device *dev) 327 { 328 struct ftmac110_chip *chip = dev->priv; 329 struct ftmac110_desc *rxd; 330 uint32_t len, rlen = 0; 331 uint64_t ctrl; 332 uint8_t *buf; 333 334 if (!chip->lnkup) 335 return 0; 336 337 do { 338 rxd = &chip->rxd[chip->rxd_idx]; 339 ctrl = le64_to_cpu(rxd->ctrl); 340 if (ctrl & FTMAC110_RXD_OWNER) 341 break; 342 343 len = (uint32_t)FTMAC110_RXD_LEN(ctrl); 344 buf = rxd->vbuf; 345 346 if (ctrl & FTMAC110_RXD_ERRMASK) { 347 printf("ftmac110: rx error\n"); 348 } else { 349 dma_map_single(buf, len, DMA_FROM_DEVICE); 350 net_process_received_packet(buf, len); 351 rlen += len; 352 } 353 354 /* owned by hardware */ 355 ctrl &= FTMAC110_RXD_CLRMASK; 356 ctrl |= FTMAC110_RXD_OWNER; 357 rxd->ctrl |= cpu_to_le64(ctrl); 358 359 chip->rxd_idx = (chip->rxd_idx + 1) % CFG_RXDES_NUM; 360 } while (0); 361 362 return rlen; 363 } 364 365 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 366 367 static int ftmac110_mdio_read( 368 const char *devname, uint8_t addr, uint8_t reg, uint16_t *value) 369 { 370 int ret = 0; 371 struct eth_device *dev; 372 373 dev = eth_get_dev_by_name(devname); 374 if (dev == NULL) { 375 printf("%s: no such device\n", devname); 376 ret = -1; 377 } else { 378 *value = mdio_read(dev, addr, reg); 379 } 380 381 return ret; 382 } 383 384 static int ftmac110_mdio_write( 385 const char *devname, uint8_t addr, uint8_t reg, uint16_t value) 386 { 387 int ret = 0; 388 struct eth_device *dev; 389 390 dev = eth_get_dev_by_name(devname); 391 if (dev == NULL) { 392 printf("%s: no such device\n", devname); 393 ret = -1; 394 } else { 395 mdio_write(dev, addr, reg, value); 396 } 397 398 return ret; 399 } 400 401 #endif /* #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) */ 402 403 int ftmac110_initialize(bd_t *bis) 404 { 405 int i, card_nr = 0; 406 struct eth_device *dev; 407 struct ftmac110_chip *chip; 408 409 dev = malloc(sizeof(*dev) + sizeof(*chip)); 410 if (dev == NULL) { 411 panic("ftmac110: out of memory 1\n"); 412 return -1; 413 } 414 chip = (struct ftmac110_chip *)(dev + 1); 415 memset(dev, 0, sizeof(*dev) + sizeof(*chip)); 416 417 sprintf(dev->name, "FTMAC110#%d", card_nr); 418 419 dev->iobase = CONFIG_FTMAC110_BASE; 420 chip->regs = (void __iomem *)dev->iobase; 421 dev->priv = chip; 422 dev->init = ftmac110_probe; 423 dev->halt = ftmac110_halt; 424 dev->send = ftmac110_send; 425 dev->recv = ftmac110_recv; 426 427 /* allocate tx descriptors (it must be 16 bytes aligned) */ 428 chip->txd = dma_alloc_coherent( 429 sizeof(struct ftmac110_desc) * CFG_TXDES_NUM, &chip->txd_dma); 430 if (!chip->txd) 431 panic("ftmac110: out of memory 3\n"); 432 memset(chip->txd, 0, 433 sizeof(struct ftmac110_desc) * CFG_TXDES_NUM); 434 for (i = 0; i < CFG_TXDES_NUM; ++i) { 435 void *va = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE); 436 437 if (!va) 438 panic("ftmac110: out of memory 4\n"); 439 chip->txd[i].vbuf = va; 440 chip->txd[i].pbuf = cpu_to_le32(virt_to_phys(va)); 441 chip->txd[i].ctrl = 0; /* owned by SW */ 442 } 443 chip->txd[i - 1].ctrl |= cpu_to_le64(FTMAC110_TXD_END); 444 chip->txd_idx = 0; 445 446 /* allocate rx descriptors (it must be 16 bytes aligned) */ 447 chip->rxd = dma_alloc_coherent( 448 sizeof(struct ftmac110_desc) * CFG_RXDES_NUM, &chip->rxd_dma); 449 if (!chip->rxd) 450 panic("ftmac110: out of memory 4\n"); 451 memset((void *)chip->rxd, 0, 452 sizeof(struct ftmac110_desc) * CFG_RXDES_NUM); 453 for (i = 0; i < CFG_RXDES_NUM; ++i) { 454 void *va = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE + 2); 455 456 if (!va) 457 panic("ftmac110: out of memory 5\n"); 458 /* it needs to be exactly 2 bytes aligned */ 459 va = ((uint8_t *)va + 2); 460 chip->rxd[i].vbuf = va; 461 chip->rxd[i].pbuf = cpu_to_le32(virt_to_phys(va)); 462 chip->rxd[i].ctrl = cpu_to_le64(FTMAC110_RXD_OWNER 463 | FTMAC110_RXD_BUFSZ(CFG_XBUF_SIZE)); 464 } 465 chip->rxd[i - 1].ctrl |= cpu_to_le64(FTMAC110_RXD_END); 466 chip->rxd_idx = 0; 467 468 eth_register(dev); 469 470 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 471 miiphy_register(dev->name, ftmac110_mdio_read, ftmac110_mdio_write); 472 #endif 473 474 card_nr++; 475 476 return card_nr; 477 } 478