1 /* 2 * Faraday FTMAC100 Ethernet 3 * 4 * (C) Copyright 2009 Faraday Technology 5 * Po-Yu Chuang <ratbert@faraday-tech.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 */ 21 22 #ifndef __FTMAC100_H 23 #define __FTMAC100_H 24 25 struct ftmac100 { 26 unsigned int isr; /* 0x00 */ 27 unsigned int imr; /* 0x04 */ 28 unsigned int mac_madr; /* 0x08 */ 29 unsigned int mac_ladr; /* 0x0c */ 30 unsigned int maht0; /* 0x10 */ 31 unsigned int maht1; /* 0x14 */ 32 unsigned int txpd; /* 0x18 */ 33 unsigned int rxpd; /* 0x1c */ 34 unsigned int txr_badr; /* 0x20 */ 35 unsigned int rxr_badr; /* 0x24 */ 36 unsigned int itc; /* 0x28 */ 37 unsigned int aptc; /* 0x2c */ 38 unsigned int dblac; /* 0x30 */ 39 unsigned int pad1[3]; /* 0x34 - 0x3c */ 40 unsigned int pad2[16]; /* 0x40 - 0x7c */ 41 unsigned int pad3[2]; /* 0x80 - 0x84 */ 42 unsigned int maccr; /* 0x88 */ 43 unsigned int macsr; /* 0x8c */ 44 unsigned int phycr; /* 0x90 */ 45 unsigned int phywdata; /* 0x94 */ 46 unsigned int fcr; /* 0x98 */ 47 unsigned int bpr; /* 0x9c */ 48 unsigned int pad4[8]; /* 0xa0 - 0xbc */ 49 unsigned int pad5; /* 0xc0 */ 50 unsigned int ts; /* 0xc4 */ 51 unsigned int dmafifos; /* 0xc8 */ 52 unsigned int tm; /* 0xcc */ 53 unsigned int pad6; /* 0xd0 */ 54 unsigned int tx_mcol_scol; /* 0xd4 */ 55 unsigned int rpf_aep; /* 0xd8 */ 56 unsigned int xm_pg; /* 0xdc */ 57 unsigned int runt_tlcc; /* 0xe0 */ 58 unsigned int crcer_ftl; /* 0xe4 */ 59 unsigned int rlc_rcc; /* 0xe8 */ 60 unsigned int broc; /* 0xec */ 61 unsigned int mulca; /* 0xf0 */ 62 unsigned int rp; /* 0xf4 */ 63 unsigned int xp; /* 0xf8 */ 64 }; 65 66 /* 67 * Interrupt status register & interrupt mask register 68 */ 69 #define FTMAC100_INT_RPKT_FINISH (1 << 0) 70 #define FTMAC100_INT_NORXBUF (1 << 1) 71 #define FTMAC100_INT_XPKT_FINISH (1 << 2) 72 #define FTMAC100_INT_NOTXBUF (1 << 3) 73 #define FTMAC100_INT_XPKT_OK (1 << 4) 74 #define FTMAC100_INT_XPKT_LOST (1 << 5) 75 #define FTMAC100_INT_RPKT_SAV (1 << 6) 76 #define FTMAC100_INT_RPKT_LOST (1 << 7) 77 #define FTMAC100_INT_AHB_ERR (1 << 8) 78 #define FTMAC100_INT_PHYSTS_CHG (1 << 9) 79 80 /* 81 * Automatic polling timer control register 82 */ 83 #define FTMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0) 84 #define FTMAC100_APTC_RXPOLL_TIME_SEL (1 << 4) 85 #define FTMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8) 86 #define FTMAC100_APTC_TXPOLL_TIME_SEL (1 << 12) 87 88 /* 89 * MAC control register 90 */ 91 #define FTMAC100_MACCR_XDMA_EN (1 << 0) 92 #define FTMAC100_MACCR_RDMA_EN (1 << 1) 93 #define FTMAC100_MACCR_SW_RST (1 << 2) 94 #define FTMAC100_MACCR_LOOP_EN (1 << 3) 95 #define FTMAC100_MACCR_CRC_DIS (1 << 4) 96 #define FTMAC100_MACCR_XMT_EN (1 << 5) 97 #define FTMAC100_MACCR_ENRX_IN_HALFTX (1 << 6) 98 #define FTMAC100_MACCR_RCV_EN (1 << 8) 99 #define FTMAC100_MACCR_HT_MULTI_EN (1 << 9) 100 #define FTMAC100_MACCR_RX_RUNT (1 << 10) 101 #define FTMAC100_MACCR_RX_FTL (1 << 11) 102 #define FTMAC100_MACCR_RCV_ALL (1 << 12) 103 #define FTMAC100_MACCR_CRC_APD (1 << 14) 104 #define FTMAC100_MACCR_FULLDUP (1 << 15) 105 #define FTMAC100_MACCR_RX_MULTIPKT (1 << 16) 106 #define FTMAC100_MACCR_RX_BROADPKT (1 << 17) 107 108 /* 109 * Transmit descriptor, aligned to 16 bytes 110 */ 111 struct ftmac100_txdes { 112 unsigned int txdes0; 113 unsigned int txdes1; 114 unsigned int txdes2; /* TXBUF_BADR */ 115 unsigned int txdes3; /* not used by HW */ 116 } __attribute__ ((aligned(16))); 117 118 #define FTMAC100_TXDES0_TXPKT_LATECOL (1 << 0) 119 #define FTMAC100_TXDES0_TXPKT_EXSCOL (1 << 1) 120 #define FTMAC100_TXDES0_TXDMA_OWN (1 << 31) 121 122 #define FTMAC100_TXDES1_TXBUF_SIZE(x) ((x) & 0x7ff) 123 #define FTMAC100_TXDES1_LTS (1 << 27) 124 #define FTMAC100_TXDES1_FTS (1 << 28) 125 #define FTMAC100_TXDES1_TX2FIC (1 << 29) 126 #define FTMAC100_TXDES1_TXIC (1 << 30) 127 #define FTMAC100_TXDES1_EDOTR (1 << 31) 128 129 /* 130 * Receive descriptor, aligned to 16 bytes 131 */ 132 struct ftmac100_rxdes { 133 unsigned int rxdes0; 134 unsigned int rxdes1; 135 unsigned int rxdes2; /* RXBUF_BADR */ 136 unsigned int rxdes3; /* not used by HW */ 137 } __attribute__ ((aligned(16))); 138 139 #define FTMAC100_RXDES0_RFL(des) ((des) & 0x7ff) 140 #define FTMAC100_RXDES0_MULTICAST (1 << 16) 141 #define FTMAC100_RXDES0_BROADCAST (1 << 17) 142 #define FTMAC100_RXDES0_RX_ERR (1 << 18) 143 #define FTMAC100_RXDES0_CRC_ERR (1 << 19) 144 #define FTMAC100_RXDES0_FTL (1 << 20) 145 #define FTMAC100_RXDES0_RUNT (1 << 21) 146 #define FTMAC100_RXDES0_RX_ODD_NB (1 << 22) 147 #define FTMAC100_RXDES0_LRS (1 << 28) 148 #define FTMAC100_RXDES0_FRS (1 << 29) 149 #define FTMAC100_RXDES0_RXDMA_OWN (1 << 31) 150 151 #define FTMAC100_RXDES1_RXBUF_SIZE(x) ((x) & 0x7ff) 152 #define FTMAC100_RXDES1_EDORR (1 << 31) 153 154 #endif /* __FTMAC100_H */ 155