1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2750326e5SPo-Yu Chuang /* 3750326e5SPo-Yu Chuang * Faraday FTMAC100 Ethernet 4750326e5SPo-Yu Chuang * 5750326e5SPo-Yu Chuang * (C) Copyright 2009 Faraday Technology 6750326e5SPo-Yu Chuang * Po-Yu Chuang <ratbert@faraday-tech.com> 7750326e5SPo-Yu Chuang */ 8750326e5SPo-Yu Chuang 9750326e5SPo-Yu Chuang #ifndef __FTMAC100_H 10750326e5SPo-Yu Chuang #define __FTMAC100_H 11750326e5SPo-Yu Chuang 12750326e5SPo-Yu Chuang struct ftmac100 { 13750326e5SPo-Yu Chuang unsigned int isr; /* 0x00 */ 14750326e5SPo-Yu Chuang unsigned int imr; /* 0x04 */ 15750326e5SPo-Yu Chuang unsigned int mac_madr; /* 0x08 */ 16750326e5SPo-Yu Chuang unsigned int mac_ladr; /* 0x0c */ 17750326e5SPo-Yu Chuang unsigned int maht0; /* 0x10 */ 18750326e5SPo-Yu Chuang unsigned int maht1; /* 0x14 */ 19750326e5SPo-Yu Chuang unsigned int txpd; /* 0x18 */ 20750326e5SPo-Yu Chuang unsigned int rxpd; /* 0x1c */ 21750326e5SPo-Yu Chuang unsigned int txr_badr; /* 0x20 */ 22750326e5SPo-Yu Chuang unsigned int rxr_badr; /* 0x24 */ 23750326e5SPo-Yu Chuang unsigned int itc; /* 0x28 */ 24750326e5SPo-Yu Chuang unsigned int aptc; /* 0x2c */ 25750326e5SPo-Yu Chuang unsigned int dblac; /* 0x30 */ 26750326e5SPo-Yu Chuang unsigned int pad1[3]; /* 0x34 - 0x3c */ 27750326e5SPo-Yu Chuang unsigned int pad2[16]; /* 0x40 - 0x7c */ 28750326e5SPo-Yu Chuang unsigned int pad3[2]; /* 0x80 - 0x84 */ 29750326e5SPo-Yu Chuang unsigned int maccr; /* 0x88 */ 30750326e5SPo-Yu Chuang unsigned int macsr; /* 0x8c */ 31750326e5SPo-Yu Chuang unsigned int phycr; /* 0x90 */ 32750326e5SPo-Yu Chuang unsigned int phywdata; /* 0x94 */ 33750326e5SPo-Yu Chuang unsigned int fcr; /* 0x98 */ 34750326e5SPo-Yu Chuang unsigned int bpr; /* 0x9c */ 35750326e5SPo-Yu Chuang unsigned int pad4[8]; /* 0xa0 - 0xbc */ 36750326e5SPo-Yu Chuang unsigned int pad5; /* 0xc0 */ 37750326e5SPo-Yu Chuang unsigned int ts; /* 0xc4 */ 38750326e5SPo-Yu Chuang unsigned int dmafifos; /* 0xc8 */ 39750326e5SPo-Yu Chuang unsigned int tm; /* 0xcc */ 40750326e5SPo-Yu Chuang unsigned int pad6; /* 0xd0 */ 41750326e5SPo-Yu Chuang unsigned int tx_mcol_scol; /* 0xd4 */ 42750326e5SPo-Yu Chuang unsigned int rpf_aep; /* 0xd8 */ 43750326e5SPo-Yu Chuang unsigned int xm_pg; /* 0xdc */ 44750326e5SPo-Yu Chuang unsigned int runt_tlcc; /* 0xe0 */ 45750326e5SPo-Yu Chuang unsigned int crcer_ftl; /* 0xe4 */ 46750326e5SPo-Yu Chuang unsigned int rlc_rcc; /* 0xe8 */ 47750326e5SPo-Yu Chuang unsigned int broc; /* 0xec */ 48750326e5SPo-Yu Chuang unsigned int mulca; /* 0xf0 */ 49750326e5SPo-Yu Chuang unsigned int rp; /* 0xf4 */ 50750326e5SPo-Yu Chuang unsigned int xp; /* 0xf8 */ 51750326e5SPo-Yu Chuang }; 52750326e5SPo-Yu Chuang 53750326e5SPo-Yu Chuang /* 54750326e5SPo-Yu Chuang * Interrupt status register & interrupt mask register 55750326e5SPo-Yu Chuang */ 56750326e5SPo-Yu Chuang #define FTMAC100_INT_RPKT_FINISH (1 << 0) 57750326e5SPo-Yu Chuang #define FTMAC100_INT_NORXBUF (1 << 1) 58750326e5SPo-Yu Chuang #define FTMAC100_INT_XPKT_FINISH (1 << 2) 59750326e5SPo-Yu Chuang #define FTMAC100_INT_NOTXBUF (1 << 3) 60750326e5SPo-Yu Chuang #define FTMAC100_INT_XPKT_OK (1 << 4) 61750326e5SPo-Yu Chuang #define FTMAC100_INT_XPKT_LOST (1 << 5) 62750326e5SPo-Yu Chuang #define FTMAC100_INT_RPKT_SAV (1 << 6) 63750326e5SPo-Yu Chuang #define FTMAC100_INT_RPKT_LOST (1 << 7) 64750326e5SPo-Yu Chuang #define FTMAC100_INT_AHB_ERR (1 << 8) 65750326e5SPo-Yu Chuang #define FTMAC100_INT_PHYSTS_CHG (1 << 9) 66750326e5SPo-Yu Chuang 67750326e5SPo-Yu Chuang /* 68750326e5SPo-Yu Chuang * Automatic polling timer control register 69750326e5SPo-Yu Chuang */ 70750326e5SPo-Yu Chuang #define FTMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0) 71750326e5SPo-Yu Chuang #define FTMAC100_APTC_RXPOLL_TIME_SEL (1 << 4) 72750326e5SPo-Yu Chuang #define FTMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8) 73750326e5SPo-Yu Chuang #define FTMAC100_APTC_TXPOLL_TIME_SEL (1 << 12) 74750326e5SPo-Yu Chuang 75750326e5SPo-Yu Chuang /* 76750326e5SPo-Yu Chuang * MAC control register 77750326e5SPo-Yu Chuang */ 78750326e5SPo-Yu Chuang #define FTMAC100_MACCR_XDMA_EN (1 << 0) 79750326e5SPo-Yu Chuang #define FTMAC100_MACCR_RDMA_EN (1 << 1) 80750326e5SPo-Yu Chuang #define FTMAC100_MACCR_SW_RST (1 << 2) 81750326e5SPo-Yu Chuang #define FTMAC100_MACCR_LOOP_EN (1 << 3) 82750326e5SPo-Yu Chuang #define FTMAC100_MACCR_CRC_DIS (1 << 4) 83750326e5SPo-Yu Chuang #define FTMAC100_MACCR_XMT_EN (1 << 5) 84750326e5SPo-Yu Chuang #define FTMAC100_MACCR_ENRX_IN_HALFTX (1 << 6) 85750326e5SPo-Yu Chuang #define FTMAC100_MACCR_RCV_EN (1 << 8) 86750326e5SPo-Yu Chuang #define FTMAC100_MACCR_HT_MULTI_EN (1 << 9) 87750326e5SPo-Yu Chuang #define FTMAC100_MACCR_RX_RUNT (1 << 10) 88750326e5SPo-Yu Chuang #define FTMAC100_MACCR_RX_FTL (1 << 11) 89750326e5SPo-Yu Chuang #define FTMAC100_MACCR_RCV_ALL (1 << 12) 90750326e5SPo-Yu Chuang #define FTMAC100_MACCR_CRC_APD (1 << 14) 91750326e5SPo-Yu Chuang #define FTMAC100_MACCR_FULLDUP (1 << 15) 92750326e5SPo-Yu Chuang #define FTMAC100_MACCR_RX_MULTIPKT (1 << 16) 93750326e5SPo-Yu Chuang #define FTMAC100_MACCR_RX_BROADPKT (1 << 17) 94750326e5SPo-Yu Chuang 95750326e5SPo-Yu Chuang /* 96750326e5SPo-Yu Chuang * Transmit descriptor, aligned to 16 bytes 97750326e5SPo-Yu Chuang */ 98750326e5SPo-Yu Chuang struct ftmac100_txdes { 99750326e5SPo-Yu Chuang unsigned int txdes0; 100750326e5SPo-Yu Chuang unsigned int txdes1; 101750326e5SPo-Yu Chuang unsigned int txdes2; /* TXBUF_BADR */ 102750326e5SPo-Yu Chuang unsigned int txdes3; /* not used by HW */ 103750326e5SPo-Yu Chuang } __attribute__ ((aligned(16))); 104750326e5SPo-Yu Chuang 105750326e5SPo-Yu Chuang #define FTMAC100_TXDES0_TXPKT_LATECOL (1 << 0) 106750326e5SPo-Yu Chuang #define FTMAC100_TXDES0_TXPKT_EXSCOL (1 << 1) 107750326e5SPo-Yu Chuang #define FTMAC100_TXDES0_TXDMA_OWN (1 << 31) 108750326e5SPo-Yu Chuang 109750326e5SPo-Yu Chuang #define FTMAC100_TXDES1_TXBUF_SIZE(x) ((x) & 0x7ff) 110750326e5SPo-Yu Chuang #define FTMAC100_TXDES1_LTS (1 << 27) 111750326e5SPo-Yu Chuang #define FTMAC100_TXDES1_FTS (1 << 28) 112750326e5SPo-Yu Chuang #define FTMAC100_TXDES1_TX2FIC (1 << 29) 113750326e5SPo-Yu Chuang #define FTMAC100_TXDES1_TXIC (1 << 30) 114750326e5SPo-Yu Chuang #define FTMAC100_TXDES1_EDOTR (1 << 31) 115750326e5SPo-Yu Chuang 116750326e5SPo-Yu Chuang /* 117750326e5SPo-Yu Chuang * Receive descriptor, aligned to 16 bytes 118750326e5SPo-Yu Chuang */ 119750326e5SPo-Yu Chuang struct ftmac100_rxdes { 120750326e5SPo-Yu Chuang unsigned int rxdes0; 121750326e5SPo-Yu Chuang unsigned int rxdes1; 122750326e5SPo-Yu Chuang unsigned int rxdes2; /* RXBUF_BADR */ 123750326e5SPo-Yu Chuang unsigned int rxdes3; /* not used by HW */ 124750326e5SPo-Yu Chuang } __attribute__ ((aligned(16))); 125750326e5SPo-Yu Chuang 126750326e5SPo-Yu Chuang #define FTMAC100_RXDES0_RFL(des) ((des) & 0x7ff) 127750326e5SPo-Yu Chuang #define FTMAC100_RXDES0_MULTICAST (1 << 16) 128750326e5SPo-Yu Chuang #define FTMAC100_RXDES0_BROADCAST (1 << 17) 129750326e5SPo-Yu Chuang #define FTMAC100_RXDES0_RX_ERR (1 << 18) 130750326e5SPo-Yu Chuang #define FTMAC100_RXDES0_CRC_ERR (1 << 19) 131750326e5SPo-Yu Chuang #define FTMAC100_RXDES0_FTL (1 << 20) 132750326e5SPo-Yu Chuang #define FTMAC100_RXDES0_RUNT (1 << 21) 133750326e5SPo-Yu Chuang #define FTMAC100_RXDES0_RX_ODD_NB (1 << 22) 134750326e5SPo-Yu Chuang #define FTMAC100_RXDES0_LRS (1 << 28) 135750326e5SPo-Yu Chuang #define FTMAC100_RXDES0_FRS (1 << 29) 136750326e5SPo-Yu Chuang #define FTMAC100_RXDES0_RXDMA_OWN (1 << 31) 137750326e5SPo-Yu Chuang 138750326e5SPo-Yu Chuang #define FTMAC100_RXDES1_RXBUF_SIZE(x) ((x) & 0x7ff) 139750326e5SPo-Yu Chuang #define FTMAC100_RXDES1_EDORR (1 << 31) 140750326e5SPo-Yu Chuang 141750326e5SPo-Yu Chuang #endif /* __FTMAC100_H */ 142