1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Faraday FTGMAC100 Ethernet 4 * 5 * (C) Copyright 2009 Faraday Technology 6 * Po-Yu Chuang <ratbert@faraday-tech.com> 7 * 8 * (C) Copyright 2010 Andes Technology 9 * Macpaul Lin <macpaul@andestech.com> 10 * 11 * Copyright (C) 2018, IBM Corporation. 12 */ 13 14 #include <clk.h> 15 #include <dm.h> 16 #include <miiphy.h> 17 #include <net.h> 18 #include <wait_bit.h> 19 #include <linux/io.h> 20 #include <linux/iopoll.h> 21 22 #include "ftgmac100.h" 23 #include "aspeed_mdio.h" 24 25 /* Min frame ethernet frame size without FCS */ 26 #define ETH_ZLEN 60 27 28 /* Receive Buffer Size Register - HW default is 0x640 */ 29 #define FTGMAC100_RBSR_DEFAULT 0x640 30 31 /* PKTBUFSTX/PKTBUFSRX must both be power of 2 */ 32 #define PKTBUFSTX 4 /* must be power of 2 */ 33 34 /* Timeout for transmit */ 35 #define FTGMAC100_TX_TIMEOUT_MS 1000 36 37 /* Timeout for a mdio read/write operation */ 38 #define FTGMAC100_MDIO_TIMEOUT_USEC 10000 39 40 /* 41 * MDC clock cycle threshold 42 * 43 * 20us * 100 = 2ms > (1 / 2.5Mhz) * 0x34 44 */ 45 #define MDC_CYCTHR 0x34 46 47 /* 48 * ftgmac100 model variants 49 */ 50 enum ftgmac100_model { 51 FTGMAC100_MODEL_FARADAY, 52 FTGMAC100_MODEL_ASPEED, 53 FTGMAC100_MODEL_NEW_ASPEED, 54 }; 55 56 /** 57 * struct ftgmac100_data - private data for the FTGMAC100 driver 58 * 59 * @iobase: The base address of the hardware registers 60 * @txdes: The array of transmit descriptors 61 * @rxdes: The array of receive descriptors 62 * @tx_index: Transmit descriptor index in @txdes 63 * @rx_index: Receive descriptor index in @rxdes 64 * @phy_addr: The PHY interface address to use 65 * @phydev: The PHY device backing the MAC 66 * @bus: The mdio bus 67 * @phy_mode: The mode of the PHY interface (rgmii, rmii, ...) 68 * @max_speed: Maximum speed of Ethernet connection supported by MAC 69 * @clks: The bulk of clocks assigned to the device in the DT 70 * @rxdes0_edorr_mask: The bit number identifying the end of the RX ring buffer 71 * @txdes0_edotr_mask: The bit number identifying the end of the TX ring buffer 72 */ 73 struct ftgmac100_data { 74 struct ftgmac100 *iobase; 75 fdt_addr_t mdio_addr; //for aspeed ast2600 new mdio 76 77 struct ftgmac100_txdes txdes[PKTBUFSTX]; 78 struct ftgmac100_rxdes rxdes[PKTBUFSRX]; 79 int tx_index; 80 int rx_index; 81 82 u32 phy_addr; 83 struct phy_device *phydev; 84 struct mii_dev *bus; 85 u32 phy_mode; 86 u32 max_speed; 87 88 struct clk_bulk clks; 89 90 /* End of RX/TX ring buffer bits. Depend on model */ 91 u32 rxdes0_edorr_mask; 92 u32 txdes0_edotr_mask; 93 }; 94 95 /* 96 * struct mii_bus functions 97 */ 98 static int ftgmac100_mdio_read(struct mii_dev *bus, int phy_addr, int dev_addr, 99 int reg_addr) 100 { 101 struct ftgmac100_data *priv = bus->priv; 102 struct ftgmac100 *ftgmac100 = priv->iobase; 103 int phycr; 104 int data; 105 int ret; 106 107 phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) | 108 FTGMAC100_PHYCR_PHYAD(phy_addr) | 109 FTGMAC100_PHYCR_REGAD(reg_addr) | 110 FTGMAC100_PHYCR_MIIRD; 111 writel(phycr, &ftgmac100->phycr); 112 113 ret = readl_poll_timeout(&ftgmac100->phycr, phycr, 114 !(phycr & FTGMAC100_PHYCR_MIIRD), 115 FTGMAC100_MDIO_TIMEOUT_USEC); 116 if (ret) { 117 pr_err("%s: mdio read failed (phy:%d reg:%x)\n", 118 priv->phydev->dev->name, phy_addr, reg_addr); 119 return ret; 120 } 121 122 data = readl(&ftgmac100->phydata); 123 124 return FTGMAC100_PHYDATA_MIIRDATA(data); 125 } 126 127 static int ftgmac100_mdio_write(struct mii_dev *bus, int phy_addr, int dev_addr, 128 int reg_addr, u16 value) 129 { 130 struct ftgmac100_data *priv = bus->priv; 131 struct ftgmac100 *ftgmac100 = priv->iobase; 132 int phycr; 133 int data; 134 int ret; 135 136 phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) | 137 FTGMAC100_PHYCR_PHYAD(phy_addr) | 138 FTGMAC100_PHYCR_REGAD(reg_addr) | 139 FTGMAC100_PHYCR_MIIWR; 140 data = FTGMAC100_PHYDATA_MIIWDATA(value); 141 142 writel(data, &ftgmac100->phydata); 143 writel(phycr, &ftgmac100->phycr); 144 145 ret = readl_poll_timeout(&ftgmac100->phycr, phycr, 146 !(phycr & FTGMAC100_PHYCR_MIIWR), 147 FTGMAC100_MDIO_TIMEOUT_USEC); 148 if (ret) { 149 pr_err("%s: mdio write failed (phy:%d reg:%x)\n", 150 priv->phydev->dev->name, phy_addr, reg_addr); 151 } 152 153 return ret; 154 } 155 156 static int ftgmac100_mdio_init(struct udevice *dev) 157 { 158 struct ftgmac100_data *priv = dev_get_priv(dev); 159 struct mii_dev *bus; 160 int ret; 161 162 bus = mdio_alloc(); 163 if (!bus) 164 return -ENOMEM; 165 166 printf("ftgmac100_mdio_init xxxxxxxxxx %x \n", priv->mdio_addr); 167 168 if(priv->mdio_addr) { 169 printf("new mdio addr %x ~~~~~~~~~~~~~~xxxxxxxxxx \n", priv->mdio_addr); 170 bus->read = aspeed_mdio_read; 171 bus->write = aspeed_mdio_write; 172 } else { 173 bus->read = ftgmac100_mdio_read; 174 bus->write = ftgmac100_mdio_write; 175 } 176 bus->priv = priv; 177 178 ret = mdio_register_seq(bus, dev->seq); 179 if (ret) { 180 free(bus); 181 return ret; 182 } 183 184 priv->bus = bus; 185 186 return 0; 187 } 188 189 static int ftgmac100_phy_adjust_link(struct ftgmac100_data *priv) 190 { 191 struct ftgmac100 *ftgmac100 = priv->iobase; 192 struct phy_device *phydev = priv->phydev; 193 u32 maccr; 194 195 if (!phydev->link) { 196 dev_err(phydev->dev, "No link\n"); 197 return -EREMOTEIO; 198 } 199 200 /* read MAC control register and clear related bits */ 201 maccr = readl(&ftgmac100->maccr) & 202 ~(FTGMAC100_MACCR_GIGA_MODE | 203 FTGMAC100_MACCR_FAST_MODE | 204 FTGMAC100_MACCR_FULLDUP); 205 206 if (phy_interface_is_rgmii(phydev) && phydev->speed == 1000) 207 maccr |= FTGMAC100_MACCR_GIGA_MODE; 208 209 if (phydev->speed == 100) 210 maccr |= FTGMAC100_MACCR_FAST_MODE; 211 212 if (phydev->duplex) 213 maccr |= FTGMAC100_MACCR_FULLDUP; 214 215 /* update MII config into maccr */ 216 writel(maccr, &ftgmac100->maccr); 217 218 return 0; 219 } 220 221 static int ftgmac100_phy_init(struct udevice *dev) 222 { 223 struct ftgmac100_data *priv = dev_get_priv(dev); 224 struct phy_device *phydev; 225 int ret; 226 227 phydev = phy_connect(priv->bus, priv->phy_addr, dev, priv->phy_mode); 228 if (!phydev) 229 return -ENODEV; 230 231 phydev->supported &= PHY_GBIT_FEATURES; 232 if (priv->max_speed) { 233 ret = phy_set_supported(phydev, priv->max_speed); 234 if (ret) 235 return ret; 236 } 237 phydev->advertising = phydev->supported; 238 priv->phydev = phydev; 239 phy_config(phydev); 240 241 return 0; 242 } 243 244 /* 245 * Reset MAC 246 */ 247 static void ftgmac100_reset(struct ftgmac100_data *priv) 248 { 249 struct ftgmac100 *ftgmac100 = priv->iobase; 250 251 debug("%s()\n", __func__); 252 253 setbits_le32(&ftgmac100->maccr, FTGMAC100_MACCR_SW_RST); 254 255 while (readl(&ftgmac100->maccr) & FTGMAC100_MACCR_SW_RST) 256 ; 257 } 258 259 /* 260 * Set MAC address 261 */ 262 static int ftgmac100_set_mac(struct ftgmac100_data *priv, 263 const unsigned char *mac) 264 { 265 struct ftgmac100 *ftgmac100 = priv->iobase; 266 unsigned int maddr = mac[0] << 8 | mac[1]; 267 unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; 268 269 debug("%s(%x %x)\n", __func__, maddr, laddr); 270 271 writel(maddr, &ftgmac100->mac_madr); 272 writel(laddr, &ftgmac100->mac_ladr); 273 274 return 0; 275 } 276 277 /* 278 * disable transmitter, receiver 279 */ 280 static void ftgmac100_stop(struct udevice *dev) 281 { 282 struct ftgmac100_data *priv = dev_get_priv(dev); 283 struct ftgmac100 *ftgmac100 = priv->iobase; 284 285 debug("%s()\n", __func__); 286 287 writel(0, &ftgmac100->maccr); 288 289 phy_shutdown(priv->phydev); 290 } 291 292 static int ftgmac100_start(struct udevice *dev) 293 { 294 struct eth_pdata *plat = dev_get_platdata(dev); 295 struct ftgmac100_data *priv = dev_get_priv(dev); 296 struct ftgmac100 *ftgmac100 = priv->iobase; 297 struct phy_device *phydev = priv->phydev; 298 unsigned int maccr; 299 ulong start, end; 300 int ret; 301 int i; 302 303 debug("%s()\n", __func__); 304 305 ftgmac100_reset(priv); 306 307 /* set the ethernet address */ 308 ftgmac100_set_mac(priv, plat->enetaddr); 309 310 /* disable all interrupts */ 311 writel(0, &ftgmac100->ier); 312 313 /* initialize descriptors */ 314 priv->tx_index = 0; 315 priv->rx_index = 0; 316 317 for (i = 0; i < PKTBUFSTX; i++) { 318 priv->txdes[i].txdes3 = 0; 319 priv->txdes[i].txdes0 = 0; 320 } 321 priv->txdes[PKTBUFSTX - 1].txdes0 = priv->txdes0_edotr_mask; 322 323 start = (ulong)&priv->txdes[0]; 324 end = start + roundup(sizeof(priv->txdes), ARCH_DMA_MINALIGN); 325 flush_dcache_range(start, end); 326 327 for (i = 0; i < PKTBUFSRX; i++) { 328 priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i]; 329 priv->rxdes[i].rxdes0 = 0; 330 } 331 priv->rxdes[PKTBUFSRX - 1].rxdes0 = priv->rxdes0_edorr_mask; 332 333 start = (ulong)&priv->rxdes[0]; 334 end = start + roundup(sizeof(priv->rxdes), ARCH_DMA_MINALIGN); 335 flush_dcache_range(start, end); 336 337 /* transmit ring */ 338 writel((u32)priv->txdes, &ftgmac100->txr_badr); 339 340 /* receive ring */ 341 writel((u32)priv->rxdes, &ftgmac100->rxr_badr); 342 343 /* poll receive descriptor automatically */ 344 writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc); 345 346 /* config receive buffer size register */ 347 writel(FTGMAC100_RBSR_SIZE(FTGMAC100_RBSR_DEFAULT), &ftgmac100->rbsr); 348 349 /* enable transmitter, receiver */ 350 maccr = FTGMAC100_MACCR_TXMAC_EN | 351 FTGMAC100_MACCR_RXMAC_EN | 352 FTGMAC100_MACCR_TXDMA_EN | 353 FTGMAC100_MACCR_RXDMA_EN | 354 FTGMAC100_MACCR_CRC_APD | 355 FTGMAC100_MACCR_FULLDUP | 356 FTGMAC100_MACCR_RX_RUNT | 357 FTGMAC100_MACCR_RX_BROADPKT; 358 359 writel(maccr, &ftgmac100->maccr); 360 361 ret = phy_startup(phydev); 362 if (ret) { 363 dev_err(phydev->dev, "Could not start PHY\n"); 364 return ret; 365 } 366 367 ret = ftgmac100_phy_adjust_link(priv); 368 if (ret) { 369 dev_err(phydev->dev, "Could not adjust link\n"); 370 return ret; 371 } 372 373 printf("%s: link up, %d Mbps %s-duplex mac:%pM\n", phydev->dev->name, 374 phydev->speed, phydev->duplex ? "full" : "half", plat->enetaddr); 375 376 return 0; 377 } 378 379 static int ftgmac100_free_pkt(struct udevice *dev, uchar *packet, int length) 380 { 381 struct ftgmac100_data *priv = dev_get_priv(dev); 382 struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index]; 383 ulong des_start = (ulong)curr_des; 384 ulong des_end = des_start + 385 roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN); 386 387 /* Release buffer to DMA and flush descriptor */ 388 curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY; 389 flush_dcache_range(des_start, des_end); 390 391 /* Move to next descriptor */ 392 priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX; 393 394 return 0; 395 } 396 397 /* 398 * Get a data block via Ethernet 399 */ 400 static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp) 401 { 402 struct ftgmac100_data *priv = dev_get_priv(dev); 403 struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index]; 404 unsigned short rxlen; 405 ulong des_start = (ulong)curr_des; 406 ulong des_end = des_start + 407 roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN); 408 ulong data_start = curr_des->rxdes3; 409 ulong data_end; 410 411 invalidate_dcache_range(des_start, des_end); 412 413 if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY)) 414 return -EAGAIN; 415 416 if (curr_des->rxdes0 & (FTGMAC100_RXDES0_RX_ERR | 417 FTGMAC100_RXDES0_CRC_ERR | 418 FTGMAC100_RXDES0_FTL | 419 FTGMAC100_RXDES0_RUNT | 420 FTGMAC100_RXDES0_RX_ODD_NB)) { 421 return -EAGAIN; 422 } 423 424 rxlen = FTGMAC100_RXDES0_VDBC(curr_des->rxdes0); 425 426 debug("%s(): RX buffer %d, %x received\n", 427 __func__, priv->rx_index, rxlen); 428 429 /* Invalidate received data */ 430 data_end = data_start + roundup(rxlen, ARCH_DMA_MINALIGN); 431 invalidate_dcache_range(data_start, data_end); 432 *packetp = (uchar *)data_start; 433 434 return rxlen; 435 } 436 437 static u32 ftgmac100_read_txdesc(const void *desc) 438 { 439 const struct ftgmac100_txdes *txdes = desc; 440 ulong des_start = (ulong)txdes; 441 ulong des_end = des_start + roundup(sizeof(*txdes), ARCH_DMA_MINALIGN); 442 443 invalidate_dcache_range(des_start, des_end); 444 445 return txdes->txdes0; 446 } 447 448 BUILD_WAIT_FOR_BIT(ftgmac100_txdone, u32, ftgmac100_read_txdesc) 449 450 /* 451 * Send a data block via Ethernet 452 */ 453 static int ftgmac100_send(struct udevice *dev, void *packet, int length) 454 { 455 struct ftgmac100_data *priv = dev_get_priv(dev); 456 struct ftgmac100 *ftgmac100 = priv->iobase; 457 struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index]; 458 ulong des_start = (ulong)curr_des; 459 ulong des_end = des_start + 460 roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN); 461 ulong data_start; 462 ulong data_end; 463 int rc; 464 465 invalidate_dcache_range(des_start, des_end); 466 467 if (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) { 468 dev_err(dev, "no TX descriptor available\n"); 469 return -EPERM; 470 } 471 472 debug("%s(%x, %x)\n", __func__, (int)packet, length); 473 474 length = (length < ETH_ZLEN) ? ETH_ZLEN : length; 475 476 curr_des->txdes3 = (unsigned int)packet; 477 478 /* Flush data to be sent */ 479 data_start = curr_des->txdes3; 480 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); 481 flush_dcache_range(data_start, data_end); 482 483 /* Only one segment on TXBUF */ 484 curr_des->txdes0 &= priv->txdes0_edotr_mask; 485 curr_des->txdes0 |= FTGMAC100_TXDES0_FTS | 486 FTGMAC100_TXDES0_LTS | 487 FTGMAC100_TXDES0_TXBUF_SIZE(length) | 488 FTGMAC100_TXDES0_TXDMA_OWN ; 489 490 /* Flush modified buffer descriptor */ 491 flush_dcache_range(des_start, des_end); 492 493 /* Start transmit */ 494 writel(1, &ftgmac100->txpd); 495 496 rc = wait_for_bit_ftgmac100_txdone(curr_des, 497 FTGMAC100_TXDES0_TXDMA_OWN, false, 498 FTGMAC100_TX_TIMEOUT_MS, true); 499 if (rc) 500 return rc; 501 502 debug("%s(): packet sent\n", __func__); 503 504 /* Move to next descriptor */ 505 priv->tx_index = (priv->tx_index + 1) % PKTBUFSTX; 506 507 return 0; 508 } 509 510 static int ftgmac100_write_hwaddr(struct udevice *dev) 511 { 512 struct eth_pdata *pdata = dev_get_platdata(dev); 513 struct ftgmac100_data *priv = dev_get_priv(dev); 514 515 return ftgmac100_set_mac(priv, pdata->enetaddr); 516 } 517 518 static int ftgmac100_ofdata_to_platdata(struct udevice *dev) 519 { 520 struct eth_pdata *pdata = dev_get_platdata(dev); 521 struct ftgmac100_data *priv = dev_get_priv(dev); 522 const char *phy_mode; 523 524 pdata->iobase = devfdt_get_addr(dev); 525 pdata->phy_interface = -1; 526 phy_mode = dev_read_string(dev, "phy-mode"); 527 if (phy_mode) 528 pdata->phy_interface = phy_get_interface_by_name(phy_mode); 529 if (pdata->phy_interface == -1) { 530 dev_err(dev, "Invalid PHY interface '%s'\n", phy_mode); 531 return -EINVAL; 532 } 533 534 printf("pdata->phy_interface %d \n", pdata->phy_interface); 535 pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0); 536 537 if (dev_get_driver_data(dev) == FTGMAC100_MODEL_NEW_ASPEED) { 538 printf("ftg ast2600 ~~~~~~~~~~~~~~~~~~~~ \n"); 539 priv->mdio_addr = devfdt_get_addr_index(dev, 1); 540 printf("ftg ast2600 ~~~~~~~~~~~~~~~~~~~~ priv->mdio_addr %x \n", priv->mdio_addr); 541 542 } 543 if ((dev_get_driver_data(dev) == FTGMAC100_MODEL_ASPEED) || 544 (dev_get_driver_data(dev) == FTGMAC100_MODEL_NEW_ASPEED)){ 545 priv->rxdes0_edorr_mask = BIT(30); 546 priv->txdes0_edotr_mask = BIT(30); 547 } else { 548 priv->rxdes0_edorr_mask = BIT(15); 549 priv->txdes0_edotr_mask = BIT(15); 550 } 551 552 return clk_get_bulk(dev, &priv->clks); 553 } 554 555 static int ftgmac100_probe(struct udevice *dev) 556 { 557 struct eth_pdata *pdata = dev_get_platdata(dev); 558 struct ftgmac100_data *priv = dev_get_priv(dev); 559 int ret; 560 561 priv->iobase = (struct ftgmac100 *)pdata->iobase; 562 priv->phy_mode = pdata->phy_interface; 563 priv->max_speed = pdata->max_speed; 564 priv->phy_addr = 0; 565 566 ret = clk_enable_bulk(&priv->clks); 567 if (ret) 568 goto out; 569 570 ret = ftgmac100_mdio_init(dev); 571 if (ret) { 572 dev_err(dev, "Failed to initialize mdiobus: %d\n", ret); 573 goto out; 574 } 575 576 ret = ftgmac100_phy_init(dev); 577 if (ret) { 578 dev_err(dev, "Failed to initialize PHY: %d\n", ret); 579 goto out; 580 } 581 582 out: 583 if (ret) 584 clk_release_bulk(&priv->clks); 585 586 return ret; 587 } 588 589 static int ftgmac100_remove(struct udevice *dev) 590 { 591 struct ftgmac100_data *priv = dev_get_priv(dev); 592 593 free(priv->phydev); 594 mdio_unregister(priv->bus); 595 mdio_free(priv->bus); 596 clk_release_bulk(&priv->clks); 597 598 return 0; 599 } 600 601 static const struct eth_ops ftgmac100_ops = { 602 .start = ftgmac100_start, 603 .send = ftgmac100_send, 604 .recv = ftgmac100_recv, 605 .stop = ftgmac100_stop, 606 .free_pkt = ftgmac100_free_pkt, 607 .write_hwaddr = ftgmac100_write_hwaddr, 608 }; 609 610 static const struct udevice_id ftgmac100_ids[] = { 611 { .compatible = "faraday,ftgmac100", .data = FTGMAC100_MODEL_FARADAY }, 612 { .compatible = "aspeed,ast2500-mac", .data = FTGMAC100_MODEL_ASPEED }, 613 { .compatible = "aspeed,ast2600-mac", .data = FTGMAC100_MODEL_NEW_ASPEED }, 614 { } 615 }; 616 617 U_BOOT_DRIVER(ftgmac100) = { 618 .name = "ftgmac100", 619 .id = UCLASS_ETH, 620 .of_match = ftgmac100_ids, 621 .ofdata_to_platdata = ftgmac100_ofdata_to_platdata, 622 .probe = ftgmac100_probe, 623 .remove = ftgmac100_remove, 624 .ops = &ftgmac100_ops, 625 .priv_auto_alloc_size = sizeof(struct ftgmac100_data), 626 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 627 .flags = DM_FLAG_ALLOC_PRIV_DMA, 628 }; 629