1 /* 2 * (C) Copyright 2000-2004 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * (C) Copyright 2007 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27 #include <common.h> 28 #include <malloc.h> 29 #include <command.h> 30 #include <config.h> 31 #include <net.h> 32 #include <miiphy.h> 33 34 #ifdef CONFIG_FSLDMAFEC 35 #undef ET_DEBUG 36 #undef MII_DEBUG 37 38 /* Ethernet Transmit and Receive Buffers */ 39 #define DBUF_LENGTH 1520 40 #define PKT_MAXBUF_SIZE 1518 41 #define PKT_MINBUF_SIZE 64 42 #define PKT_MAXBLR_SIZE 1536 43 #define LAST_PKTBUFSRX PKTBUFSRX - 1 44 #define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY) 45 #define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST) 46 #define FIFO_ERRSTAT (FIFO_STAT_RXW | FIFO_STAT_UF | FIFO_STAT_OF) 47 48 /* RxBD bits definitions */ 49 #define BD_ENET_RX_ERR (BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \ 50 BD_ENET_RX_OV | BD_ENET_RX_TR) 51 52 #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) 53 #include <asm/immap.h> 54 #include <asm/fsl_mcdmafec.h> 55 56 #include "MCD_dma.h" 57 58 DECLARE_GLOBAL_DATA_PTR; 59 60 struct fec_info_dma fec_info[] = { 61 #ifdef CFG_FEC0_IOBASE 62 { 63 0, /* index */ 64 CFG_FEC0_IOBASE, /* io base */ 65 CFG_FEC0_PINMUX, /* gpio pin muxing */ 66 CFG_FEC0_MIIBASE, /* mii base */ 67 -1, /* phy_addr */ 68 0, /* duplex and speed */ 69 0, /* phy name */ 70 0, /* phyname init */ 71 0, /* RX BD */ 72 0, /* TX BD */ 73 0, /* rx Index */ 74 0, /* tx Index */ 75 0, /* tx buffer */ 76 0, /* initialized flag */ 77 (struct fec_info_dma *)-1, /* next */ 78 FEC0_RX_TASK, /* rxTask */ 79 FEC0_TX_TASK, /* txTask */ 80 FEC0_RX_PRIORITY, /* rxPri */ 81 FEC0_TX_PRIORITY, /* txPri */ 82 FEC0_RX_INIT, /* rxInit */ 83 FEC0_TX_INIT, /* txInit */ 84 0, /* usedTbdIndex */ 85 0, /* cleanTbdNum */ 86 }, 87 #endif 88 #ifdef CFG_FEC1_IOBASE 89 { 90 1, /* index */ 91 CFG_FEC1_IOBASE, /* io base */ 92 CFG_FEC1_PINMUX, /* gpio pin muxing */ 93 CFG_FEC1_MIIBASE, /* mii base */ 94 -1, /* phy_addr */ 95 0, /* duplex and speed */ 96 0, /* phy name */ 97 0, /* phy name init */ 98 #ifdef CFG_DMA_USE_INTSRAM 99 DBUF_LENGTH, /* RX BD */ 100 #else 101 0, /* RX BD */ 102 #endif 103 0, /* TX BD */ 104 0, /* rx Index */ 105 0, /* tx Index */ 106 0, /* tx buffer */ 107 0, /* initialized flag */ 108 (struct fec_info_dma *)-1, /* next */ 109 FEC1_RX_TASK, /* rxTask */ 110 FEC1_TX_TASK, /* txTask */ 111 FEC1_RX_PRIORITY, /* rxPri */ 112 FEC1_TX_PRIORITY, /* txPri */ 113 FEC1_RX_INIT, /* rxInit */ 114 FEC1_TX_INIT, /* txInit */ 115 0, /* usedTbdIndex */ 116 0, /* cleanTbdNum */ 117 } 118 #endif 119 }; 120 121 static int fec_send(struct eth_device *dev, volatile void *packet, int length); 122 static int fec_recv(struct eth_device *dev); 123 static int fec_init(struct eth_device *dev, bd_t * bd); 124 static void fec_halt(struct eth_device *dev); 125 126 #ifdef ET_DEBUG 127 static void dbg_fec_regs(struct eth_device *dev) 128 { 129 struct fec_info_dma *info = dev->priv; 130 volatile fecdma_t *fecp = (fecdma_t *) (info->iobase); 131 132 printf("=====\n"); 133 printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir); 134 printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr); 135 printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr); 136 printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr); 137 printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr); 138 printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc); 139 printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr); 140 printf("r hash %x - %x\n", (int)&fecp->rhr, fecp->rhr); 141 printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr); 142 printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr); 143 printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur); 144 printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd); 145 printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur); 146 printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr); 147 printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur); 148 printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr); 149 printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr); 150 printf("r_fdata %x - %x\n", (int)&fecp->rfdr, fecp->rfdr); 151 printf("r_fstat %x - %x\n", (int)&fecp->rfsr, fecp->rfsr); 152 printf("r_fctrl %x - %x\n", (int)&fecp->rfcr, fecp->rfcr); 153 printf("r_flrfp %x - %x\n", (int)&fecp->rlrfp, fecp->rlrfp); 154 printf("r_flwfp %x - %x\n", (int)&fecp->rlwfp, fecp->rlwfp); 155 printf("r_frfar %x - %x\n", (int)&fecp->rfar, fecp->rfar); 156 printf("r_frfrp %x - %x\n", (int)&fecp->rfrp, fecp->rfrp); 157 printf("r_frfwp %x - %x\n", (int)&fecp->rfwp, fecp->rfwp); 158 printf("t_fdata %x - %x\n", (int)&fecp->tfdr, fecp->tfdr); 159 printf("t_fstat %x - %x\n", (int)&fecp->tfsr, fecp->tfsr); 160 printf("t_fctrl %x - %x\n", (int)&fecp->tfcr, fecp->tfcr); 161 printf("t_flrfp %x - %x\n", (int)&fecp->tlrfp, fecp->tlrfp); 162 printf("t_flwfp %x - %x\n", (int)&fecp->tlwfp, fecp->tlwfp); 163 printf("t_ftfar %x - %x\n", (int)&fecp->tfar, fecp->tfar); 164 printf("t_ftfrp %x - %x\n", (int)&fecp->tfrp, fecp->tfrp); 165 printf("t_ftfwp %x - %x\n", (int)&fecp->tfwp, fecp->tfwp); 166 printf("frst %x - %x\n", (int)&fecp->frst, fecp->frst); 167 printf("ctcwr %x - %x\n", (int)&fecp->ctcwr, fecp->ctcwr); 168 } 169 #endif 170 171 static void set_fec_duplex_speed(volatile fecdma_t * fecp, bd_t * bd, 172 int dup_spd) 173 { 174 if ((dup_spd >> 16) == FULL) { 175 /* Set maximum frame length */ 176 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE | 177 FEC_RCR_PROM | 0x100; 178 fecp->tcr = FEC_TCR_FDEN; 179 } else { 180 /* Half duplex mode */ 181 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | 182 FEC_RCR_MII_MODE | FEC_RCR_DRT; 183 fecp->tcr &= ~FEC_TCR_FDEN; 184 } 185 186 if ((dup_spd & 0xFFFF) == _100BASET) { 187 #ifdef MII_DEBUG 188 printf("100Mbps\n"); 189 #endif 190 bd->bi_ethspeed = 100; 191 } else { 192 #ifdef MII_DEBUG 193 printf("10Mbps\n"); 194 #endif 195 bd->bi_ethspeed = 10; 196 } 197 } 198 199 static int fec_send(struct eth_device *dev, volatile void *packet, int length) 200 { 201 struct fec_info_dma *info = dev->priv; 202 cbd_t *pTbd, *pUsedTbd; 203 u16 phyStatus; 204 205 miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &phyStatus); 206 207 /* process all the consumed TBDs */ 208 while (info->cleanTbdNum < CFG_TX_ETH_BUFFER) { 209 pUsedTbd = &info->txbd[info->usedTbdIdx]; 210 if (pUsedTbd->cbd_sc & BD_ENET_TX_READY) { 211 #ifdef ET_DEBUG 212 printf("Cannot clean TBD %d, in use\n", 213 info->cleanTbdNum); 214 #endif 215 return 0; 216 } 217 218 /* clean this buffer descriptor */ 219 if (info->usedTbdIdx == (CFG_TX_ETH_BUFFER - 1)) 220 pUsedTbd->cbd_sc = BD_ENET_TX_WRAP; 221 else 222 pUsedTbd->cbd_sc = 0; 223 224 /* update some indeces for a correct handling of the TBD ring */ 225 info->cleanTbdNum++; 226 info->usedTbdIdx = (info->usedTbdIdx + 1) % CFG_TX_ETH_BUFFER; 227 } 228 229 /* Check for valid length of data. */ 230 if ((length > 1500) || (length <= 0)) { 231 return -1; 232 } 233 234 /* Check the number of vacant TxBDs. */ 235 if (info->cleanTbdNum < 1) { 236 printf("No available TxBDs ...\n"); 237 return -1; 238 } 239 240 /* Get the first TxBD to send the mac header */ 241 pTbd = &info->txbd[info->txIdx]; 242 pTbd->cbd_datlen = length; 243 pTbd->cbd_bufaddr = (u32) packet; 244 pTbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY; 245 info->txIdx = (info->txIdx + 1) % CFG_TX_ETH_BUFFER; 246 247 /* Enable DMA transmit task */ 248 MCD_continDma(info->txTask); 249 250 info->cleanTbdNum -= 1; 251 252 /* wait until frame is sent . */ 253 while (pTbd->cbd_sc & BD_ENET_TX_READY) { 254 udelay(10); 255 } 256 257 return (int)(info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS); 258 } 259 260 static int fec_recv(struct eth_device *dev) 261 { 262 struct fec_info_dma *info = dev->priv; 263 volatile fecdma_t *fecp = (fecdma_t *) (info->iobase); 264 265 cbd_t *pRbd = &info->rxbd[info->rxIdx]; 266 u32 ievent; 267 int frame_length, len = 0; 268 269 /* Check if any critical events have happened */ 270 ievent = fecp->eir; 271 if (ievent != 0) { 272 fecp->eir = ievent; 273 274 if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) { 275 printf("fec_recv: error\n"); 276 fec_halt(dev); 277 fec_init(dev, NULL); 278 return 0; 279 } 280 281 if (ievent & FEC_EIR_HBERR) { 282 /* Heartbeat error */ 283 fecp->tcr |= FEC_TCR_GTS; 284 } 285 286 if (ievent & FEC_EIR_GRA) { 287 /* Graceful stop complete */ 288 if (fecp->tcr & FEC_TCR_GTS) { 289 printf("fec_recv: tcr_gts\n"); 290 fec_halt(dev); 291 fecp->tcr &= ~FEC_TCR_GTS; 292 fec_init(dev, NULL); 293 } 294 } 295 } 296 297 if (!(pRbd->cbd_sc & BD_ENET_RX_EMPTY)) { 298 if ((pRbd->cbd_sc & BD_ENET_RX_LAST) 299 && !(pRbd->cbd_sc & BD_ENET_RX_ERR) 300 && ((pRbd->cbd_datlen - 4) > 14)) { 301 302 /* Get buffer address and size */ 303 frame_length = pRbd->cbd_datlen - 4; 304 305 /* Fill the buffer and pass it to upper layers */ 306 NetReceive((volatile uchar *)pRbd->cbd_bufaddr, 307 frame_length); 308 len = frame_length; 309 } 310 311 /* Reset buffer descriptor as empty */ 312 if ((info->rxIdx) == (PKTBUFSRX - 1)) 313 pRbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); 314 else 315 pRbd->cbd_sc = BD_ENET_RX_EMPTY; 316 317 pRbd->cbd_datlen = PKTSIZE_ALIGN; 318 319 /* Now, we have an empty RxBD, restart the DMA receive task */ 320 MCD_continDma(info->rxTask); 321 322 /* Increment BD count */ 323 info->rxIdx = (info->rxIdx + 1) % PKTBUFSRX; 324 } 325 326 return len; 327 } 328 329 static void fec_set_hwaddr(volatile fecdma_t * fecp, u8 * mac) 330 { 331 u8 currByte; /* byte for which to compute the CRC */ 332 int byte; /* loop - counter */ 333 int bit; /* loop - counter */ 334 u32 crc = 0xffffffff; /* initial value */ 335 336 for (byte = 0; byte < 6; byte++) { 337 currByte = mac[byte]; 338 for (bit = 0; bit < 8; bit++) { 339 if ((currByte & 0x01) ^ (crc & 0x01)) { 340 crc >>= 1; 341 crc = crc ^ 0xedb88320; 342 } else { 343 crc >>= 1; 344 } 345 currByte >>= 1; 346 } 347 } 348 349 crc = crc >> 26; 350 351 /* Set individual hash table register */ 352 if (crc >= 32) { 353 fecp->ialr = (1 << (crc - 32)); 354 fecp->iaur = 0; 355 } else { 356 fecp->ialr = 0; 357 fecp->iaur = (1 << crc); 358 } 359 360 /* Set physical address */ 361 fecp->palr = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3]; 362 fecp->paur = (mac[4] << 24) + (mac[5] << 16) + 0x8808; 363 364 /* Clear multicast address hash table */ 365 fecp->gaur = 0; 366 fecp->galr = 0; 367 } 368 369 static int fec_init(struct eth_device *dev, bd_t * bd) 370 { 371 struct fec_info_dma *info = dev->priv; 372 volatile fecdma_t *fecp = (fecdma_t *) (info->iobase); 373 int i; 374 375 #ifdef ET_DEBUG 376 printf("fec_init: iobase 0x%08x ...\n", info->iobase); 377 #endif 378 379 fecpin_setclear(dev, 1); 380 381 fec_halt(dev); 382 383 #if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \ 384 defined (CFG_DISCOVER_PHY) 385 386 mii_init(); 387 388 set_fec_duplex_speed(fecp, bd, info->dup_spd); 389 #else 390 #ifndef CFG_DISCOVER_PHY 391 set_fec_duplex_speed(fecp, bd, (FECDUPLEX << 16) | FECSPEED); 392 #endif /* ifndef CFG_DISCOVER_PHY */ 393 #endif /* CONFIG_CMD_MII || CONFIG_MII */ 394 395 /* We use strictly polling mode only */ 396 fecp->eimr = 0; 397 398 /* Clear any pending interrupt */ 399 fecp->eir = 0xffffffff; 400 401 /* Set station address */ 402 if ((u32) fecp == CFG_FEC0_IOBASE) { 403 fec_set_hwaddr(fecp, bd->bi_enetaddr); 404 } else { 405 fec_set_hwaddr(fecp, bd->bi_enet1addr); 406 } 407 408 /* Set Opcode/Pause Duration Register */ 409 fecp->opd = 0x00010020; 410 411 /* Setup Buffers and Buffer Desriptors */ 412 info->rxIdx = 0; 413 info->txIdx = 0; 414 415 /* Setup Receiver Buffer Descriptors (13.14.24.18) 416 * Settings: Empty, Wrap */ 417 for (i = 0; i < PKTBUFSRX; i++) { 418 info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; 419 info->rxbd[i].cbd_datlen = PKTSIZE_ALIGN; 420 info->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i]; 421 } 422 info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; 423 424 /* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) 425 * Settings: Last, Tx CRC */ 426 for (i = 0; i < CFG_TX_ETH_BUFFER; i++) { 427 info->txbd[i].cbd_sc = 0; 428 info->txbd[i].cbd_datlen = 0; 429 info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]); 430 } 431 info->txbd[CFG_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP; 432 433 info->usedTbdIdx = 0; 434 info->cleanTbdNum = CFG_TX_ETH_BUFFER; 435 436 /* Set Rx FIFO alarm and granularity value */ 437 fecp->rfcr = 0x0c000000; 438 fecp->rfar = 0x0000030c; 439 440 /* Set Tx FIFO granularity value */ 441 fecp->tfcr = FIFO_CTRL_FRAME | FIFO_CTRL_GR(6) | 0x00040000; 442 fecp->tfar = 0x00000080; 443 444 fecp->tfwr = 0x2; 445 fecp->ctcwr = 0x03000000; 446 447 /* Enable DMA receive task */ 448 MCD_startDma(info->rxTask, /* Dma channel */ 449 (s8 *) info->rxbd, /*Source Address */ 450 0, /* Source increment */ 451 (s8 *) (&fecp->rfdr), /* dest */ 452 4, /* dest increment */ 453 0, /* DMA size */ 454 4, /* xfer size */ 455 info->rxInit, /* initiator */ 456 info->rxPri, /* priority */ 457 (MCD_FECRX_DMA | MCD_TT_FLAGS_DEF), /* Flags */ 458 (MCD_NO_CSUM | MCD_NO_BYTE_SWAP) /* Function description */ 459 ); 460 461 /* Enable DMA tx task with no ready buffer descriptors */ 462 MCD_startDma(info->txTask, /* Dma channel */ 463 (s8 *) info->txbd, /*Source Address */ 464 0, /* Source increment */ 465 (s8 *) (&fecp->tfdr), /* dest */ 466 4, /* dest incr */ 467 0, /* DMA size */ 468 4, /* xfer size */ 469 info->txInit, /* initiator */ 470 info->txPri, /* priority */ 471 (MCD_FECTX_DMA | MCD_TT_FLAGS_DEF), /* Flags */ 472 (MCD_NO_CSUM | MCD_NO_BYTE_SWAP) /* Function description */ 473 ); 474 475 /* Now enable the transmit and receive processing */ 476 fecp->ecr |= FEC_ECR_ETHER_EN; 477 478 return 1; 479 } 480 481 static void fec_halt(struct eth_device *dev) 482 { 483 struct fec_info_dma *info = dev->priv; 484 volatile fecdma_t *fecp = (fecdma_t *) (info->iobase); 485 int counter = 0xffff; 486 487 /* issue graceful stop command to the FEC transmitter if necessary */ 488 fecp->tcr |= FEC_TCR_GTS; 489 490 /* wait for graceful stop to register */ 491 while ((counter--) && (!(fecp->eir & FEC_EIR_GRA))) ; 492 493 /* Disable DMA tasks */ 494 MCD_killDma(info->txTask); 495 MCD_killDma(info->rxTask);; 496 497 /* Disable the Ethernet Controller */ 498 fecp->ecr &= ~FEC_ECR_ETHER_EN; 499 500 /* Clear FIFO status registers */ 501 fecp->rfsr &= FIFO_ERRSTAT; 502 fecp->tfsr &= FIFO_ERRSTAT; 503 504 fecp->frst = 0x01000000; 505 506 /* Issue a reset command to the FEC chip */ 507 fecp->ecr |= FEC_ECR_RESET; 508 509 /* wait at least 20 clock cycles */ 510 udelay(10000); 511 512 #ifdef ET_DEBUG 513 printf("Ethernet task stopped\n"); 514 #endif 515 } 516 517 int mcdmafec_initialize(bd_t * bis) 518 { 519 struct eth_device *dev; 520 int i; 521 #ifdef CFG_DMA_USE_INTSRAM 522 u32 tmp = CFG_INTSRAM + 0x2000; 523 #endif 524 525 for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) { 526 527 dev = 528 (struct eth_device *)memalign(CFG_CACHELINE_SIZE, 529 sizeof *dev); 530 if (dev == NULL) 531 hang(); 532 533 memset(dev, 0, sizeof(*dev)); 534 535 sprintf(dev->name, "FEC%d", fec_info[i].index); 536 537 dev->priv = &fec_info[i]; 538 dev->init = fec_init; 539 dev->halt = fec_halt; 540 dev->send = fec_send; 541 dev->recv = fec_recv; 542 543 /* setup Receive and Transmit buffer descriptor */ 544 #ifdef CFG_DMA_USE_INTSRAM 545 fec_info[i].rxbd = (int)fec_info[i].rxbd + tmp; 546 tmp = fec_info[i].rxbd; 547 fec_info[i].txbd = 548 (int)fec_info[i].txbd + tmp + (PKTBUFSRX * sizeof(cbd_t)); 549 tmp = fec_info[i].txbd; 550 fec_info[i].txbuf = 551 (int)fec_info[i].txbuf + tmp + 552 (CFG_TX_ETH_BUFFER * sizeof(cbd_t)); 553 tmp = fec_info[i].txbuf; 554 #else 555 fec_info[i].rxbd = 556 (cbd_t *) memalign(CFG_CACHELINE_SIZE, 557 (PKTBUFSRX * sizeof(cbd_t))); 558 fec_info[i].txbd = 559 (cbd_t *) memalign(CFG_CACHELINE_SIZE, 560 (CFG_TX_ETH_BUFFER * sizeof(cbd_t))); 561 fec_info[i].txbuf = 562 (char *)memalign(CFG_CACHELINE_SIZE, DBUF_LENGTH); 563 #endif 564 565 #ifdef ET_DEBUG 566 printf("rxbd %x txbd %x\n", 567 (int)fec_info[i].rxbd, (int)fec_info[i].txbd); 568 #endif 569 570 fec_info[i].phy_name = (char *)memalign(CFG_CACHELINE_SIZE, 32); 571 572 eth_register(dev); 573 574 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 575 miiphy_register(dev->name, 576 mcffec_miiphy_read, mcffec_miiphy_write); 577 #endif 578 579 if (i > 0) 580 fec_info[i - 1].next = &fec_info[i]; 581 } 582 fec_info[i - 1].next = &fec_info[0]; 583 584 /* default speed */ 585 bis->bi_ethspeed = 10; 586 587 return 1; 588 } 589 590 #endif /* CONFIG_CMD_NET && CONFIG_NET_MULTI */ 591 #endif /* CONFIG_FSLDMAFEC */ 592