1 /* 2 * (C) Copyright 2000-2004 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * (C) Copyright 2007 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27 #include <common.h> 28 #include <malloc.h> 29 #include <command.h> 30 #include <config.h> 31 #include <net.h> 32 #include <miiphy.h> 33 34 #ifdef CONFIG_FSLDMAFEC 35 #undef ET_DEBUG 36 #undef MII_DEBUG 37 38 /* Ethernet Transmit and Receive Buffers */ 39 #define DBUF_LENGTH 1520 40 #define PKT_MAXBUF_SIZE 1518 41 #define PKT_MINBUF_SIZE 64 42 #define PKT_MAXBLR_SIZE 1536 43 #define LAST_PKTBUFSRX PKTBUFSRX - 1 44 #define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY) 45 #define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST) 46 #define FIFO_ERRSTAT (FIFO_STAT_RXW | FIFO_STAT_UF | FIFO_STAT_OF) 47 48 /* RxBD bits definitions */ 49 #define BD_ENET_RX_ERR (BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \ 50 BD_ENET_RX_OV | BD_ENET_RX_TR) 51 52 #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) 53 #include <asm/immap.h> 54 #include <asm/fsl_mcdmafec.h> 55 56 #include "MCD_dma.h" 57 58 DECLARE_GLOBAL_DATA_PTR; 59 60 struct fec_info_dma fec_info[] = { 61 #ifdef CFG_FEC0_IOBASE 62 { 63 0, /* index */ 64 CFG_FEC0_IOBASE, /* io base */ 65 CFG_FEC0_PINMUX, /* gpio pin muxing */ 66 CFG_FEC0_MIIBASE, /* mii base */ 67 -1, /* phy_addr */ 68 0, /* duplex and speed */ 69 0, /* phy name */ 70 0, /* phyname init */ 71 0, /* RX BD */ 72 0, /* TX BD */ 73 0, /* rx Index */ 74 0, /* tx Index */ 75 0, /* tx buffer */ 76 0, /* initialized flag */ 77 (struct fec_info_dma *)-1, /* next */ 78 FEC0_RX_TASK, /* rxTask */ 79 FEC0_TX_TASK, /* txTask */ 80 FEC0_RX_PRIORITY, /* rxPri */ 81 FEC0_TX_PRIORITY, /* txPri */ 82 FEC0_RX_INIT, /* rxInit */ 83 FEC0_TX_INIT, /* txInit */ 84 0, /* usedTbdIndex */ 85 0, /* cleanTbdNum */ 86 }, 87 #endif 88 #ifdef CFG_FEC1_IOBASE 89 { 90 1, /* index */ 91 CFG_FEC1_IOBASE, /* io base */ 92 CFG_FEC1_PINMUX, /* gpio pin muxing */ 93 CFG_FEC1_MIIBASE, /* mii base */ 94 -1, /* phy_addr */ 95 0, /* duplex and speed */ 96 0, /* phy name */ 97 0, /* phy name init */ 98 0, /* RX BD */ 99 0, /* TX BD */ 100 0, /* rx Index */ 101 0, /* tx Index */ 102 0, /* tx buffer */ 103 0, /* initialized flag */ 104 (struct fec_info_dma *)-1, /* next */ 105 FEC1_RX_TASK, /* rxTask */ 106 FEC1_TX_TASK, /* txTask */ 107 FEC1_RX_PRIORITY, /* rxPri */ 108 FEC1_TX_PRIORITY, /* txPri */ 109 FEC1_RX_INIT, /* rxInit */ 110 FEC1_TX_INIT, /* txInit */ 111 0, /* usedTbdIndex */ 112 0, /* cleanTbdNum */ 113 } 114 #endif 115 }; 116 117 static int fec_send(struct eth_device *dev, volatile void *packet, int length); 118 static int fec_recv(struct eth_device *dev); 119 static int fec_init(struct eth_device *dev, bd_t * bd); 120 static void fec_halt(struct eth_device *dev); 121 122 #ifdef ET_DEBUG 123 static void dbg_fec_regs(struct eth_device *dev) 124 { 125 struct fec_info_dma *info = dev->priv; 126 volatile fecdma_t *fecp = (fecdma_t *) (info->iobase); 127 128 printf("=====\n"); 129 printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir); 130 printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr); 131 printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr); 132 printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr); 133 printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr); 134 printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc); 135 printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr); 136 printf("r hash %x - %x\n", (int)&fecp->rhr, fecp->rhr); 137 printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr); 138 printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr); 139 printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur); 140 printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd); 141 printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur); 142 printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr); 143 printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur); 144 printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr); 145 printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr); 146 printf("r_fdata %x - %x\n", (int)&fecp->rfdr, fecp->rfdr); 147 printf("r_fstat %x - %x\n", (int)&fecp->rfsr, fecp->rfsr); 148 printf("r_fctrl %x - %x\n", (int)&fecp->rfcr, fecp->rfcr); 149 printf("r_flrfp %x - %x\n", (int)&fecp->rlrfp, fecp->rlrfp); 150 printf("r_flwfp %x - %x\n", (int)&fecp->rlwfp, fecp->rlwfp); 151 printf("r_frfar %x - %x\n", (int)&fecp->rfar, fecp->rfar); 152 printf("r_frfrp %x - %x\n", (int)&fecp->rfrp, fecp->rfrp); 153 printf("r_frfwp %x - %x\n", (int)&fecp->rfwp, fecp->rfwp); 154 printf("t_fdata %x - %x\n", (int)&fecp->tfdr, fecp->tfdr); 155 printf("t_fstat %x - %x\n", (int)&fecp->tfsr, fecp->tfsr); 156 printf("t_fctrl %x - %x\n", (int)&fecp->tfcr, fecp->tfcr); 157 printf("t_flrfp %x - %x\n", (int)&fecp->tlrfp, fecp->tlrfp); 158 printf("t_flwfp %x - %x\n", (int)&fecp->tlwfp, fecp->tlwfp); 159 printf("t_ftfar %x - %x\n", (int)&fecp->tfar, fecp->tfar); 160 printf("t_ftfrp %x - %x\n", (int)&fecp->tfrp, fecp->tfrp); 161 printf("t_ftfwp %x - %x\n", (int)&fecp->tfwp, fecp->tfwp); 162 printf("frst %x - %x\n", (int)&fecp->frst, fecp->frst); 163 printf("ctcwr %x - %x\n", (int)&fecp->ctcwr, fecp->ctcwr); 164 } 165 #endif 166 167 static void set_fec_duplex_speed(volatile fecdma_t * fecp, bd_t * bd, int dup_spd) 168 { 169 if ((dup_spd >> 16) == FULL) { 170 /* Set maximum frame length */ 171 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE | 172 FEC_RCR_PROM | 0x100; 173 fecp->tcr = FEC_TCR_FDEN; 174 } else { 175 /* Half duplex mode */ 176 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | 177 FEC_RCR_MII_MODE | FEC_RCR_DRT; 178 fecp->tcr &= ~FEC_TCR_FDEN; 179 } 180 181 if ((dup_spd & 0xFFFF) == _100BASET) { 182 #ifdef MII_DEBUG 183 printf("100Mbps\n"); 184 #endif 185 bd->bi_ethspeed = 100; 186 } else { 187 #ifdef MII_DEBUG 188 printf("10Mbps\n"); 189 #endif 190 bd->bi_ethspeed = 10; 191 } 192 } 193 194 static int fec_send(struct eth_device *dev, volatile void *packet, int length) 195 { 196 struct fec_info_dma *info = dev->priv; 197 cbd_t *pTbd, *pUsedTbd; 198 u16 phyStatus; 199 200 miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &phyStatus); 201 202 /* process all the consumed TBDs */ 203 while (info->cleanTbdNum < CFG_TX_ETH_BUFFER) { 204 pUsedTbd = &info->txbd[info->usedTbdIdx]; 205 if (pUsedTbd->cbd_sc & BD_ENET_TX_READY) { 206 #ifdef ET_DEBUG 207 printf("Cannot clean TBD %d, in use\n", 208 info->cleanTbdNum); 209 #endif 210 return 0; 211 } 212 213 /* clean this buffer descriptor */ 214 if (info->usedTbdIdx == (CFG_TX_ETH_BUFFER - 1)) 215 pUsedTbd->cbd_sc = BD_ENET_TX_WRAP; 216 else 217 pUsedTbd->cbd_sc = 0; 218 219 /* update some indeces for a correct handling of the TBD ring */ 220 info->cleanTbdNum++; 221 info->usedTbdIdx = (info->usedTbdIdx + 1) % CFG_TX_ETH_BUFFER; 222 } 223 224 /* Check for valid length of data. */ 225 if ((length > 1500) || (length <= 0)) { 226 return -1; 227 } 228 229 /* Check the number of vacant TxBDs. */ 230 if (info->cleanTbdNum < 1) { 231 printf("No available TxBDs ...\n"); 232 return -1; 233 } 234 235 /* Get the first TxBD to send the mac header */ 236 pTbd = &info->txbd[info->txIdx]; 237 pTbd->cbd_datlen = length; 238 pTbd->cbd_bufaddr = (u32) packet; 239 pTbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY; 240 info->txIdx = (info->txIdx + 1) % CFG_TX_ETH_BUFFER; 241 242 /* Enable DMA transmit task */ 243 MCD_continDma(info->txTask); 244 245 info->cleanTbdNum -= 1; 246 247 /* wait until frame is sent . */ 248 while (pTbd->cbd_sc & BD_ENET_TX_READY) { 249 udelay(10); 250 } 251 252 return (int)(info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS); 253 } 254 255 static int fec_recv(struct eth_device *dev) 256 { 257 struct fec_info_dma *info = dev->priv; 258 volatile fecdma_t *fecp = (fecdma_t *) (info->iobase); 259 260 cbd_t *pRbd = &info->rxbd[info->rxIdx]; 261 u32 ievent; 262 int frame_length, len = 0; 263 264 /* Check if any critical events have happened */ 265 ievent = fecp->eir; 266 if (ievent != 0) { 267 fecp->eir = ievent; 268 269 if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) { 270 printf("fec_recv: error\n"); 271 fec_halt(dev); 272 fec_init(dev, NULL); 273 return 0; 274 } 275 276 if (ievent & FEC_EIR_HBERR) { 277 /* Heartbeat error */ 278 fecp->tcr |= FEC_TCR_GTS; 279 } 280 281 if (ievent & FEC_EIR_GRA) { 282 /* Graceful stop complete */ 283 if (fecp->tcr & FEC_TCR_GTS) { 284 printf("fec_recv: tcr_gts\n"); 285 fec_halt(dev); 286 fecp->tcr &= ~FEC_TCR_GTS; 287 fec_init(dev, NULL); 288 } 289 } 290 } 291 292 if (!(pRbd->cbd_sc & BD_ENET_RX_EMPTY)) { 293 if ((pRbd->cbd_sc & BD_ENET_RX_LAST) 294 && !(pRbd->cbd_sc & BD_ENET_RX_ERR) 295 && ((pRbd->cbd_datlen - 4) > 14)) { 296 297 /* Get buffer address and size */ 298 frame_length = pRbd->cbd_datlen - 4; 299 300 /* Fill the buffer and pass it to upper layers */ 301 NetReceive((volatile uchar *)pRbd->cbd_bufaddr, 302 frame_length); 303 len = frame_length; 304 } 305 306 /* Reset buffer descriptor as empty */ 307 if ((info->rxIdx) == (PKTBUFSRX - 1)) 308 pRbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); 309 else 310 pRbd->cbd_sc = BD_ENET_RX_EMPTY; 311 312 pRbd->cbd_datlen = PKTSIZE_ALIGN; 313 314 /* Now, we have an empty RxBD, restart the DMA receive task */ 315 MCD_continDma(info->rxTask); 316 317 /* Increment BD count */ 318 info->rxIdx = (info->rxIdx + 1) % PKTBUFSRX; 319 } 320 321 return len; 322 } 323 324 static void fec_set_hwaddr(volatile fecdma_t * fecp, u8 * mac) 325 { 326 u8 currByte; /* byte for which to compute the CRC */ 327 int byte; /* loop - counter */ 328 int bit; /* loop - counter */ 329 u32 crc = 0xffffffff; /* initial value */ 330 331 for (byte = 0; byte < 6; byte++) { 332 currByte = mac[byte]; 333 for (bit = 0; bit < 8; bit++) { 334 if ((currByte & 0x01) ^ (crc & 0x01)) { 335 crc >>= 1; 336 crc = crc ^ 0xedb88320; 337 } else { 338 crc >>= 1; 339 } 340 currByte >>= 1; 341 } 342 } 343 344 crc = crc >> 26; 345 346 /* Set individual hash table register */ 347 if (crc >= 32) { 348 fecp->ialr = (1 << (crc - 32)); 349 fecp->iaur = 0; 350 } else { 351 fecp->ialr = 0; 352 fecp->iaur = (1 << crc); 353 } 354 355 /* Set physical address */ 356 fecp->palr = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3]; 357 fecp->paur = (mac[4] << 24) + (mac[5] << 16) + 0x8808; 358 359 /* Clear multicast address hash table */ 360 fecp->gaur = 0; 361 fecp->galr = 0; 362 } 363 364 static int fec_init(struct eth_device *dev, bd_t * bd) 365 { 366 struct fec_info_dma *info = dev->priv; 367 volatile fecdma_t *fecp = (fecdma_t *) (info->iobase); 368 int i; 369 370 #ifdef ET_DEBUG 371 printf("fec_init: iobase 0x%08x ...\n", info->iobase); 372 #endif 373 374 fecpin_setclear(dev, 1); 375 376 fec_halt(dev); 377 378 #if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \ 379 defined (CFG_DISCOVER_PHY) 380 381 mii_init(); 382 383 set_fec_duplex_speed(fecp, bd, info->dup_spd); 384 #else 385 #ifndef CFG_DISCOVER_PHY 386 set_fec_duplex_speed(fecp, bd, (FECDUPLEX << 16) | FECSPEED); 387 #endif /* ifndef CFG_DISCOVER_PHY */ 388 #endif /* CONFIG_CMD_MII || CONFIG_MII */ 389 390 /* We use strictly polling mode only */ 391 fecp->eimr = 0; 392 393 /* Clear any pending interrupt */ 394 fecp->eir = 0xffffffff; 395 396 /* Set station address */ 397 if ((u32) fecp == CFG_FEC0_IOBASE) { 398 fec_set_hwaddr(fecp, bd->bi_enetaddr); 399 } else { 400 fec_set_hwaddr(fecp, bd->bi_enet1addr); 401 } 402 403 /* Set Opcode/Pause Duration Register */ 404 fecp->opd = 0x00010020; 405 406 /* Setup Buffers and Buffer Desriptors */ 407 info->rxIdx = 0; 408 info->txIdx = 0; 409 410 /* Setup Receiver Buffer Descriptors (13.14.24.18) 411 * Settings: Empty, Wrap */ 412 for (i = 0; i < PKTBUFSRX; i++) { 413 info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; 414 info->rxbd[i].cbd_datlen = PKTSIZE_ALIGN; 415 info->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i]; 416 } 417 info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; 418 419 /* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) 420 * Settings: Last, Tx CRC */ 421 for (i = 0; i < CFG_TX_ETH_BUFFER; i++) { 422 info->txbd[i].cbd_sc = 0; 423 info->txbd[i].cbd_datlen = 0; 424 info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]); 425 } 426 info->txbd[CFG_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP; 427 428 info->usedTbdIdx = 0; 429 info->cleanTbdNum = CFG_TX_ETH_BUFFER; 430 431 /* Set Rx FIFO alarm and granularity value */ 432 fecp->rfcr = 0x0c000000; 433 fecp->rfar = 0x0000030c; 434 435 /* Set Tx FIFO granularity value */ 436 fecp->tfcr = FIFO_CTRL_FRAME | FIFO_CTRL_GR(6) | 0x00040000; 437 fecp->tfar = 0x00000080; 438 439 fecp->tfwr = 0x2; 440 fecp->ctcwr = 0x03000000; 441 442 /* Enable DMA receive task */ 443 MCD_startDma(info->rxTask, /* Dma channel */ 444 (s8 *) info->rxbd, /*Source Address */ 445 0, /* Source increment */ 446 (s8 *) (&fecp->rfdr), /* dest */ 447 4, /* dest increment */ 448 0, /* DMA size */ 449 4, /* xfer size */ 450 info->rxInit, /* initiator */ 451 info->rxPri, /* priority */ 452 (MCD_FECRX_DMA | MCD_TT_FLAGS_DEF), /* Flags */ 453 (MCD_NO_CSUM | MCD_NO_BYTE_SWAP) /* Function description */ 454 ); 455 456 /* Enable DMA tx task with no ready buffer descriptors */ 457 MCD_startDma(info->txTask, /* Dma channel */ 458 (s8 *) info->txbd, /*Source Address */ 459 0, /* Source increment */ 460 (s8 *) (&fecp->tfdr), /* dest */ 461 4, /* dest incr */ 462 0, /* DMA size */ 463 4, /* xfer size */ 464 info->txInit, /* initiator */ 465 info->txPri, /* priority */ 466 (MCD_FECTX_DMA | MCD_TT_FLAGS_DEF), /* Flags */ 467 (MCD_NO_CSUM | MCD_NO_BYTE_SWAP) /* Function description */ 468 ); 469 470 /* Now enable the transmit and receive processing */ 471 fecp->ecr |= FEC_ECR_ETHER_EN; 472 473 return 1; 474 } 475 476 static void fec_halt(struct eth_device *dev) 477 { 478 struct fec_info_dma *info = dev->priv; 479 volatile fecdma_t *fecp = (fecdma_t *) (info->iobase); 480 int counter = 0xffff; 481 482 /* issue graceful stop command to the FEC transmitter if necessary */ 483 fecp->tcr |= FEC_TCR_GTS; 484 485 /* wait for graceful stop to register */ 486 while ((counter--) && (!(fecp->eir & FEC_EIR_GRA))) ; 487 488 /* Disable DMA tasks */ 489 MCD_killDma(info->txTask); 490 MCD_killDma(info->rxTask);; 491 492 /* Disable the Ethernet Controller */ 493 fecp->ecr &= ~FEC_ECR_ETHER_EN; 494 495 /* Clear FIFO status registers */ 496 fecp->rfsr &= FIFO_ERRSTAT; 497 fecp->tfsr &= FIFO_ERRSTAT; 498 499 fecp->frst = 0x01000000; 500 501 /* Issue a reset command to the FEC chip */ 502 fecp->ecr |= FEC_ECR_RESET; 503 504 /* wait at least 20 clock cycles */ 505 udelay(10000); 506 507 #ifdef ET_DEBUG 508 printf("Ethernet task stopped\n"); 509 #endif 510 } 511 512 int mcdmafec_initialize(bd_t * bis) 513 { 514 struct eth_device *dev; 515 int i; 516 517 for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) { 518 519 dev = 520 (struct eth_device *)memalign(CFG_CACHELINE_SIZE, 521 sizeof *dev); 522 if (dev == NULL) 523 hang(); 524 525 memset(dev, 0, sizeof(*dev)); 526 527 sprintf(dev->name, "FEC%d", fec_info[i].index); 528 529 dev->priv = &fec_info[i]; 530 dev->init = fec_init; 531 dev->halt = fec_halt; 532 dev->send = fec_send; 533 dev->recv = fec_recv; 534 535 /* setup Receive and Transmit buffer descriptor */ 536 fec_info[i].rxbd = 537 (cbd_t *) memalign(CFG_CACHELINE_SIZE, 538 (PKTBUFSRX * sizeof(cbd_t))); 539 fec_info[i].txbd = 540 (cbd_t *) memalign(CFG_CACHELINE_SIZE, 541 (CFG_TX_ETH_BUFFER * sizeof(cbd_t))); 542 fec_info[i].txbuf = 543 (char *)memalign(CFG_CACHELINE_SIZE, DBUF_LENGTH); 544 545 #ifdef ET_DEBUG 546 printf("rxbd %x txbd %x\n", 547 (int)fec_info[i].rxbd, (int)fec_info[i].txbd); 548 #endif 549 550 fec_info[i].phy_name = (char *)memalign(CFG_CACHELINE_SIZE, 32); 551 552 eth_register(dev); 553 554 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 555 miiphy_register(dev->name, 556 mcffec_miiphy_read, mcffec_miiphy_write); 557 #endif 558 559 if (i > 0) 560 fec_info[i - 1].next = &fec_info[i]; 561 } 562 fec_info[i - 1].next = &fec_info[0]; 563 564 /* default speed */ 565 bis->bi_ethspeed = 10; 566 567 return 1; 568 } 569 570 #endif /* CONFIG_CMD_NET && CONFIG_NET_MULTI */ 571 #endif /* CONFIG_FSLDMAFEC */ 572