1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2014 Freescale Semiconductor
4  */
5 
6 /* qbman_sys_decl.h and qbman_sys.h are the two platform-specific files in the
7  * driver. They are only included via qbman_private.h, which is itself a
8  * platform-independent file and is included by all the other driver source.
9  *
10  * qbman_sys_decl.h is included prior to all other declarations and logic, and
11  * it exists to provide compatibility with any linux interfaces our
12  * single-source driver code is dependent on (eg. kmalloc). Ie. this file
13  * provides linux compatibility.
14  *
15  * This qbman_sys.h header, on the other hand, is included *after* any common
16  * and platform-neutral declarations and logic in qbman_private.h, and exists to
17  * implement any platform-specific logic of the qbman driver itself. Ie. it is
18  * *not* to provide linux compatibility.
19  */
20 
21 /* Trace the 3 different classes of read/write access to QBMan. #undef as
22  * required. */
23 #undef QBMAN_CCSR_TRACE
24 #undef QBMAN_CINH_TRACE
25 #undef QBMAN_CENA_TRACE
26 
27 /* Temporarily define this to get around the fact that cache enabled mapping is
28  * not working right now. Will remove this after uboot could map the cache
29  * enabled portal memory.
30  */
31 #define QBMAN_CINH_ONLY
32 
33 static inline void word_copy(void *d, const void *s, unsigned int cnt)
34 {
35 	uint32_t *dd = d;
36 	const uint32_t *ss = s;
37 
38 	while (cnt--)
39 		*(dd++) = *(ss++);
40 }
41 
42 /* Currently, the CENA support code expects each 32-bit word to be written in
43  * host order, and these are converted to hardware (little-endian) order on
44  * command submission. However, 64-bit quantities are must be written (and read)
45  * as two 32-bit words with the least-significant word first, irrespective of
46  * host endianness. */
47 static inline void u64_to_le32_copy(void *d, const uint64_t *s,
48 					unsigned int cnt)
49 {
50 	uint32_t *dd = d;
51 	const uint32_t *ss = (const uint32_t *)s;
52 
53 	while (cnt--) {
54 		/* TBD: the toolchain was choking on the use of 64-bit types up
55 		 * until recently so this works entirely with 32-bit variables.
56 		 * When 64-bit types become usable again, investigate better
57 		 * ways of doing this. */
58 #if defined(__BIG_ENDIAN)
59 		*(dd++) = ss[1];
60 		*(dd++) = ss[0];
61 		ss += 2;
62 #else
63 		*(dd++) = *(ss++);
64 		*(dd++) = *(ss++);
65 #endif
66 	}
67 }
68 static inline void u64_from_le32_copy(uint64_t *d, const void *s,
69 					unsigned int cnt)
70 {
71 	const uint32_t *ss = s;
72 	uint32_t *dd = (uint32_t *)d;
73 
74 	while (cnt--) {
75 #if defined(__BIG_ENDIAN)
76 		dd[1] = *(ss++);
77 		dd[0] = *(ss++);
78 		dd += 2;
79 #else
80 		*(dd++) = *(ss++);
81 		*(dd++) = *(ss++);
82 #endif
83 	}
84 }
85 
86 /* Convert a host-native 32bit value into little endian */
87 #if defined(__BIG_ENDIAN)
88 static inline uint32_t make_le32(uint32_t val)
89 {
90 	return ((val & 0xff) << 24) | ((val & 0xff00) << 8) |
91 		((val & 0xff0000) >> 8) | ((val & 0xff000000) >> 24);
92 }
93 #else
94 #define make_le32(val) (val)
95 #endif
96 static inline void make_le32_n(uint32_t *val, unsigned int num)
97 {
98 	while (num--) {
99 		*val = make_le32(*val);
100 		val++;
101 	}
102 }
103 
104 	/******************/
105 	/* Portal access  */
106 	/******************/
107 struct qbman_swp_sys {
108 	/* On GPP, the sys support for qbman_swp is here. The CENA region isi
109 	 * not an mmap() of the real portal registers, but an allocated
110 	 * place-holder, because the actual writes/reads to/from the portal are
111 	 * marshalled from these allocated areas using QBMan's "MC access
112 	 * registers". CINH accesses are atomic so there's no need for a
113 	 * place-holder. */
114 	void *cena;
115 	void __iomem *addr_cena;
116 	void __iomem *addr_cinh;
117 };
118 
119 /* P_OFFSET is (ACCESS_CMD,0,12) - offset within the portal
120  * C is (ACCESS_CMD,12,1) - is inhibited? (0==CENA, 1==CINH)
121  * SWP_IDX is (ACCESS_CMD,16,10) - Software portal index
122  * P is (ACCESS_CMD,28,1) - (0==special portal, 1==any portal)
123  * T is (ACCESS_CMD,29,1) - Command type (0==READ, 1==WRITE)
124  * E is (ACCESS_CMD,31,1) - Command execute (1 to issue, poll for 0==complete)
125  */
126 
127 static inline void qbman_cinh_write(struct qbman_swp_sys *s, uint32_t offset,
128 				    uint32_t val)
129 {
130 	__raw_writel(val, s->addr_cinh + offset);
131 #ifdef QBMAN_CINH_TRACE
132 	pr_info("qbman_cinh_write(%p:0x%03x) 0x%08x\n",
133 		s->addr_cinh, offset, val);
134 #endif
135 }
136 
137 static inline uint32_t qbman_cinh_read(struct qbman_swp_sys *s, uint32_t offset)
138 {
139 	uint32_t reg = __raw_readl(s->addr_cinh + offset);
140 
141 #ifdef QBMAN_CINH_TRACE
142 	pr_info("qbman_cinh_read(%p:0x%03x) 0x%08x\n",
143 		s->addr_cinh, offset, reg);
144 #endif
145 	return reg;
146 }
147 
148 static inline void *qbman_cena_write_start(struct qbman_swp_sys *s,
149 						uint32_t offset)
150 {
151 	void *shadow = s->cena + offset;
152 
153 #ifdef QBMAN_CENA_TRACE
154 	pr_info("qbman_cena_write_start(%p:0x%03x) %p\n",
155 		s->addr_cena, offset, shadow);
156 #endif
157 	BUG_ON(offset & 63);
158 	dcbz(shadow);
159 	return shadow;
160 }
161 
162 static inline void qbman_cena_write_complete(struct qbman_swp_sys *s,
163 						uint32_t offset, void *cmd)
164 {
165 	const uint32_t *shadow = cmd;
166 	int loop;
167 
168 #ifdef QBMAN_CENA_TRACE
169 	pr_info("qbman_cena_write_complete(%p:0x%03x) %p\n",
170 		s->addr_cena, offset, shadow);
171 	hexdump(cmd, 64);
172 #endif
173 	for (loop = 15; loop >= 0; loop--)
174 #ifdef QBMAN_CINH_ONLY
175 		__raw_writel(shadow[loop], s->addr_cinh +
176 					 offset + loop * 4);
177 #else
178 		__raw_writel(shadow[loop], s->addr_cena +
179 					 offset + loop * 4);
180 #endif
181 }
182 
183 static inline void *qbman_cena_read(struct qbman_swp_sys *s, uint32_t offset)
184 {
185 	uint32_t *shadow = s->cena + offset;
186 	unsigned int loop;
187 
188 #ifdef QBMAN_CENA_TRACE
189 	pr_info("qbman_cena_read(%p:0x%03x) %p\n",
190 		s->addr_cena, offset, shadow);
191 #endif
192 
193 	for (loop = 0; loop < 16; loop++)
194 #ifdef QBMAN_CINH_ONLY
195 		shadow[loop] = __raw_readl(s->addr_cinh + offset
196 					+ loop * 4);
197 #else
198 		shadow[loop] = __raw_readl(s->addr_cena + offset
199 					+ loop * 4);
200 #endif
201 #ifdef QBMAN_CENA_TRACE
202 	hexdump(shadow, 64);
203 #endif
204 	return shadow;
205 }
206 
207 static inline void qbman_cena_invalidate_prefetch(struct qbman_swp_sys *s,
208 						  uint32_t offset)
209 {
210 }
211 
212 	/******************/
213 	/* Portal support */
214 	/******************/
215 
216 /* The SWP_CFG portal register is special, in that it is used by the
217  * platform-specific code rather than the platform-independent code in
218  * qbman_portal.c. So use of it is declared locally here. */
219 #define QBMAN_CINH_SWP_CFG   0xd00
220 
221 /* For MC portal use, we always configure with
222  * DQRR_MF is (SWP_CFG,20,3) - DQRR max fill (<- 0x4)
223  * EST is (SWP_CFG,16,3) - EQCR_CI stashing threshold (<- 0x0)
224  * RPM is (SWP_CFG,12,2) - RCR production notification mode (<- 0x3)
225  * DCM is (SWP_CFG,10,2) - DQRR consumption notification mode (<- 0x2)
226  * EPM is (SWP_CFG,8,2) - EQCR production notification mode (<- 0x3)
227  * SD is (SWP_CFG,5,1) - memory stashing drop enable (<- FALSE)
228  * SP is (SWP_CFG,4,1) - memory stashing priority (<- TRUE)
229  * SE is (SWP_CFG,3,1) - memory stashing enable (<- 0x0)
230  * DP is (SWP_CFG,2,1) - dequeue stashing priority (<- TRUE)
231  * DE is (SWP_CFG,1,1) - dequeue stashing enable (<- 0x0)
232  * EP is (SWP_CFG,0,1) - EQCR_CI stashing priority (<- FALSE)
233  */
234 static inline uint32_t qbman_set_swp_cfg(uint8_t max_fill, uint8_t wn,
235 					uint8_t est, uint8_t rpm, uint8_t dcm,
236 					uint8_t epm, int sd, int sp, int se,
237 					int dp, int de, int ep)
238 {
239 	uint32_t reg;
240 
241 	reg = e32_uint8_t(20, (uint32_t)(3 + (max_fill >> 3)), max_fill) |
242 		e32_uint8_t(16, 3, est) | e32_uint8_t(12, 2, rpm) |
243 		e32_uint8_t(10, 2, dcm) | e32_uint8_t(8, 2, epm) |
244 		e32_int(5, 1, sd) | e32_int(4, 1, sp) | e32_int(3, 1, se) |
245 		e32_int(2, 1, dp) | e32_int(1, 1, de) | e32_int(0, 1, ep) |
246 		e32_uint8_t(14, 1, wn);
247 	return reg;
248 }
249 
250 static inline int qbman_swp_sys_init(struct qbman_swp_sys *s,
251 				     const struct qbman_swp_desc *d,
252 				     uint8_t dqrr_size)
253 {
254 	uint32_t reg;
255 
256 	s->addr_cena = d->cena_bar;
257 	s->addr_cinh = d->cinh_bar;
258 	s->cena = (void *)valloc(CONFIG_SYS_PAGE_SIZE);
259 	if (!s->cena) {
260 		printf("Could not allocate page for cena shadow\n");
261 		return -1;
262 	}
263 	memset((void *)s->cena, 0x00, CONFIG_SYS_PAGE_SIZE);
264 
265 #ifdef QBMAN_CHECKING
266 	/* We should never be asked to initialise for a portal that isn't in
267 	 * the power-on state. (Ie. don't forget to reset portals when they are
268 	 * decommissioned!)
269 	 */
270 	reg = qbman_cinh_read(s, QBMAN_CINH_SWP_CFG);
271 	BUG_ON(reg);
272 #endif
273 #ifdef QBMAN_CINH_ONLY
274 	reg = qbman_set_swp_cfg(dqrr_size, 1, 0, 3, 2, 3, 0, 1, 0, 1, 0, 0);
275 #else
276 	reg = qbman_set_swp_cfg(dqrr_size, 0, 0, 3, 2, 3, 0, 1, 0, 1, 0, 0);
277 #endif
278 	qbman_cinh_write(s, QBMAN_CINH_SWP_CFG, reg);
279 	reg = qbman_cinh_read(s, QBMAN_CINH_SWP_CFG);
280 	if (!reg) {
281 		printf("The portal is not enabled!\n");
282 		free(s->cena);
283 		return -1;
284 	}
285 	return 0;
286 }
287 
288 static inline void qbman_swp_sys_finish(struct qbman_swp_sys *s)
289 {
290 	free((void *)s->cena);
291 }
292