1c916d7c9SKumar Gala /* 2c916d7c9SKumar Gala * Copyright 2009-2011 Freescale Semiconductor, Inc. 3b21f87a3SAndy Fleming * Andy Fleming <afleming@gmail.com> 4c916d7c9SKumar Gala * 51a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6c916d7c9SKumar Gala * Some part is taken from tsec.c 7c916d7c9SKumar Gala */ 8c916d7c9SKumar Gala #include <common.h> 9c916d7c9SKumar Gala #include <miiphy.h> 10c916d7c9SKumar Gala #include <phy.h> 11c916d7c9SKumar Gala #include <asm/io.h> 128225b2fdSShaohui Xie #include <fsl_tgec.h> 13c916d7c9SKumar Gala #include <fm_eth.h> 14c916d7c9SKumar Gala 15c916d7c9SKumar Gala /* 16c916d7c9SKumar Gala * Write value to the PHY for this device to the register at regnum, waiting 17c916d7c9SKumar Gala * until the write is done before it returns. All PHY configuration has to be 18c916d7c9SKumar Gala * done through the TSEC1 MIIM regs 19c916d7c9SKumar Gala */ 20960d70c6SKim Phillips static int tgec_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, 21c916d7c9SKumar Gala int regnum, u16 value) 22c916d7c9SKumar Gala { 23c916d7c9SKumar Gala u32 mdio_ctl; 24c916d7c9SKumar Gala u32 stat_val; 25c916d7c9SKumar Gala struct tgec_mdio_controller *regs = bus->priv; 26c916d7c9SKumar Gala 27c916d7c9SKumar Gala if (dev_addr == MDIO_DEVAD_NONE) 28c916d7c9SKumar Gala return 0; 29c916d7c9SKumar Gala 30c916d7c9SKumar Gala /* Wait till the bus is free */ 31c916d7c9SKumar Gala stat_val = MDIO_STAT_CLKDIV(100); 32c916d7c9SKumar Gala out_be32(®s->mdio_stat, stat_val); 33c916d7c9SKumar Gala while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY) 34c916d7c9SKumar Gala ; 35c916d7c9SKumar Gala 36c916d7c9SKumar Gala /* Set the port and dev addr */ 37c916d7c9SKumar Gala mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr); 38c916d7c9SKumar Gala out_be32(®s->mdio_ctl, mdio_ctl); 39c916d7c9SKumar Gala 40c916d7c9SKumar Gala /* Set the register address */ 41c916d7c9SKumar Gala out_be32(®s->mdio_addr, regnum & 0xffff); 42c916d7c9SKumar Gala 43c916d7c9SKumar Gala /* Wait till the bus is free */ 44c916d7c9SKumar Gala while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY) 45c916d7c9SKumar Gala ; 46c916d7c9SKumar Gala 47c916d7c9SKumar Gala /* Write the value to the register */ 48c916d7c9SKumar Gala out_be32(®s->mdio_data, MDIO_DATA(value)); 49c916d7c9SKumar Gala 50c916d7c9SKumar Gala /* Wait till the MDIO write is complete */ 51c916d7c9SKumar Gala while ((in_be32(®s->mdio_data)) & MDIO_DATA_BSY) 52c916d7c9SKumar Gala ; 53c916d7c9SKumar Gala 54c916d7c9SKumar Gala return 0; 55c916d7c9SKumar Gala } 56c916d7c9SKumar Gala 57c916d7c9SKumar Gala /* 58c916d7c9SKumar Gala * Reads from register regnum in the PHY for device dev, returning the value. 59c916d7c9SKumar Gala * Clears miimcom first. All PHY configuration has to be done through the 60c916d7c9SKumar Gala * TSEC1 MIIM regs 61c916d7c9SKumar Gala */ 62960d70c6SKim Phillips static int tgec_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, 63c916d7c9SKumar Gala int regnum) 64c916d7c9SKumar Gala { 65c916d7c9SKumar Gala u32 mdio_ctl; 66c916d7c9SKumar Gala u32 stat_val; 67c916d7c9SKumar Gala struct tgec_mdio_controller *regs = bus->priv; 68c916d7c9SKumar Gala 69c916d7c9SKumar Gala if (dev_addr == MDIO_DEVAD_NONE) 70c916d7c9SKumar Gala return 0xffff; 71c916d7c9SKumar Gala 72c916d7c9SKumar Gala stat_val = MDIO_STAT_CLKDIV(100); 73c916d7c9SKumar Gala out_be32(®s->mdio_stat, stat_val); 74c916d7c9SKumar Gala /* Wait till the bus is free */ 75c916d7c9SKumar Gala while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY) 76c916d7c9SKumar Gala ; 77c916d7c9SKumar Gala 78c916d7c9SKumar Gala /* Set the Port and Device Addrs */ 79c916d7c9SKumar Gala mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr); 80c916d7c9SKumar Gala out_be32(®s->mdio_ctl, mdio_ctl); 81c916d7c9SKumar Gala 82c916d7c9SKumar Gala /* Set the register address */ 83c916d7c9SKumar Gala out_be32(®s->mdio_addr, regnum & 0xffff); 84c916d7c9SKumar Gala 85c916d7c9SKumar Gala /* Wait till the bus is free */ 86c916d7c9SKumar Gala while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY) 87c916d7c9SKumar Gala ; 88c916d7c9SKumar Gala 89c916d7c9SKumar Gala /* Initiate the read */ 90c916d7c9SKumar Gala mdio_ctl |= MDIO_CTL_READ; 91c916d7c9SKumar Gala out_be32(®s->mdio_ctl, mdio_ctl); 92c916d7c9SKumar Gala 93c916d7c9SKumar Gala /* Wait till the MDIO write is complete */ 94c916d7c9SKumar Gala while ((in_be32(®s->mdio_data)) & MDIO_DATA_BSY) 95c916d7c9SKumar Gala ; 96c916d7c9SKumar Gala 97c916d7c9SKumar Gala /* Return all Fs if nothing was there */ 98c916d7c9SKumar Gala if (in_be32(®s->mdio_stat) & MDIO_STAT_RD_ER) 99c916d7c9SKumar Gala return 0xffff; 100c916d7c9SKumar Gala 101c916d7c9SKumar Gala return in_be32(®s->mdio_data) & 0xffff; 102c916d7c9SKumar Gala } 103c916d7c9SKumar Gala 104960d70c6SKim Phillips static int tgec_mdio_reset(struct mii_dev *bus) 105c916d7c9SKumar Gala { 106c916d7c9SKumar Gala return 0; 107c916d7c9SKumar Gala } 108c916d7c9SKumar Gala 109c916d7c9SKumar Gala int fm_tgec_mdio_init(bd_t *bis, struct tgec_mdio_info *info) 110c916d7c9SKumar Gala { 111c916d7c9SKumar Gala struct mii_dev *bus = mdio_alloc(); 112c916d7c9SKumar Gala 113c916d7c9SKumar Gala if (!bus) { 114c916d7c9SKumar Gala printf("Failed to allocate FM TGEC MDIO bus\n"); 115c916d7c9SKumar Gala return -1; 116c916d7c9SKumar Gala } 117c916d7c9SKumar Gala 118c916d7c9SKumar Gala bus->read = tgec_mdio_read; 119c916d7c9SKumar Gala bus->write = tgec_mdio_write; 120c916d7c9SKumar Gala bus->reset = tgec_mdio_reset; 121*192bc694SBen Whitten strcpy(bus->name, info->name); 122c916d7c9SKumar Gala 123c916d7c9SKumar Gala bus->priv = info->regs; 124c916d7c9SKumar Gala 125c916d7c9SKumar Gala return mdio_register(bus); 126c916d7c9SKumar Gala } 127