1 /* 2 * Copyright 2012 Freescale Semiconductor, Inc. 3 * Roy Zang <tie-fei.zang@freescale.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 #include <common.h> 8 #include <phy.h> 9 #include <fm_eth.h> 10 #include <asm/io.h> 11 #include <asm/immap_85xx.h> 12 #include <asm/fsl_serdes.h> 13 14 u32 port_to_devdisr[] = { 15 [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, 16 [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, 17 [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, 18 [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, 19 [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5, 20 [FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6, 21 [FM1_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC1_9, 22 [FM1_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC1_10, 23 [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1, 24 [FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2, 25 [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1, 26 [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2, 27 [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3, 28 [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4, 29 [FM2_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC2_5, 30 [FM2_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC2_6, 31 [FM2_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC2_9, 32 [FM2_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC2_10, 33 [FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2_1, 34 [FM2_10GEC2] = FSL_CORENET_DEVDISR2_10GEC2_2, 35 }; 36 37 static int is_device_disabled(enum fm_port port) 38 { 39 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 40 u32 devdisr2 = in_be32(&gur->devdisr2); 41 42 return port_to_devdisr[port] & devdisr2; 43 } 44 45 void fman_disable_port(enum fm_port port) 46 { 47 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 48 49 setbits_be32(&gur->devdisr2, port_to_devdisr[port]); 50 } 51 52 void fman_enable_port(enum fm_port port) 53 { 54 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 55 56 clrbits_be32(&gur->devdisr2, port_to_devdisr[port]); 57 } 58 59 phy_interface_t fman_port_enet_if(enum fm_port port) 60 { 61 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 62 u32 rcwsr13 = in_be32(&gur->rcwsr[13]); 63 64 if (is_device_disabled(port)) 65 return PHY_INTERFACE_MODE_NONE; 66 67 if ((port == FM1_10GEC1 || port == FM1_10GEC2) && 68 ((is_serdes_configured(XAUI_FM1_MAC9)) || 69 (is_serdes_configured(XAUI_FM1_MAC10)) || 70 (is_serdes_configured(XFI_FM1_MAC9)) || 71 (is_serdes_configured(XFI_FM1_MAC10)))) 72 return PHY_INTERFACE_MODE_XGMII; 73 74 if ((port == FM1_DTSEC9 || port == FM1_DTSEC10) && 75 ((is_serdes_configured(XFI_FM1_MAC9)) || 76 (is_serdes_configured(XFI_FM1_MAC10)))) 77 return PHY_INTERFACE_MODE_NONE; 78 79 if ((port == FM2_10GEC1 || port == FM2_10GEC2) && 80 ((is_serdes_configured(XAUI_FM2_MAC9)) || 81 (is_serdes_configured(XAUI_FM2_MAC10)) || 82 (is_serdes_configured(XFI_FM2_MAC9)) || 83 (is_serdes_configured(XFI_FM2_MAC10)))) 84 return PHY_INTERFACE_MODE_XGMII; 85 86 #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ 87 #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000 88 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000 89 #define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */ 90 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000 91 #define FSL_CORENET_RCWSR13_EC2_FM2_DTSEC6_RGMII 0x08000000 92 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000 93 /* handle RGMII first */ 94 if ((port == FM2_DTSEC5) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == 95 FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII)) 96 return PHY_INTERFACE_MODE_RGMII; 97 98 if ((port == FM1_DTSEC5) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == 99 FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII)) 100 return PHY_INTERFACE_MODE_RGMII; 101 102 if ((port == FM2_DTSEC6) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == 103 FSL_CORENET_RCWSR13_EC2_FM2_DTSEC6_RGMII)) 104 return PHY_INTERFACE_MODE_RGMII; 105 switch (port) { 106 case FM1_DTSEC1: 107 case FM1_DTSEC2: 108 case FM1_DTSEC3: 109 case FM1_DTSEC4: 110 case FM1_DTSEC5: 111 case FM1_DTSEC6: 112 case FM1_DTSEC9: 113 case FM1_DTSEC10: 114 if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) 115 return PHY_INTERFACE_MODE_SGMII; 116 break; 117 case FM2_DTSEC1: 118 case FM2_DTSEC2: 119 case FM2_DTSEC3: 120 case FM2_DTSEC4: 121 case FM2_DTSEC5: 122 case FM2_DTSEC6: 123 case FM2_DTSEC9: 124 case FM2_DTSEC10: 125 if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1)) 126 return PHY_INTERFACE_MODE_SGMII; 127 break; 128 default: 129 break; 130 } 131 132 /* handle QSGMII */ 133 switch (port) { 134 case FM1_DTSEC1: 135 case FM1_DTSEC2: 136 case FM1_DTSEC3: 137 case FM1_DTSEC4: 138 /* check lane G on SerDes1 */ 139 if (is_serdes_configured(QSGMII_FM1_A)) 140 return PHY_INTERFACE_MODE_QSGMII; 141 break; 142 case FM1_DTSEC5: 143 case FM1_DTSEC6: 144 case FM1_DTSEC9: 145 case FM1_DTSEC10: 146 /* check lane C on SerDes1 */ 147 if (is_serdes_configured(QSGMII_FM1_B)) 148 return PHY_INTERFACE_MODE_QSGMII; 149 break; 150 case FM2_DTSEC1: 151 case FM2_DTSEC2: 152 case FM2_DTSEC3: 153 case FM2_DTSEC4: 154 /* check lane G on SerDes2 */ 155 if (is_serdes_configured(QSGMII_FM2_A)) 156 return PHY_INTERFACE_MODE_QSGMII; 157 break; 158 case FM2_DTSEC5: 159 case FM2_DTSEC6: 160 case FM2_DTSEC9: 161 case FM2_DTSEC10: 162 /* check lane C on SerDes2 */ 163 if (is_serdes_configured(QSGMII_FM2_B)) 164 return PHY_INTERFACE_MODE_QSGMII; 165 break; 166 default: 167 break; 168 } 169 170 return PHY_INTERFACE_MODE_NONE; 171 } 172