1 /* 2 * Copyright 2012 Freescale Semiconductor, Inc. 3 * Roy Zang <tie-fei.zang@freescale.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 #include <common.h> 8 #include <phy.h> 9 #include <fm_eth.h> 10 #include <asm/io.h> 11 #include <asm/immap_85xx.h> 12 #include <asm/fsl_serdes.h> 13 14 u32 port_to_devdisr[] = { 15 [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, 16 [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, 17 [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, 18 [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, 19 [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5, 20 [FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6, 21 [FM1_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC1_9, 22 [FM1_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC1_10, 23 [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1, 24 [FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2, 25 [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1, 26 [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2, 27 [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3, 28 [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4, 29 [FM2_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC2_5, 30 [FM2_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC2_6, 31 [FM2_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC2_9, 32 [FM2_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC2_10, 33 [FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2_1, 34 [FM2_10GEC2] = FSL_CORENET_DEVDISR2_10GEC2_2, 35 }; 36 37 static int is_device_disabled(enum fm_port port) 38 { 39 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 40 u32 devdisr2 = in_be32(&gur->devdisr2); 41 42 return port_to_devdisr[port] & devdisr2; 43 } 44 45 void fman_disable_port(enum fm_port port) 46 { 47 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 48 49 setbits_be32(&gur->devdisr2, port_to_devdisr[port]); 50 } 51 52 void fman_enable_port(enum fm_port port) 53 { 54 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 55 56 clrbits_be32(&gur->devdisr2, port_to_devdisr[port]); 57 } 58 59 phy_interface_t fman_port_enet_if(enum fm_port port) 60 { 61 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 62 u32 rcwsr13 = in_be32(&gur->rcwsr[13]); 63 64 if (is_device_disabled(port)) 65 return PHY_INTERFACE_MODE_NONE; 66 67 if ((port == FM1_10GEC1 || port == FM1_10GEC2) && 68 ((is_serdes_configured(XAUI_FM1_MAC9)) || 69 (is_serdes_configured(XAUI_FM1_MAC10)) || 70 (is_serdes_configured(XFI_FM1_MAC9)) || 71 (is_serdes_configured(XFI_FM1_MAC10)))) 72 return PHY_INTERFACE_MODE_XGMII; 73 74 if ((port == FM2_10GEC1 || port == FM2_10GEC2) && 75 ((is_serdes_configured(XAUI_FM2_MAC9)) || 76 (is_serdes_configured(XAUI_FM2_MAC10)) || 77 (is_serdes_configured(XFI_FM2_MAC9)) || 78 (is_serdes_configured(XFI_FM2_MAC10)))) 79 return PHY_INTERFACE_MODE_XGMII; 80 81 #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ 82 #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000 83 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000 84 #define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */ 85 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000 86 #define FSL_CORENET_RCWSR13_EC2_FM2_DTSEC6_RGMII 0x08000000 87 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000 88 /* handle RGMII first */ 89 if ((port == FM2_DTSEC5) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == 90 FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII)) 91 return PHY_INTERFACE_MODE_RGMII; 92 93 if ((port == FM1_DTSEC5) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == 94 FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII)) 95 return PHY_INTERFACE_MODE_RGMII; 96 97 if ((port == FM2_DTSEC6) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == 98 FSL_CORENET_RCWSR13_EC2_FM2_DTSEC6_RGMII)) 99 return PHY_INTERFACE_MODE_RGMII; 100 switch (port) { 101 case FM1_DTSEC1: 102 case FM1_DTSEC2: 103 case FM1_DTSEC3: 104 case FM1_DTSEC4: 105 case FM1_DTSEC5: 106 case FM1_DTSEC6: 107 case FM1_DTSEC9: 108 case FM1_DTSEC10: 109 if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) 110 return PHY_INTERFACE_MODE_SGMII; 111 break; 112 case FM2_DTSEC1: 113 case FM2_DTSEC2: 114 case FM2_DTSEC3: 115 case FM2_DTSEC4: 116 case FM2_DTSEC5: 117 case FM2_DTSEC6: 118 case FM2_DTSEC9: 119 case FM2_DTSEC10: 120 if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1)) 121 return PHY_INTERFACE_MODE_SGMII; 122 break; 123 default: 124 break; 125 } 126 127 /* handle QSGMII */ 128 switch (port) { 129 case FM1_DTSEC1: 130 case FM1_DTSEC2: 131 case FM1_DTSEC3: 132 case FM1_DTSEC4: 133 /* check lane G on SerDes1 */ 134 if (is_serdes_configured(QSGMII_FM1_A)) 135 return PHY_INTERFACE_MODE_QSGMII; 136 break; 137 case FM1_DTSEC5: 138 case FM1_DTSEC6: 139 case FM1_DTSEC9: 140 case FM1_DTSEC10: 141 /* check lane C on SerDes1 */ 142 if (is_serdes_configured(QSGMII_FM1_B)) 143 return PHY_INTERFACE_MODE_QSGMII; 144 break; 145 case FM2_DTSEC1: 146 case FM2_DTSEC2: 147 case FM2_DTSEC3: 148 case FM2_DTSEC4: 149 /* check lane G on SerDes2 */ 150 if (is_serdes_configured(QSGMII_FM2_A)) 151 return PHY_INTERFACE_MODE_QSGMII; 152 break; 153 case FM2_DTSEC5: 154 case FM2_DTSEC6: 155 case FM2_DTSEC9: 156 case FM2_DTSEC10: 157 /* check lane C on SerDes2 */ 158 if (is_serdes_configured(QSGMII_FM2_B)) 159 return PHY_INTERFACE_MODE_QSGMII; 160 break; 161 default: 162 break; 163 } 164 165 return PHY_INTERFACE_MODE_NONE; 166 } 167