xref: /openbmc/u-boot/drivers/net/fm/t4240.c (revision 054dfd9b)
1 /*
2  * Copyright 2012 Freescale Semiconductor, Inc.
3  *	Roy Zang <tie-fei.zang@freescale.com>
4  *
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public License as
7  * published by the Free Software Foundation; either version 2 of
8  * the License, or (at your option) any later version.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18  * MA 02111-1307 USA
19  */
20 #include <common.h>
21 #include <phy.h>
22 #include <fm_eth.h>
23 #include <asm/io.h>
24 #include <asm/immap_85xx.h>
25 #include <asm/fsl_serdes.h>
26 
27 u32 port_to_devdisr[] = {
28 	[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
29 	[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
30 	[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
31 	[FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
32 	[FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
33 	[FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6,
34 	[FM1_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC1_9,
35 	[FM1_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC1_10,
36 	[FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1,
37 	[FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2,
38 	[FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1,
39 	[FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2,
40 	[FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3,
41 	[FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4,
42 	[FM2_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC2_5,
43 	[FM2_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC2_6,
44 	[FM2_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC2_9,
45 	[FM2_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC2_10,
46 	[FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2_1,
47 	[FM2_10GEC2] = FSL_CORENET_DEVDISR2_10GEC2_2,
48 };
49 
50 static int is_device_disabled(enum fm_port port)
51 {
52 	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
53 	u32 devdisr2 = in_be32(&gur->devdisr2);
54 
55 	return port_to_devdisr[port] & devdisr2;
56 }
57 
58 void fman_disable_port(enum fm_port port)
59 {
60 	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
61 
62 	setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
63 }
64 
65 phy_interface_t fman_port_enet_if(enum fm_port port)
66 {
67 	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
68 	u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
69 
70 	if (is_device_disabled(port))
71 		return PHY_INTERFACE_MODE_NONE;
72 
73 	if ((port == FM1_10GEC1 || port == FM1_10GEC2) &&
74 	    ((is_serdes_configured(XAUI_FM1_MAC9))	||
75 	     (is_serdes_configured(XAUI_FM1_MAC10))	||
76 	     (is_serdes_configured(XFI_FM1_MAC9))	||
77 	     (is_serdes_configured(XFI_FM1_MAC10))))
78 		return PHY_INTERFACE_MODE_XGMII;
79 
80 	if ((port == FM2_10GEC1 || port == FM2_10GEC2) &&
81 	    ((is_serdes_configured(XAUI_FM2_MAC9))	||
82 	     (is_serdes_configured(XAUI_FM2_MAC10))	||
83 	     (is_serdes_configured(XFI_FM2_MAC9))	||
84 	     (is_serdes_configured(XFI_FM2_MAC10))))
85 		return PHY_INTERFACE_MODE_XGMII;
86 
87 #define FSL_CORENET_RCWSR13_EC1			0x60000000 /* bits 417..418 */
88 #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII	0x00000000
89 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO		0x40000000
90 #define FSL_CORENET_RCWSR13_EC2			0x18000000 /* bits 419..420 */
91 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII	0x00000000
92 #define FSL_CORENET_RCWSR13_EC2_FM2_DTSEC6_RGMII	0x08000000
93 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO		0x10000000
94 	/* handle RGMII first */
95 	if ((port == FM2_DTSEC5) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
96 		FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII))
97 		return PHY_INTERFACE_MODE_RGMII;
98 
99 	if ((port == FM1_DTSEC5) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
100 		FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII))
101 		return PHY_INTERFACE_MODE_RGMII;
102 
103 	if ((port == FM2_DTSEC6) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
104 		FSL_CORENET_RCWSR13_EC2_FM2_DTSEC6_RGMII))
105 		return PHY_INTERFACE_MODE_RGMII;
106 	switch (port) {
107 	case FM1_DTSEC1:
108 	case FM1_DTSEC2:
109 	case FM1_DTSEC3:
110 	case FM1_DTSEC4:
111 	case FM1_DTSEC5:
112 	case FM1_DTSEC6:
113 	case FM1_DTSEC9:
114 	case FM1_DTSEC10:
115 		if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
116 			return PHY_INTERFACE_MODE_SGMII;
117 		break;
118 	case FM2_DTSEC1:
119 	case FM2_DTSEC2:
120 	case FM2_DTSEC3:
121 	case FM2_DTSEC4:
122 	case FM2_DTSEC5:
123 	case FM2_DTSEC6:
124 	case FM2_DTSEC9:
125 	case FM2_DTSEC10:
126 		if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1))
127 			return PHY_INTERFACE_MODE_SGMII;
128 		break;
129 	default:
130 		return PHY_INTERFACE_MODE_NONE;
131 	}
132 
133 	return PHY_INTERFACE_MODE_NONE;
134 }
135