1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2012 Freescale Semiconductor, Inc. 4 * 5 * Shengzhou Liu <Shengzhou.Liu@freescale.com> 6 */ 7 8 #include <common.h> 9 #include <phy.h> 10 #include <fm_eth.h> 11 #include <asm/immap_85xx.h> 12 #include <asm/fsl_serdes.h> 13 14 u32 port_to_devdisr[] = { 15 [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, 16 [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, 17 [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, 18 [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, 19 [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5, 20 [FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6, 21 [FM1_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC1_9, 22 [FM1_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC1_10, 23 [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1, 24 [FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2, 25 [FM1_10GEC3] = FSL_CORENET_DEVDISR2_10GEC1_3, 26 [FM1_10GEC4] = FSL_CORENET_DEVDISR2_10GEC1_4, 27 }; 28 29 static int is_device_disabled(enum fm_port port) 30 { 31 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 32 u32 devdisr2 = in_be32(&gur->devdisr2); 33 34 return port_to_devdisr[port] & devdisr2; 35 } 36 37 void fman_disable_port(enum fm_port port) 38 { 39 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 40 41 setbits_be32(&gur->devdisr2, port_to_devdisr[port]); 42 } 43 44 phy_interface_t fman_port_enet_if(enum fm_port port) 45 { 46 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 47 u32 rcwsr13 = in_be32(&gur->rcwsr[13]); 48 49 if (is_device_disabled(port)) 50 return PHY_INTERFACE_MODE_NONE; 51 52 if ((port == FM1_10GEC1 || port == FM1_10GEC2) && 53 ((is_serdes_configured(XAUI_FM1_MAC9)) || 54 (is_serdes_configured(XFI_FM1_MAC9)) || 55 (is_serdes_configured(XFI_FM1_MAC10)))) 56 return PHY_INTERFACE_MODE_XGMII; 57 58 if ((port == FM1_10GEC3 || port == FM1_10GEC4) && 59 ((is_serdes_configured(XFI_FM1_MAC1)) || 60 (is_serdes_configured(XFI_FM1_MAC2)))) 61 return PHY_INTERFACE_MODE_XGMII; 62 63 if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == 64 FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII)) 65 return PHY_INTERFACE_MODE_RGMII; 66 67 if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == 68 FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII)) 69 return PHY_INTERFACE_MODE_RGMII; 70 71 if ((port == FM1_DTSEC10) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == 72 FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII)) 73 return PHY_INTERFACE_MODE_RGMII; 74 75 switch (port) { 76 case FM1_DTSEC1: 77 case FM1_DTSEC2: 78 case FM1_DTSEC3: 79 case FM1_DTSEC4: 80 case FM1_DTSEC5: 81 case FM1_DTSEC6: 82 case FM1_DTSEC9: 83 case FM1_DTSEC10: 84 if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) 85 return PHY_INTERFACE_MODE_SGMII; 86 break; 87 default: 88 return PHY_INTERFACE_MODE_NONE; 89 } 90 91 return PHY_INTERFACE_MODE_NONE; 92 } 93