1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <phy.h> 8 #include <fm_eth.h> 9 #include <asm/io.h> 10 #include <asm/immap_85xx.h> 11 #include <asm/fsl_serdes.h> 12 13 u32 port_to_devdisr[] = { 14 [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, 15 [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, 16 [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, 17 [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, 18 [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5, 19 [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1, 20 [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1, 21 [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2, 22 [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3, 23 [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4, 24 [FM2_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC2_5, 25 [FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2, 26 }; 27 28 static int is_device_disabled(enum fm_port port) 29 { 30 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 31 u32 devdisr2 = in_be32(&gur->devdisr2); 32 33 return port_to_devdisr[port] & devdisr2; 34 } 35 36 void fman_disable_port(enum fm_port port) 37 { 38 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 39 40 /* don't allow disabling of DTSEC1 as its needed for MDIO */ 41 if (port == FM1_DTSEC1) 42 return; 43 44 setbits_be32(&gur->devdisr2, port_to_devdisr[port]); 45 } 46 47 void fman_enable_port(enum fm_port port) 48 { 49 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 50 51 clrbits_be32(&gur->devdisr2, port_to_devdisr[port]); 52 } 53 54 phy_interface_t fman_port_enet_if(enum fm_port port) 55 { 56 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 57 u32 rcwsr11 = in_be32(&gur->rcwsr[11]); 58 59 if (is_device_disabled(port)) 60 return PHY_INTERFACE_MODE_NONE; 61 62 if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1))) 63 return PHY_INTERFACE_MODE_XGMII; 64 65 if ((port == FM2_10GEC1) && (is_serdes_configured(XAUI_FM2))) 66 return PHY_INTERFACE_MODE_XGMII; 67 68 /* handle RGMII first */ 69 if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) == 70 FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII)) 71 return PHY_INTERFACE_MODE_RGMII; 72 73 if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) == 74 FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII)) 75 return PHY_INTERFACE_MODE_MII; 76 77 if ((port == FM2_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == 78 FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII)) 79 return PHY_INTERFACE_MODE_RGMII; 80 81 if ((port == FM2_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == 82 FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII)) 83 return PHY_INTERFACE_MODE_MII; 84 85 switch (port) { 86 case FM1_DTSEC1: 87 case FM1_DTSEC2: 88 case FM1_DTSEC3: 89 case FM1_DTSEC4: 90 case FM1_DTSEC5: 91 if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) 92 return PHY_INTERFACE_MODE_SGMII; 93 break; 94 case FM2_DTSEC1: 95 case FM2_DTSEC2: 96 case FM2_DTSEC3: 97 case FM2_DTSEC4: 98 case FM2_DTSEC5: 99 if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1)) 100 return PHY_INTERFACE_MODE_SGMII; 101 break; 102 default: 103 return PHY_INTERFACE_MODE_NONE; 104 } 105 106 return PHY_INTERFACE_MODE_NONE; 107 } 108