1d31e53b4STimur Tabi /* 2d31e53b4STimur Tabi * Copyright 2011 Freescale Semiconductor, Inc. 3d31e53b4STimur Tabi * 41a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 5d31e53b4STimur Tabi */ 6d31e53b4STimur Tabi #include <common.h> 7d31e53b4STimur Tabi #include <phy.h> 8d31e53b4STimur Tabi #include <fm_eth.h> 9d31e53b4STimur Tabi #include <asm/io.h> 10d31e53b4STimur Tabi #include <asm/immap_85xx.h> 11d31e53b4STimur Tabi #include <asm/fsl_serdes.h> 12d31e53b4STimur Tabi 13d31e53b4STimur Tabi u32 port_to_devdisr[] = { 14d31e53b4STimur Tabi [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, 15d31e53b4STimur Tabi [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, 16d31e53b4STimur Tabi [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, 17d31e53b4STimur Tabi [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, 18d31e53b4STimur Tabi [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5, 19d31e53b4STimur Tabi [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1, 20d31e53b4STimur Tabi [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1, 21d31e53b4STimur Tabi [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2, 22d31e53b4STimur Tabi [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3, 23d31e53b4STimur Tabi [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4, 24d31e53b4STimur Tabi [FM2_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC2_5, 25d31e53b4STimur Tabi [FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2, 26d31e53b4STimur Tabi }; 27d31e53b4STimur Tabi 28d31e53b4STimur Tabi static int is_device_disabled(enum fm_port port) 29d31e53b4STimur Tabi { 30d31e53b4STimur Tabi ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 31d31e53b4STimur Tabi u32 devdisr2 = in_be32(&gur->devdisr2); 32d31e53b4STimur Tabi 33d31e53b4STimur Tabi return port_to_devdisr[port] & devdisr2; 34d31e53b4STimur Tabi } 35d31e53b4STimur Tabi 36d31e53b4STimur Tabi void fman_disable_port(enum fm_port port) 37d31e53b4STimur Tabi { 38d31e53b4STimur Tabi ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 39d31e53b4STimur Tabi 40d31e53b4STimur Tabi /* don't allow disabling of DTSEC1 as its needed for MDIO */ 41d31e53b4STimur Tabi if (port == FM1_DTSEC1) 42d31e53b4STimur Tabi return; 43d31e53b4STimur Tabi 44d31e53b4STimur Tabi setbits_be32(&gur->devdisr2, port_to_devdisr[port]); 45d31e53b4STimur Tabi } 46d31e53b4STimur Tabi 47*f51d3b71SValentin Longchamp void fman_enable_port(enum fm_port port) 48*f51d3b71SValentin Longchamp { 49*f51d3b71SValentin Longchamp ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 50*f51d3b71SValentin Longchamp 51*f51d3b71SValentin Longchamp clrbits_be32(&gur->devdisr2, port_to_devdisr[port]); 52*f51d3b71SValentin Longchamp } 53*f51d3b71SValentin Longchamp 54d31e53b4STimur Tabi phy_interface_t fman_port_enet_if(enum fm_port port) 55d31e53b4STimur Tabi { 56d31e53b4STimur Tabi ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 57d31e53b4STimur Tabi u32 rcwsr11 = in_be32(&gur->rcwsr[11]); 58d31e53b4STimur Tabi 59d31e53b4STimur Tabi if (is_device_disabled(port)) 60d31e53b4STimur Tabi return PHY_INTERFACE_MODE_NONE; 61d31e53b4STimur Tabi 62d31e53b4STimur Tabi if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1))) 63d31e53b4STimur Tabi return PHY_INTERFACE_MODE_XGMII; 64d31e53b4STimur Tabi 65d31e53b4STimur Tabi if ((port == FM2_10GEC1) && (is_serdes_configured(XAUI_FM2))) 66d31e53b4STimur Tabi return PHY_INTERFACE_MODE_XGMII; 67d31e53b4STimur Tabi 68d31e53b4STimur Tabi /* handle RGMII first */ 69d31e53b4STimur Tabi if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) == 70d31e53b4STimur Tabi FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII)) 71d31e53b4STimur Tabi return PHY_INTERFACE_MODE_RGMII; 72d31e53b4STimur Tabi 73d31e53b4STimur Tabi if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) == 74d31e53b4STimur Tabi FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII)) 75d31e53b4STimur Tabi return PHY_INTERFACE_MODE_MII; 76d31e53b4STimur Tabi 77d31e53b4STimur Tabi if ((port == FM2_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == 78d31e53b4STimur Tabi FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII)) 79d31e53b4STimur Tabi return PHY_INTERFACE_MODE_RGMII; 80d31e53b4STimur Tabi 81d31e53b4STimur Tabi if ((port == FM2_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == 82d31e53b4STimur Tabi FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII)) 83d31e53b4STimur Tabi return PHY_INTERFACE_MODE_MII; 84d31e53b4STimur Tabi 85d31e53b4STimur Tabi switch (port) { 86d31e53b4STimur Tabi case FM1_DTSEC1: 87d31e53b4STimur Tabi case FM1_DTSEC2: 88d31e53b4STimur Tabi case FM1_DTSEC3: 89d31e53b4STimur Tabi case FM1_DTSEC4: 90d31e53b4STimur Tabi case FM1_DTSEC5: 91d31e53b4STimur Tabi if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) 92d31e53b4STimur Tabi return PHY_INTERFACE_MODE_SGMII; 93d31e53b4STimur Tabi break; 94d31e53b4STimur Tabi case FM2_DTSEC1: 95d31e53b4STimur Tabi case FM2_DTSEC2: 96d31e53b4STimur Tabi case FM2_DTSEC3: 97d31e53b4STimur Tabi case FM2_DTSEC4: 98d31e53b4STimur Tabi case FM2_DTSEC5: 99d31e53b4STimur Tabi if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1)) 100d31e53b4STimur Tabi return PHY_INTERFACE_MODE_SGMII; 101d31e53b4STimur Tabi break; 102d31e53b4STimur Tabi default: 103d31e53b4STimur Tabi return PHY_INTERFACE_MODE_NONE; 104d31e53b4STimur Tabi } 105d31e53b4STimur Tabi 106d31e53b4STimur Tabi return PHY_INTERFACE_MODE_NONE; 107d31e53b4STimur Tabi } 108