1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <phy.h> 8 #include <fm_eth.h> 9 #include <asm/io.h> 10 #include <asm/immap_85xx.h> 11 #include <asm/fsl_serdes.h> 12 13 static u32 port_to_devdisr[] = { 14 [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, 15 [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, 16 [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, 17 [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, 18 [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5, 19 [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1, 20 }; 21 22 static int is_device_disabled(enum fm_port port) 23 { 24 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 25 u32 devdisr2 = in_be32(&gur->devdisr2); 26 27 return port_to_devdisr[port] & devdisr2; 28 } 29 30 void fman_disable_port(enum fm_port port) 31 { 32 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 33 34 /* don't allow disabling of DTSEC1 as its needed for MDIO */ 35 if (port == FM1_DTSEC1) 36 return; 37 38 setbits_be32(&gur->devdisr2, port_to_devdisr[port]); 39 } 40 41 phy_interface_t fman_port_enet_if(enum fm_port port) 42 { 43 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 44 u32 rcwsr11 = in_be32(&gur->rcwsr[11]); 45 46 if (is_device_disabled(port)) 47 return PHY_INTERFACE_MODE_NONE; 48 49 if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1))) 50 return PHY_INTERFACE_MODE_XGMII; 51 52 /* handle RGMII first */ 53 if ((port == FM1_DTSEC4) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) == 54 FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII)) 55 return PHY_INTERFACE_MODE_RGMII; 56 57 if ((port == FM1_DTSEC4) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) == 58 FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII)) 59 return PHY_INTERFACE_MODE_MII; 60 61 if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == 62 FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII)) 63 return PHY_INTERFACE_MODE_RGMII; 64 65 if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == 66 FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII)) 67 return PHY_INTERFACE_MODE_MII; 68 69 switch (port) { 70 case FM1_DTSEC1: 71 case FM1_DTSEC2: 72 case FM1_DTSEC3: 73 case FM1_DTSEC4: 74 case FM1_DTSEC5: 75 if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) 76 return PHY_INTERFACE_MODE_SGMII; 77 break; 78 default: 79 return PHY_INTERFACE_MODE_NONE; 80 } 81 82 return PHY_INTERFACE_MODE_NONE; 83 } 84