1*c916d7c9SKumar Gala /* 2*c916d7c9SKumar Gala * Copyright 2011 Freescale Semiconductor, Inc. 3*c916d7c9SKumar Gala * 4*c916d7c9SKumar Gala * This program is free software; you can redistribute it and/or 5*c916d7c9SKumar Gala * modify it under the terms of the GNU General Public License as 6*c916d7c9SKumar Gala * published by the Free Software Foundation; either version 2 of 7*c916d7c9SKumar Gala * the License, or (at your option) any later version. 8*c916d7c9SKumar Gala * 9*c916d7c9SKumar Gala * This program is distributed in the hope that it will be useful, 10*c916d7c9SKumar Gala * but WITHOUT ANY WARRANTY; without even the implied warranty of 11*c916d7c9SKumar Gala * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12*c916d7c9SKumar Gala * GNU General Public License for more details. 13*c916d7c9SKumar Gala * 14*c916d7c9SKumar Gala * You should have received a copy of the GNU General Public License 15*c916d7c9SKumar Gala * along with this program; if not, write to the Free Software 16*c916d7c9SKumar Gala * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17*c916d7c9SKumar Gala * MA 02111-1307 USA 18*c916d7c9SKumar Gala */ 19*c916d7c9SKumar Gala #include <common.h> 20*c916d7c9SKumar Gala #include <phy.h> 21*c916d7c9SKumar Gala #include <fm_eth.h> 22*c916d7c9SKumar Gala #include <asm/io.h> 23*c916d7c9SKumar Gala #include <asm/immap_85xx.h> 24*c916d7c9SKumar Gala #include <asm/fsl_serdes.h> 25*c916d7c9SKumar Gala 26*c916d7c9SKumar Gala u32 port_to_devdisr[] = { 27*c916d7c9SKumar Gala [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, 28*c916d7c9SKumar Gala [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, 29*c916d7c9SKumar Gala [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, 30*c916d7c9SKumar Gala [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, 31*c916d7c9SKumar Gala [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1, 32*c916d7c9SKumar Gala [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1, 33*c916d7c9SKumar Gala [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2, 34*c916d7c9SKumar Gala [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3, 35*c916d7c9SKumar Gala [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4, 36*c916d7c9SKumar Gala [FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2, 37*c916d7c9SKumar Gala }; 38*c916d7c9SKumar Gala 39*c916d7c9SKumar Gala static int is_device_disabled(enum fm_port port) 40*c916d7c9SKumar Gala { 41*c916d7c9SKumar Gala ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 42*c916d7c9SKumar Gala u32 devdisr2 = in_be32(&gur->devdisr2); 43*c916d7c9SKumar Gala 44*c916d7c9SKumar Gala return port_to_devdisr[port] & devdisr2; 45*c916d7c9SKumar Gala } 46*c916d7c9SKumar Gala 47*c916d7c9SKumar Gala phy_interface_t fman_port_enet_if(enum fm_port port) 48*c916d7c9SKumar Gala { 49*c916d7c9SKumar Gala ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 50*c916d7c9SKumar Gala u32 rcwsr11 = in_be32(&gur->rcwsr[11]); 51*c916d7c9SKumar Gala 52*c916d7c9SKumar Gala if (is_device_disabled(port)) 53*c916d7c9SKumar Gala return PHY_INTERFACE_MODE_NONE; 54*c916d7c9SKumar Gala 55*c916d7c9SKumar Gala if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1))) 56*c916d7c9SKumar Gala return PHY_INTERFACE_MODE_XGMII; 57*c916d7c9SKumar Gala 58*c916d7c9SKumar Gala if ((port == FM2_10GEC1) && (is_serdes_configured(XAUI_FM2))) 59*c916d7c9SKumar Gala return PHY_INTERFACE_MODE_XGMII; 60*c916d7c9SKumar Gala 61*c916d7c9SKumar Gala /* handle RGMII first */ 62*c916d7c9SKumar Gala if ((port == FM1_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) == 63*c916d7c9SKumar Gala FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1)) 64*c916d7c9SKumar Gala return PHY_INTERFACE_MODE_RGMII; 65*c916d7c9SKumar Gala 66*c916d7c9SKumar Gala if ((port == FM1_DTSEC2) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == 67*c916d7c9SKumar Gala FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2)) 68*c916d7c9SKumar Gala return PHY_INTERFACE_MODE_RGMII; 69*c916d7c9SKumar Gala 70*c916d7c9SKumar Gala if ((port == FM2_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == 71*c916d7c9SKumar Gala FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1)) 72*c916d7c9SKumar Gala return PHY_INTERFACE_MODE_RGMII; 73*c916d7c9SKumar Gala 74*c916d7c9SKumar Gala switch (port) { 75*c916d7c9SKumar Gala case FM1_DTSEC1: 76*c916d7c9SKumar Gala case FM1_DTSEC2: 77*c916d7c9SKumar Gala case FM1_DTSEC3: 78*c916d7c9SKumar Gala case FM1_DTSEC4: 79*c916d7c9SKumar Gala if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) 80*c916d7c9SKumar Gala return PHY_INTERFACE_MODE_SGMII; 81*c916d7c9SKumar Gala break; 82*c916d7c9SKumar Gala case FM2_DTSEC1: 83*c916d7c9SKumar Gala case FM2_DTSEC2: 84*c916d7c9SKumar Gala case FM2_DTSEC3: 85*c916d7c9SKumar Gala case FM2_DTSEC4: 86*c916d7c9SKumar Gala if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1)) 87*c916d7c9SKumar Gala return PHY_INTERFACE_MODE_SGMII; 88*c916d7c9SKumar Gala break; 89*c916d7c9SKumar Gala default: 90*c916d7c9SKumar Gala return PHY_INTERFACE_MODE_NONE; 91*c916d7c9SKumar Gala } 92*c916d7c9SKumar Gala 93*c916d7c9SKumar Gala return PHY_INTERFACE_MODE_NONE; 94*c916d7c9SKumar Gala } 95