1c916d7c9SKumar Gala /* 2c916d7c9SKumar Gala * Copyright 2011 Freescale Semiconductor, Inc. 3c916d7c9SKumar Gala * 4c916d7c9SKumar Gala * This program is free software; you can redistribute it and/or 5c916d7c9SKumar Gala * modify it under the terms of the GNU General Public License as 6c916d7c9SKumar Gala * published by the Free Software Foundation; either version 2 of 7c916d7c9SKumar Gala * the License, or (at your option) any later version. 8c916d7c9SKumar Gala * 9c916d7c9SKumar Gala * This program is distributed in the hope that it will be useful, 10c916d7c9SKumar Gala * but WITHOUT ANY WARRANTY; without even the implied warranty of 11c916d7c9SKumar Gala * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12c916d7c9SKumar Gala * GNU General Public License for more details. 13c916d7c9SKumar Gala * 14c916d7c9SKumar Gala * You should have received a copy of the GNU General Public License 15c916d7c9SKumar Gala * along with this program; if not, write to the Free Software 16c916d7c9SKumar Gala * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17c916d7c9SKumar Gala * MA 02111-1307 USA 18c916d7c9SKumar Gala */ 19c916d7c9SKumar Gala #include <common.h> 20c916d7c9SKumar Gala #include <phy.h> 21c916d7c9SKumar Gala #include <fm_eth.h> 22c916d7c9SKumar Gala #include <asm/io.h> 23c916d7c9SKumar Gala #include <asm/immap_85xx.h> 24c916d7c9SKumar Gala #include <asm/fsl_serdes.h> 25c916d7c9SKumar Gala 26c916d7c9SKumar Gala u32 port_to_devdisr[] = { 27c916d7c9SKumar Gala [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, 28c916d7c9SKumar Gala [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, 29c916d7c9SKumar Gala [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, 30c916d7c9SKumar Gala [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, 31c916d7c9SKumar Gala [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1, 32c916d7c9SKumar Gala [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1, 33c916d7c9SKumar Gala [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2, 34c916d7c9SKumar Gala [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3, 35c916d7c9SKumar Gala [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4, 36c916d7c9SKumar Gala [FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2, 37c916d7c9SKumar Gala }; 38c916d7c9SKumar Gala 39c916d7c9SKumar Gala static int is_device_disabled(enum fm_port port) 40c916d7c9SKumar Gala { 41c916d7c9SKumar Gala ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 42c916d7c9SKumar Gala u32 devdisr2 = in_be32(&gur->devdisr2); 43c916d7c9SKumar Gala 44c916d7c9SKumar Gala return port_to_devdisr[port] & devdisr2; 45c916d7c9SKumar Gala } 46c916d7c9SKumar Gala 47*69a85242SKumar Gala void fman_disable_port(enum fm_port port) 48*69a85242SKumar Gala { 49*69a85242SKumar Gala ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 50*69a85242SKumar Gala setbits_be32(&gur->devdisr2, port_to_devdisr[port]); 51*69a85242SKumar Gala } 52*69a85242SKumar Gala 53c916d7c9SKumar Gala phy_interface_t fman_port_enet_if(enum fm_port port) 54c916d7c9SKumar Gala { 55c916d7c9SKumar Gala ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 56c916d7c9SKumar Gala u32 rcwsr11 = in_be32(&gur->rcwsr[11]); 57c916d7c9SKumar Gala 58c916d7c9SKumar Gala if (is_device_disabled(port)) 59c916d7c9SKumar Gala return PHY_INTERFACE_MODE_NONE; 60c916d7c9SKumar Gala 61c916d7c9SKumar Gala if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1))) 62c916d7c9SKumar Gala return PHY_INTERFACE_MODE_XGMII; 63c916d7c9SKumar Gala 64c916d7c9SKumar Gala if ((port == FM2_10GEC1) && (is_serdes_configured(XAUI_FM2))) 65c916d7c9SKumar Gala return PHY_INTERFACE_MODE_XGMII; 66c916d7c9SKumar Gala 67c916d7c9SKumar Gala /* handle RGMII first */ 68c916d7c9SKumar Gala if ((port == FM1_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) == 69c916d7c9SKumar Gala FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1)) 70c916d7c9SKumar Gala return PHY_INTERFACE_MODE_RGMII; 71c916d7c9SKumar Gala 72c916d7c9SKumar Gala if ((port == FM1_DTSEC2) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == 73c916d7c9SKumar Gala FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2)) 74c916d7c9SKumar Gala return PHY_INTERFACE_MODE_RGMII; 75c916d7c9SKumar Gala 76c916d7c9SKumar Gala if ((port == FM2_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == 77c916d7c9SKumar Gala FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1)) 78c916d7c9SKumar Gala return PHY_INTERFACE_MODE_RGMII; 79c916d7c9SKumar Gala 80c916d7c9SKumar Gala switch (port) { 81c916d7c9SKumar Gala case FM1_DTSEC1: 82c916d7c9SKumar Gala case FM1_DTSEC2: 83c916d7c9SKumar Gala case FM1_DTSEC3: 84c916d7c9SKumar Gala case FM1_DTSEC4: 85c916d7c9SKumar Gala if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) 86c916d7c9SKumar Gala return PHY_INTERFACE_MODE_SGMII; 87c916d7c9SKumar Gala break; 88c916d7c9SKumar Gala case FM2_DTSEC1: 89c916d7c9SKumar Gala case FM2_DTSEC2: 90c916d7c9SKumar Gala case FM2_DTSEC3: 91c916d7c9SKumar Gala case FM2_DTSEC4: 92c916d7c9SKumar Gala if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1)) 93c916d7c9SKumar Gala return PHY_INTERFACE_MODE_SGMII; 94c916d7c9SKumar Gala break; 95c916d7c9SKumar Gala default: 96c916d7c9SKumar Gala return PHY_INTERFACE_MODE_NONE; 97c916d7c9SKumar Gala } 98c916d7c9SKumar Gala 99c916d7c9SKumar Gala return PHY_INTERFACE_MODE_NONE; 100c916d7c9SKumar Gala } 101