1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2c916d7c9SKumar Gala /*
3c916d7c9SKumar Gala * Copyright 2011 Freescale Semiconductor, Inc.
4c916d7c9SKumar Gala */
5c916d7c9SKumar Gala #include <common.h>
6c916d7c9SKumar Gala #include <phy.h>
7c916d7c9SKumar Gala #include <fm_eth.h>
8c916d7c9SKumar Gala #include <asm/io.h>
9c916d7c9SKumar Gala #include <asm/immap_85xx.h>
10c916d7c9SKumar Gala #include <asm/fsl_serdes.h>
11c916d7c9SKumar Gala
12960d70c6SKim Phillips static u32 port_to_devdisr[] = {
13c916d7c9SKumar Gala [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
14c916d7c9SKumar Gala [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
15c916d7c9SKumar Gala [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
16c916d7c9SKumar Gala [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
17c916d7c9SKumar Gala [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1,
18c916d7c9SKumar Gala [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1,
19c916d7c9SKumar Gala [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2,
20c916d7c9SKumar Gala [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3,
21c916d7c9SKumar Gala [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4,
22c916d7c9SKumar Gala [FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2,
23c916d7c9SKumar Gala };
24c916d7c9SKumar Gala
is_device_disabled(enum fm_port port)25c916d7c9SKumar Gala static int is_device_disabled(enum fm_port port)
26c916d7c9SKumar Gala {
27c916d7c9SKumar Gala ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
28c916d7c9SKumar Gala u32 devdisr2 = in_be32(&gur->devdisr2);
29c916d7c9SKumar Gala
30c916d7c9SKumar Gala return port_to_devdisr[port] & devdisr2;
31c916d7c9SKumar Gala }
32c916d7c9SKumar Gala
fman_disable_port(enum fm_port port)3369a85242SKumar Gala void fman_disable_port(enum fm_port port)
3469a85242SKumar Gala {
3569a85242SKumar Gala ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
36f5b9e736SKumar Gala
37f5b9e736SKumar Gala /* don't allow disabling of DTSEC1 as its needed for MDIO */
38f5b9e736SKumar Gala if (port == FM1_DTSEC1)
39f5b9e736SKumar Gala return;
40f5b9e736SKumar Gala
4169a85242SKumar Gala setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
4269a85242SKumar Gala }
4369a85242SKumar Gala
fman_enable_port(enum fm_port port)44f51d3b71SValentin Longchamp void fman_enable_port(enum fm_port port)
45f51d3b71SValentin Longchamp {
46f51d3b71SValentin Longchamp ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
47f51d3b71SValentin Longchamp
48f51d3b71SValentin Longchamp clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
49f51d3b71SValentin Longchamp }
50f51d3b71SValentin Longchamp
fman_port_enet_if(enum fm_port port)51c916d7c9SKumar Gala phy_interface_t fman_port_enet_if(enum fm_port port)
52c916d7c9SKumar Gala {
53c916d7c9SKumar Gala ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
54c916d7c9SKumar Gala u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
55c916d7c9SKumar Gala
56c916d7c9SKumar Gala if (is_device_disabled(port))
57c916d7c9SKumar Gala return PHY_INTERFACE_MODE_NONE;
58c916d7c9SKumar Gala
59c916d7c9SKumar Gala if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1)))
60c916d7c9SKumar Gala return PHY_INTERFACE_MODE_XGMII;
61c916d7c9SKumar Gala
62c916d7c9SKumar Gala if ((port == FM2_10GEC1) && (is_serdes_configured(XAUI_FM2)))
63c916d7c9SKumar Gala return PHY_INTERFACE_MODE_XGMII;
64c916d7c9SKumar Gala
65c916d7c9SKumar Gala /* handle RGMII first */
66c916d7c9SKumar Gala if ((port == FM1_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
67c916d7c9SKumar Gala FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1))
68c916d7c9SKumar Gala return PHY_INTERFACE_MODE_RGMII;
69c916d7c9SKumar Gala
70c916d7c9SKumar Gala if ((port == FM1_DTSEC2) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
71c916d7c9SKumar Gala FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2))
72c916d7c9SKumar Gala return PHY_INTERFACE_MODE_RGMII;
73c916d7c9SKumar Gala
74c916d7c9SKumar Gala if ((port == FM2_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
75c916d7c9SKumar Gala FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))
76c916d7c9SKumar Gala return PHY_INTERFACE_MODE_RGMII;
77c916d7c9SKumar Gala
78c916d7c9SKumar Gala switch (port) {
79c916d7c9SKumar Gala case FM1_DTSEC1:
80c916d7c9SKumar Gala case FM1_DTSEC2:
81c916d7c9SKumar Gala case FM1_DTSEC3:
82c916d7c9SKumar Gala case FM1_DTSEC4:
83c916d7c9SKumar Gala if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
84c916d7c9SKumar Gala return PHY_INTERFACE_MODE_SGMII;
85c916d7c9SKumar Gala break;
86c916d7c9SKumar Gala case FM2_DTSEC1:
87c916d7c9SKumar Gala case FM2_DTSEC2:
88c916d7c9SKumar Gala case FM2_DTSEC3:
89c916d7c9SKumar Gala case FM2_DTSEC4:
90c916d7c9SKumar Gala if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1))
91c916d7c9SKumar Gala return PHY_INTERFACE_MODE_SGMII;
92c916d7c9SKumar Gala break;
93c916d7c9SKumar Gala default:
94c916d7c9SKumar Gala return PHY_INTERFACE_MODE_NONE;
95c916d7c9SKumar Gala }
96c916d7c9SKumar Gala
97c916d7c9SKumar Gala return PHY_INTERFACE_MODE_NONE;
98c916d7c9SKumar Gala }
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