1 /* 2 * Copyright 2012 Freescale Semiconductor, Inc. 3 * Andy Fleming <afleming@gmail.com> 4 * Roy Zang <tie-fei.zang@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 * Some part is taken from tsec.c 8 */ 9 #include <common.h> 10 #include <miiphy.h> 11 #include <phy.h> 12 #include <asm/io.h> 13 #include <asm/fsl_memac.h> 14 #include <fm_eth.h> 15 16 /* 17 * Write value to the PHY for this device to the register at regnum, waiting 18 * until the write is done before it returns. All PHY configuration has to be 19 * done through the TSEC1 MIIM regs 20 */ 21 int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, 22 int regnum, u16 value) 23 { 24 u32 mdio_ctl; 25 struct memac_mdio_controller *regs = bus->priv; 26 u32 c45 = 1; /* Default to 10G interface */ 27 28 if (dev_addr == MDIO_DEVAD_NONE) { 29 c45 = 0; /* clause 22 */ 30 dev_addr = regnum & 0x1f; 31 clrbits_be32(®s->mdio_stat, MDIO_STAT_ENC); 32 } else 33 setbits_be32(®s->mdio_stat, MDIO_STAT_ENC); 34 35 /* Wait till the bus is free */ 36 while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY) 37 ; 38 39 /* Set the port and dev addr */ 40 mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr); 41 out_be32(®s->mdio_ctl, mdio_ctl); 42 43 /* Set the register address */ 44 if (c45) 45 out_be32(®s->mdio_addr, regnum & 0xffff); 46 47 /* Wait till the bus is free */ 48 while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY) 49 ; 50 51 /* Write the value to the register */ 52 out_be32(®s->mdio_data, MDIO_DATA(value)); 53 54 /* Wait till the MDIO write is complete */ 55 while ((in_be32(®s->mdio_data)) & MDIO_DATA_BSY) 56 ; 57 58 return 0; 59 } 60 61 /* 62 * Reads from register regnum in the PHY for device dev, returning the value. 63 * Clears miimcom first. All PHY configuration has to be done through the 64 * TSEC1 MIIM regs 65 */ 66 int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, 67 int regnum) 68 { 69 u32 mdio_ctl; 70 struct memac_mdio_controller *regs = bus->priv; 71 u32 c45 = 1; 72 73 if (dev_addr == MDIO_DEVAD_NONE) { 74 if (!strcmp(bus->name, DEFAULT_FM_TGEC_MDIO_NAME)) 75 return 0xffff; 76 c45 = 0; /* clause 22 */ 77 dev_addr = regnum & 0x1f; 78 clrbits_be32(®s->mdio_stat, MDIO_STAT_ENC); 79 } else 80 setbits_be32(®s->mdio_stat, MDIO_STAT_ENC); 81 82 /* Wait till the bus is free */ 83 while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY) 84 ; 85 86 /* Set the Port and Device Addrs */ 87 mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr); 88 out_be32(®s->mdio_ctl, mdio_ctl); 89 90 /* Set the register address */ 91 if (c45) 92 out_be32(®s->mdio_addr, regnum & 0xffff); 93 94 /* Wait till the bus is free */ 95 while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY) 96 ; 97 98 /* Initiate the read */ 99 mdio_ctl |= MDIO_CTL_READ; 100 out_be32(®s->mdio_ctl, mdio_ctl); 101 102 /* Wait till the MDIO write is complete */ 103 while ((in_be32(®s->mdio_data)) & MDIO_DATA_BSY) 104 ; 105 106 /* Return all Fs if nothing was there */ 107 if (in_be32(®s->mdio_stat) & MDIO_STAT_RD_ER) 108 return 0xffff; 109 110 return in_be32(®s->mdio_data) & 0xffff; 111 } 112 113 int memac_mdio_reset(struct mii_dev *bus) 114 { 115 return 0; 116 } 117 118 int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info) 119 { 120 struct mii_dev *bus = mdio_alloc(); 121 122 if (!bus) { 123 printf("Failed to allocate FM TGEC MDIO bus\n"); 124 return -1; 125 } 126 127 bus->read = memac_mdio_read; 128 bus->write = memac_mdio_write; 129 bus->reset = memac_mdio_reset; 130 sprintf(bus->name, info->name); 131 132 bus->priv = info->regs; 133 134 /* 135 * On some platforms like B4860, default value of MDIO_CLK_DIV bits 136 * in mdio_stat(mdio_cfg) register generates MDIO clock too high 137 * (much higher than 2.5MHz), violating the IEEE specs. 138 * On other platforms like T1040, default value of MDIO_CLK_DIV bits 139 * is zero, so MDIO clock is disabled. 140 * So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to 141 * be properly initialized. 142 * NEG bit default should be '1' as per FMAN-v3 RM, but on platform 143 * like T2080QDS, this bit default is '0', which leads to MDIO failure 144 * on XAUI PHY, so set this bit definitely. 145 */ 146 setbits_be32(&((struct memac_mdio_controller *)info->regs)->mdio_stat, 147 MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG); 148 149 return mdio_register(bus); 150 } 151