1 /* 2 * Copyright 2012 Freescale Semiconductor, Inc. 3 * Roy Zang <tie-fei.zang@freescale.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* MAXFRM - maximum frame length */ 9 #define MAXFRM_MASK 0x0000ffff 10 11 #include <common.h> 12 #include <phy.h> 13 #include <asm/types.h> 14 #include <asm/io.h> 15 #include <fsl_memac.h> 16 17 #include "fm.h" 18 19 static void memac_init_mac(struct fsl_enet_mac *mac) 20 { 21 struct memac *regs = mac->base; 22 23 /* mask all interrupt */ 24 out_be32(®s->imask, IMASK_MASK_ALL); 25 26 /* clear all events */ 27 out_be32(®s->ievent, IEVENT_CLEAR_ALL); 28 29 /* set the max receive length */ 30 out_be32(®s->maxfrm, mac->max_rx_len & MAXFRM_MASK); 31 32 /* multicast frame reception for the hash entry disable */ 33 out_be32(®s->hashtable_ctrl, 0); 34 } 35 36 static void memac_enable_mac(struct fsl_enet_mac *mac) 37 { 38 struct memac *regs = mac->base; 39 40 setbits_be32(®s->command_config, 41 MEMAC_CMD_CFG_RXTX_EN | MEMAC_CMD_CFG_NO_LEN_CHK); 42 } 43 44 static void memac_disable_mac(struct fsl_enet_mac *mac) 45 { 46 struct memac *regs = mac->base; 47 48 clrbits_be32(®s->command_config, MEMAC_CMD_CFG_RXTX_EN); 49 } 50 51 static void memac_set_mac_addr(struct fsl_enet_mac *mac, u8 *mac_addr) 52 { 53 struct memac *regs = mac->base; 54 u32 mac_addr0, mac_addr1; 55 56 /* 57 * if a station address of 0x12345678ABCD, perform a write to 58 * MAC_ADDR0 of 0x78563412, MAC_ADDR1 of 0x0000CDAB 59 */ 60 mac_addr0 = (mac_addr[3] << 24) | (mac_addr[2] << 16) | \ 61 (mac_addr[1] << 8) | (mac_addr[0]); 62 out_be32(®s->mac_addr_0, mac_addr0); 63 64 mac_addr1 = ((mac_addr[5] << 8) | mac_addr[4]) & 0x0000ffff; 65 out_be32(®s->mac_addr_1, mac_addr1); 66 } 67 68 static void memac_set_interface_mode(struct fsl_enet_mac *mac, 69 phy_interface_t type, int speed) 70 { 71 /* Roy need more work here */ 72 73 struct memac *regs = mac->base; 74 u32 if_mode, if_status; 75 76 /* clear all bits relative with interface mode */ 77 if_mode = in_be32(®s->if_mode); 78 if_status = in_be32(®s->if_status); 79 80 /* set interface mode */ 81 switch (type) { 82 case PHY_INTERFACE_MODE_GMII: 83 if_mode &= ~IF_MODE_MASK; 84 if_mode |= IF_MODE_GMII; 85 break; 86 case PHY_INTERFACE_MODE_RGMII: 87 if_mode |= (IF_MODE_GMII | IF_MODE_RG); 88 break; 89 case PHY_INTERFACE_MODE_RMII: 90 if_mode |= (IF_MODE_GMII | IF_MODE_RM); 91 break; 92 case PHY_INTERFACE_MODE_SGMII: 93 case PHY_INTERFACE_MODE_SGMII_2500: 94 case PHY_INTERFACE_MODE_QSGMII: 95 if_mode &= ~IF_MODE_MASK; 96 if_mode |= (IF_MODE_GMII); 97 break; 98 case PHY_INTERFACE_MODE_XGMII: 99 if_mode &= ~IF_MODE_MASK; 100 if_mode |= IF_MODE_XGMII; 101 break; 102 default: 103 break; 104 } 105 /* Enable automatic speed selection for Non-XGMII */ 106 if (type != PHY_INTERFACE_MODE_XGMII) 107 if_mode |= IF_MODE_EN_AUTO; 108 109 if (type == PHY_INTERFACE_MODE_RGMII) { 110 if_mode &= ~IF_MODE_EN_AUTO; 111 if_mode &= ~IF_MODE_SETSP_MASK; 112 switch (speed) { 113 case SPEED_1000: 114 if_mode |= IF_MODE_SETSP_1000M; 115 break; 116 case SPEED_100: 117 if_mode |= IF_MODE_SETSP_100M; 118 break; 119 case SPEED_10: 120 if_mode |= IF_MODE_SETSP_10M; 121 default: 122 break; 123 } 124 } 125 126 debug(" %s, if_mode = %x\n", __func__, if_mode); 127 debug(" %s, if_status = %x\n", __func__, if_status); 128 out_be32(®s->if_mode, if_mode); 129 return; 130 } 131 132 void init_memac(struct fsl_enet_mac *mac, void *base, 133 void *phyregs, int max_rx_len) 134 { 135 mac->base = base; 136 mac->phyregs = phyregs; 137 mac->max_rx_len = max_rx_len; 138 mac->init_mac = memac_init_mac; 139 mac->enable_mac = memac_enable_mac; 140 mac->disable_mac = memac_disable_mac; 141 mac->set_mac_addr = memac_set_mac_addr; 142 mac->set_if_mode = memac_set_interface_mode; 143 } 144