1 /* 2 * Copyright 2012 Freescale Semiconductor, Inc. 3 * Roy Zang <tie-fei.zang@freescale.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* MAXFRM - maximum frame length */ 9 #define MAXFRM_MASK 0x0000ffff 10 11 #include <common.h> 12 #include <phy.h> 13 #include <asm/types.h> 14 #include <asm/io.h> 15 #include <asm/fsl_memac.h> 16 17 #include "fm.h" 18 19 static void memac_init_mac(struct fsl_enet_mac *mac) 20 { 21 struct memac *regs = mac->base; 22 23 /* mask all interrupt */ 24 out_be32(®s->imask, IMASK_MASK_ALL); 25 26 /* clear all events */ 27 out_be32(®s->ievent, IEVENT_CLEAR_ALL); 28 29 /* set the max receive length */ 30 out_be32(®s->maxfrm, mac->max_rx_len & MAXFRM_MASK); 31 32 /* multicast frame reception for the hash entry disable */ 33 out_be32(®s->hashtable_ctrl, 0); 34 } 35 36 static void memac_enable_mac(struct fsl_enet_mac *mac) 37 { 38 struct memac *regs = mac->base; 39 40 setbits_be32(®s->command_config, MEMAC_CMD_CFG_RXTX_EN); 41 } 42 43 static void memac_disable_mac(struct fsl_enet_mac *mac) 44 { 45 struct memac *regs = mac->base; 46 47 clrbits_be32(®s->command_config, MEMAC_CMD_CFG_RXTX_EN); 48 } 49 50 static void memac_set_mac_addr(struct fsl_enet_mac *mac, u8 *mac_addr) 51 { 52 struct memac *regs = mac->base; 53 u32 mac_addr0, mac_addr1; 54 55 /* 56 * if a station address of 0x12345678ABCD, perform a write to 57 * MAC_ADDR0 of 0x78563412, MAC_ADDR1 of 0x0000CDAB 58 */ 59 mac_addr0 = (mac_addr[3] << 24) | (mac_addr[2] << 16) | \ 60 (mac_addr[1] << 8) | (mac_addr[0]); 61 out_be32(®s->mac_addr_0, mac_addr0); 62 63 mac_addr1 = ((mac_addr[5] << 8) | mac_addr[4]) & 0x0000ffff; 64 out_be32(®s->mac_addr_1, mac_addr1); 65 } 66 67 static void memac_set_interface_mode(struct fsl_enet_mac *mac, 68 phy_interface_t type, int speed) 69 { 70 /* Roy need more work here */ 71 72 struct memac *regs = mac->base; 73 u32 if_mode, if_status; 74 75 /* clear all bits relative with interface mode */ 76 if_mode = in_be32(®s->if_mode); 77 if_status = in_be32(®s->if_status); 78 79 /* set interface mode */ 80 switch (type) { 81 case PHY_INTERFACE_MODE_GMII: 82 if_mode &= ~IF_MODE_MASK; 83 if_mode |= IF_MODE_GMII; 84 break; 85 case PHY_INTERFACE_MODE_RGMII: 86 if_mode |= (IF_MODE_GMII | IF_MODE_RG); 87 break; 88 case PHY_INTERFACE_MODE_RMII: 89 if_mode |= (IF_MODE_GMII | IF_MODE_RM); 90 break; 91 case PHY_INTERFACE_MODE_SGMII: 92 case PHY_INTERFACE_MODE_QSGMII: 93 if_mode &= ~IF_MODE_MASK; 94 if_mode |= (IF_MODE_GMII); 95 break; 96 default: 97 break; 98 } 99 /* Enable automatic speed selection */ 100 if_mode |= IF_MODE_EN_AUTO; 101 102 if (type == PHY_INTERFACE_MODE_RGMII) { 103 if_mode &= ~IF_MODE_EN_AUTO; 104 if_mode &= ~IF_MODE_SETSP_MASK; 105 switch (speed) { 106 case SPEED_1000: 107 if_mode |= IF_MODE_SETSP_1000M; 108 break; 109 case SPEED_100: 110 if_mode |= IF_MODE_SETSP_100M; 111 break; 112 case SPEED_10: 113 if_mode |= IF_MODE_SETSP_10M; 114 default: 115 break; 116 } 117 } 118 119 debug(" %s, if_mode = %x\n", __func__, if_mode); 120 debug(" %s, if_status = %x\n", __func__, if_status); 121 out_be32(®s->if_mode, if_mode); 122 return; 123 } 124 125 void init_memac(struct fsl_enet_mac *mac, void *base, 126 void *phyregs, int max_rx_len) 127 { 128 mac->base = base; 129 mac->phyregs = phyregs; 130 mac->max_rx_len = max_rx_len; 131 mac->init_mac = memac_init_mac; 132 mac->enable_mac = memac_enable_mac; 133 mac->disable_mac = memac_disable_mac; 134 mac->set_mac_addr = memac_set_mac_addr; 135 mac->set_if_mode = memac_set_interface_mode; 136 } 137