1 /* 2 * Copyright 2012 Freescale Semiconductor, Inc. 3 * Roy Zang <tie-fei.zang@freescale.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* MAXFRM - maximum frame length */ 9 #define MAXFRM_MASK 0x0000ffff 10 11 #include <common.h> 12 #include <phy.h> 13 #include <asm/types.h> 14 #include <asm/io.h> 15 #include <asm/fsl_enet.h> 16 #include <asm/fsl_memac.h> 17 18 #include "fm.h" 19 20 static void memac_init_mac(struct fsl_enet_mac *mac) 21 { 22 struct memac *regs = mac->base; 23 24 /* mask all interrupt */ 25 out_be32(®s->imask, IMASK_MASK_ALL); 26 27 /* clear all events */ 28 out_be32(®s->ievent, IEVENT_CLEAR_ALL); 29 30 /* set the max receive length */ 31 out_be32(®s->maxfrm, mac->max_rx_len & MAXFRM_MASK); 32 33 /* multicast frame reception for the hash entry disable */ 34 out_be32(®s->hashtable_ctrl, 0); 35 } 36 37 static void memac_enable_mac(struct fsl_enet_mac *mac) 38 { 39 struct memac *regs = mac->base; 40 41 setbits_be32(®s->command_config, MEMAC_CMD_CFG_RXTX_EN); 42 } 43 44 static void memac_disable_mac(struct fsl_enet_mac *mac) 45 { 46 struct memac *regs = mac->base; 47 48 clrbits_be32(®s->command_config, MEMAC_CMD_CFG_RXTX_EN); 49 } 50 51 static void memac_set_mac_addr(struct fsl_enet_mac *mac, u8 *mac_addr) 52 { 53 struct memac *regs = mac->base; 54 u32 mac_addr0, mac_addr1; 55 56 /* 57 * if a station address of 0x12345678ABCD, perform a write to 58 * MAC_ADDR0 of 0x78563412, MAC_ADDR1 of 0x0000CDAB 59 */ 60 mac_addr0 = (mac_addr[3] << 24) | (mac_addr[2] << 16) | \ 61 (mac_addr[1] << 8) | (mac_addr[0]); 62 out_be32(®s->mac_addr_0, mac_addr0); 63 64 mac_addr1 = ((mac_addr[5] << 8) | mac_addr[4]) & 0x0000ffff; 65 out_be32(®s->mac_addr_1, mac_addr1); 66 } 67 68 static void memac_set_interface_mode(struct fsl_enet_mac *mac, 69 phy_interface_t type, int speed) 70 { 71 /* Roy need more work here */ 72 73 struct memac *regs = mac->base; 74 u32 if_mode, if_status; 75 76 /* clear all bits relative with interface mode */ 77 if_mode = in_be32(®s->if_mode); 78 if_status = in_be32(®s->if_status); 79 80 /* set interface mode */ 81 switch (type) { 82 case PHY_INTERFACE_MODE_GMII: 83 if_mode &= ~IF_MODE_MASK; 84 if_mode |= IF_MODE_GMII; 85 break; 86 case PHY_INTERFACE_MODE_RGMII: 87 if_mode |= (IF_MODE_GMII | IF_MODE_RG); 88 break; 89 case PHY_INTERFACE_MODE_RMII: 90 if_mode |= (IF_MODE_GMII | IF_MODE_RM); 91 break; 92 case PHY_INTERFACE_MODE_SGMII: 93 if_mode &= ~IF_MODE_MASK; 94 if_mode |= (IF_MODE_GMII); 95 break; 96 default: 97 break; 98 } 99 /* Enable automatic speed selection */ 100 if_mode |= IF_MODE_EN_AUTO; 101 102 if (type == PHY_INTERFACE_MODE_RGMII) { 103 if_mode &= ~IF_MODE_EN_AUTO; 104 if_mode &= ~IF_MODE_SETSP_MASK; 105 switch (speed) { 106 case SPEED_1000: 107 if_mode |= IF_MODE_SETSP_1000M; 108 break; 109 case SPEED_100: 110 if_mode |= IF_MODE_SETSP_100M; 111 break; 112 case SPEED_10: 113 if_mode |= IF_MODE_SETSP_10M; 114 default: 115 break; 116 } 117 } 118 119 debug(" %s, if_mode = %x\n", __func__, if_mode); 120 debug(" %s, if_status = %x\n", __func__, if_status); 121 out_be32(®s->if_mode, if_mode); 122 return; 123 } 124 125 void init_memac(struct fsl_enet_mac *mac, void *base, 126 void *phyregs, int max_rx_len) 127 { 128 mac->base = base; 129 mac->phyregs = phyregs; 130 mac->max_rx_len = max_rx_len; 131 mac->init_mac = memac_init_mac; 132 mac->enable_mac = memac_enable_mac; 133 mac->disable_mac = memac_disable_mac; 134 mac->set_mac_addr = memac_set_mac_addr; 135 mac->set_if_mode = memac_set_interface_mode; 136 } 137