1 /* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <phy.h> 8 #include <fm_eth.h> 9 #include <asm/io.h> 10 #include <asm/arch/fsl_serdes.h> 11 12 #define FSL_CHASSIS2_RCWSR13_EC1 0xe0000000 /* bits 416..418 */ 13 #define FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII 0x00000000 14 #define FSL_CHASSIS2_RCWSR13_EC1_GPIO 0x20000000 15 #define FSL_CHASSIS2_RCWSR13_EC1_FTM 0xa0000000 16 #define FSL_CHASSIS2_RCWSR13_EC2 0x1c000000 /* bits 419..421 */ 17 #define FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII 0x00000000 18 #define FSL_CHASSIS2_RCWSR13_EC2_GPIO 0x04000000 19 #define FSL_CHASSIS2_RCWSR13_EC2_1588 0x08000000 20 #define FSL_CHASSIS2_RCWSR13_EC2_FTM 0x14000000 21 22 u32 port_to_devdisr[] = { 23 [FM1_DTSEC1] = FSL_CHASSIS2_DEVDISR2_DTSEC1_1, 24 [FM1_DTSEC2] = FSL_CHASSIS2_DEVDISR2_DTSEC1_2, 25 [FM1_DTSEC3] = FSL_CHASSIS2_DEVDISR2_DTSEC1_3, 26 [FM1_DTSEC4] = FSL_CHASSIS2_DEVDISR2_DTSEC1_4, 27 [FM1_DTSEC5] = FSL_CHASSIS2_DEVDISR2_DTSEC1_5, 28 [FM1_DTSEC6] = FSL_CHASSIS2_DEVDISR2_DTSEC1_6, 29 [FM1_DTSEC9] = FSL_CHASSIS2_DEVDISR2_DTSEC1_9, 30 [FM1_DTSEC10] = FSL_CHASSIS2_DEVDISR2_DTSEC1_10, 31 [FM1_10GEC1] = FSL_CHASSIS2_DEVDISR2_10GEC1_1, 32 [FM1_10GEC2] = FSL_CHASSIS2_DEVDISR2_10GEC1_2, 33 [FM1_10GEC3] = FSL_CHASSIS2_DEVDISR2_10GEC1_3, 34 [FM1_10GEC4] = FSL_CHASSIS2_DEVDISR2_10GEC1_4, 35 }; 36 37 static int is_device_disabled(enum fm_port port) 38 { 39 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 40 u32 devdisr2 = in_be32(&gur->devdisr2); 41 42 return port_to_devdisr[port] & devdisr2; 43 } 44 45 void fman_disable_port(enum fm_port port) 46 { 47 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 48 49 setbits_be32(&gur->devdisr2, port_to_devdisr[port]); 50 } 51 52 phy_interface_t fman_port_enet_if(enum fm_port port) 53 { 54 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 55 u32 rcwsr13 = in_be32(&gur->rcwsr[13]); 56 57 if (is_device_disabled(port)) 58 return PHY_INTERFACE_MODE_NONE; 59 60 if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9))) 61 return PHY_INTERFACE_MODE_XGMII; 62 63 if ((port == FM1_DTSEC9) && (is_serdes_configured(XFI_FM1_MAC9))) 64 return PHY_INTERFACE_MODE_NONE; 65 66 if (port == FM1_DTSEC3) 67 if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) == 68 FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII) { 69 return PHY_INTERFACE_MODE_RGMII; 70 } 71 if (port == FM1_DTSEC4) 72 if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) == 73 FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII) { 74 return PHY_INTERFACE_MODE_RGMII; 75 } 76 77 /* handle SGMII */ 78 switch (port) { 79 case FM1_DTSEC1: 80 case FM1_DTSEC2: 81 if ((port == FM1_DTSEC2) && 82 is_serdes_configured(SGMII_2500_FM1_DTSEC2)) 83 return PHY_INTERFACE_MODE_SGMII_2500; 84 case FM1_DTSEC5: 85 case FM1_DTSEC6: 86 case FM1_DTSEC9: 87 if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) 88 return PHY_INTERFACE_MODE_SGMII; 89 else if ((port == FM1_DTSEC9) && 90 is_serdes_configured(SGMII_2500_FM1_DTSEC9)) 91 return PHY_INTERFACE_MODE_SGMII_2500; 92 break; 93 default: 94 break; 95 } 96 97 /* handle QSGMII */ 98 switch (port) { 99 case FM1_DTSEC1: 100 case FM1_DTSEC2: 101 case FM1_DTSEC5: 102 case FM1_DTSEC6: 103 /* only MAC 1,2,5,6 available for QSGMII */ 104 if (is_serdes_configured(QSGMII_FM1_A)) 105 return PHY_INTERFACE_MODE_QSGMII; 106 break; 107 default: 108 break; 109 } 110 111 return PHY_INTERFACE_MODE_NONE; 112 } 113