xref: /openbmc/u-boot/drivers/net/fm/eth.c (revision 71a988aa)
1 /*
2  * Copyright 2009-2012 Freescale Semiconductor, Inc.
3  *	Dave Liu <daveliu@freescale.com>
4  *
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public License as
7  * published by the Free Software Foundation; either version 2 of
8  * the License, or (at your option) any later version.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18  * MA 02111-1307 USA
19  */
20 #include <common.h>
21 #include <asm/io.h>
22 #include <malloc.h>
23 #include <net.h>
24 #include <hwconfig.h>
25 #include <fm_eth.h>
26 #include <fsl_mdio.h>
27 #include <miiphy.h>
28 #include <phy.h>
29 #include <asm/fsl_dtsec.h>
30 #include <asm/fsl_tgec.h>
31 #include <asm/fsl_memac.h>
32 
33 #include "fm.h"
34 
35 static struct eth_device *devlist[NUM_FM_PORTS];
36 static int num_controllers;
37 
38 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
39 
40 #define TBIANA_SETTINGS (TBIANA_ASYMMETRIC_PAUSE | TBIANA_SYMMETRIC_PAUSE | \
41 			 TBIANA_FULL_DUPLEX)
42 
43 #define TBIANA_SGMII_ACK 0x4001
44 
45 #define TBICR_SETTINGS (TBICR_ANEG_ENABLE | TBICR_RESTART_ANEG | \
46 			TBICR_FULL_DUPLEX | TBICR_SPEED1_SET)
47 
48 /* Configure the TBI for SGMII operation */
49 static void dtsec_configure_serdes(struct fm_eth *priv)
50 {
51 #ifdef CONFIG_SYS_FMAN_V3
52 	u32 value;
53 	struct mii_dev bus;
54 	bus.priv = priv->mac->phyregs;
55 
56 	/* SGMII IF mode + AN enable */
57 	value = PHY_SGMII_IF_MODE_AN | PHY_SGMII_IF_MODE_SGMII;
58 	memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value);
59 
60 	/* Dev ability according to SGMII specification */
61 	value = PHY_SGMII_DEV_ABILITY_SGMII;
62 	memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x4, value);
63 
64 	/* Adjust link timer for SGMII  -
65 	1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40 */
66 	memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x3);
67 	memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0xd40);
68 
69 	/* Restart AN */
70 	value = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN;
71 	memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0, value);
72 #else
73 	struct dtsec *regs = priv->mac->base;
74 	struct tsec_mii_mng *phyregs = priv->mac->phyregs;
75 
76 	/*
77 	 * Access TBI PHY registers at given TSEC register offset as
78 	 * opposed to the register offset used for external PHY accesses
79 	 */
80 	tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_TBICON,
81 			TBICON_CLK_SELECT);
82 	tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_ANA,
83 			TBIANA_SGMII_ACK);
84 	tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0,
85 			TBI_CR, TBICR_SETTINGS);
86 #endif
87 }
88 
89 static void dtsec_init_phy(struct eth_device *dev)
90 {
91 	struct fm_eth *fm_eth = dev->priv;
92 #ifndef CONFIG_SYS_FMAN_V3
93 	struct dtsec *regs = (struct dtsec *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
94 
95 	/* Assign a Physical address to the TBI */
96 	out_be32(&regs->tbipa, CONFIG_SYS_TBIPA_VALUE);
97 #endif
98 
99 	if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII)
100 		dtsec_configure_serdes(fm_eth);
101 }
102 
103 static int tgec_is_fibre(struct eth_device *dev)
104 {
105 	struct fm_eth *fm = dev->priv;
106 	char phyopt[20];
107 
108 	sprintf(phyopt, "fsl_fm%d_xaui_phy", fm->fm_index + 1);
109 
110 	return hwconfig_arg_cmp(phyopt, "xfi");
111 }
112 #endif
113 
114 static u16 muram_readw(u16 *addr)
115 {
116 	u32 base = (u32)addr & ~0x3;
117 	u32 val32 = *(u32 *)base;
118 	int byte_pos;
119 	u16 ret;
120 
121 	byte_pos = (u32)addr & 0x3;
122 	if (byte_pos)
123 		ret = (u16)(val32 & 0x0000ffff);
124 	else
125 		ret = (u16)((val32 & 0xffff0000) >> 16);
126 
127 	return ret;
128 }
129 
130 static void muram_writew(u16 *addr, u16 val)
131 {
132 	u32 base = (u32)addr & ~0x3;
133 	u32 org32 = *(u32 *)base;
134 	u32 val32;
135 	int byte_pos;
136 
137 	byte_pos = (u32)addr & 0x3;
138 	if (byte_pos)
139 		val32 = (org32 & 0xffff0000) | val;
140 	else
141 		val32 = (org32 & 0x0000ffff) | ((u32)val << 16);
142 
143 	*(u32 *)base = val32;
144 }
145 
146 static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port)
147 {
148 	int timeout = 1000000;
149 
150 	clrbits_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_EN);
151 
152 	/* wait until the rx port is not busy */
153 	while ((in_be32(&rx_port->fmbm_rst) & FMBM_RST_BSY) && timeout--)
154 		;
155 }
156 
157 static void bmi_rx_port_init(struct fm_bmi_rx_port *rx_port)
158 {
159 	/* set BMI to independent mode, Rx port disable */
160 	out_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_IM);
161 	/* clear FOF in IM case */
162 	out_be32(&rx_port->fmbm_rim, 0);
163 	/* Rx frame next engine -RISC */
164 	out_be32(&rx_port->fmbm_rfne, NIA_ENG_RISC | NIA_RISC_AC_IM_RX);
165 	/* Rx command attribute - no order, MR[3] = 1 */
166 	clrbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_ORDER | FMBM_RFCA_MR_MASK);
167 	setbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_MR(4));
168 	/* enable Rx statistic counters */
169 	out_be32(&rx_port->fmbm_rstc, FMBM_RSTC_EN);
170 	/* disable Rx performance counters */
171 	out_be32(&rx_port->fmbm_rpc, 0);
172 }
173 
174 static void bmi_tx_port_disable(struct fm_bmi_tx_port *tx_port)
175 {
176 	int timeout = 1000000;
177 
178 	clrbits_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_EN);
179 
180 	/* wait until the tx port is not busy */
181 	while ((in_be32(&tx_port->fmbm_tst) & FMBM_TST_BSY) && timeout--)
182 		;
183 }
184 
185 static void bmi_tx_port_init(struct fm_bmi_tx_port *tx_port)
186 {
187 	/* set BMI to independent mode, Tx port disable */
188 	out_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_IM);
189 	/* Tx frame next engine -RISC */
190 	out_be32(&tx_port->fmbm_tfne, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
191 	out_be32(&tx_port->fmbm_tfene, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
192 	/* Tx command attribute - no order, MR[3] = 1 */
193 	clrbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_ORDER | FMBM_TFCA_MR_MASK);
194 	setbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_MR(4));
195 	/* enable Tx statistic counters */
196 	out_be32(&tx_port->fmbm_tstc, FMBM_TSTC_EN);
197 	/* disable Tx performance counters */
198 	out_be32(&tx_port->fmbm_tpc, 0);
199 }
200 
201 static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
202 {
203 	struct fm_port_global_pram *pram;
204 	u32 pram_page_offset;
205 	void *rx_bd_ring_base;
206 	void *rx_buf_pool;
207 	struct fm_port_bd *rxbd;
208 	struct fm_port_qd *rxqd;
209 	struct fm_bmi_rx_port *bmi_rx_port = fm_eth->rx_port;
210 	int i;
211 
212 	/* alloc global parameter ram at MURAM */
213 	pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
214 		FM_PRAM_SIZE, FM_PRAM_ALIGN);
215 	fm_eth->rx_pram = pram;
216 
217 	/* parameter page offset to MURAM */
218 	pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index);
219 
220 	/* enable global mode- snooping data buffers and BDs */
221 	pram->mode = PRAM_MODE_GLOBAL;
222 
223 	/* init the Rx queue descriptor pionter */
224 	pram->rxqd_ptr = pram_page_offset + 0x20;
225 
226 	/* set the max receive buffer length, power of 2 */
227 	muram_writew(&pram->mrblr, MAX_RXBUF_LOG2);
228 
229 	/* alloc Rx buffer descriptors from main memory */
230 	rx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
231 			* RX_BD_RING_SIZE);
232 	if (!rx_bd_ring_base)
233 		return 0;
234 	memset(rx_bd_ring_base, 0, sizeof(struct fm_port_bd)
235 			* RX_BD_RING_SIZE);
236 
237 	/* alloc Rx buffer from main memory */
238 	rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE);
239 	if (!rx_buf_pool)
240 		return 0;
241 	memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE);
242 
243 	/* save them to fm_eth */
244 	fm_eth->rx_bd_ring = rx_bd_ring_base;
245 	fm_eth->cur_rxbd = rx_bd_ring_base;
246 	fm_eth->rx_buf = rx_buf_pool;
247 
248 	/* init Rx BDs ring */
249 	rxbd = (struct fm_port_bd *)rx_bd_ring_base;
250 	for (i = 0; i < RX_BD_RING_SIZE; i++) {
251 		rxbd->status = RxBD_EMPTY;
252 		rxbd->len = 0;
253 		rxbd->buf_ptr_hi = 0;
254 		rxbd->buf_ptr_lo = (u32)rx_buf_pool + i * MAX_RXBUF_LEN;
255 		rxbd++;
256 	}
257 
258 	/* set the Rx queue descriptor */
259 	rxqd = &pram->rxqd;
260 	muram_writew(&rxqd->gen, 0);
261 	muram_writew(&rxqd->bd_ring_base_hi, 0);
262 	rxqd->bd_ring_base_lo = (u32)rx_bd_ring_base;
263 	muram_writew(&rxqd->bd_ring_size, sizeof(struct fm_port_bd)
264 			* RX_BD_RING_SIZE);
265 	muram_writew(&rxqd->offset_in, 0);
266 	muram_writew(&rxqd->offset_out, 0);
267 
268 	/* set IM parameter ram pointer to Rx Frame Queue ID */
269 	out_be32(&bmi_rx_port->fmbm_rfqid, pram_page_offset);
270 
271 	return 1;
272 }
273 
274 static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
275 {
276 	struct fm_port_global_pram *pram;
277 	u32 pram_page_offset;
278 	void *tx_bd_ring_base;
279 	struct fm_port_bd *txbd;
280 	struct fm_port_qd *txqd;
281 	struct fm_bmi_tx_port *bmi_tx_port = fm_eth->tx_port;
282 	int i;
283 
284 	/* alloc global parameter ram at MURAM */
285 	pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
286 		FM_PRAM_SIZE, FM_PRAM_ALIGN);
287 	fm_eth->tx_pram = pram;
288 
289 	/* parameter page offset to MURAM */
290 	pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index);
291 
292 	/* enable global mode- snooping data buffers and BDs */
293 	pram->mode = PRAM_MODE_GLOBAL;
294 
295 	/* init the Tx queue descriptor pionter */
296 	pram->txqd_ptr = pram_page_offset + 0x40;
297 
298 	/* alloc Tx buffer descriptors from main memory */
299 	tx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
300 			* TX_BD_RING_SIZE);
301 	if (!tx_bd_ring_base)
302 		return 0;
303 	memset(tx_bd_ring_base, 0, sizeof(struct fm_port_bd)
304 			* TX_BD_RING_SIZE);
305 	/* save it to fm_eth */
306 	fm_eth->tx_bd_ring = tx_bd_ring_base;
307 	fm_eth->cur_txbd = tx_bd_ring_base;
308 
309 	/* init Tx BDs ring */
310 	txbd = (struct fm_port_bd *)tx_bd_ring_base;
311 	for (i = 0; i < TX_BD_RING_SIZE; i++) {
312 		txbd->status = TxBD_LAST;
313 		txbd->len = 0;
314 		txbd->buf_ptr_hi = 0;
315 		txbd->buf_ptr_lo = 0;
316 	}
317 
318 	/* set the Tx queue decriptor */
319 	txqd = &pram->txqd;
320 	muram_writew(&txqd->bd_ring_base_hi, 0);
321 	txqd->bd_ring_base_lo = (u32)tx_bd_ring_base;
322 	muram_writew(&txqd->bd_ring_size, sizeof(struct fm_port_bd)
323 			* TX_BD_RING_SIZE);
324 	muram_writew(&txqd->offset_in, 0);
325 	muram_writew(&txqd->offset_out, 0);
326 
327 	/* set IM parameter ram pointer to Tx Confirmation Frame Queue ID */
328 	out_be32(&bmi_tx_port->fmbm_tcfqid, pram_page_offset);
329 
330 	return 1;
331 }
332 
333 static int fm_eth_init(struct fm_eth *fm_eth)
334 {
335 
336 	if (!fm_eth_rx_port_parameter_init(fm_eth))
337 		return 0;
338 
339 	if (!fm_eth_tx_port_parameter_init(fm_eth))
340 		return 0;
341 
342 	return 1;
343 }
344 
345 static int fm_eth_startup(struct fm_eth *fm_eth)
346 {
347 	struct fsl_enet_mac *mac;
348 	mac = fm_eth->mac;
349 
350 	/* Rx/TxBDs, Rx/TxQDs, Rx buff and parameter ram init */
351 	if (!fm_eth_init(fm_eth))
352 		return 0;
353 	/* setup the MAC controller */
354 	mac->init_mac(mac);
355 
356 	/* For some reason we need to set SPEED_100 */
357 	if ((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) && mac->set_if_mode)
358 		mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100);
359 
360 	/* init bmi rx port, IM mode and disable */
361 	bmi_rx_port_init(fm_eth->rx_port);
362 	/* init bmi tx port, IM mode and disable */
363 	bmi_tx_port_init(fm_eth->tx_port);
364 
365 	return 1;
366 }
367 
368 static void fmc_tx_port_graceful_stop_enable(struct fm_eth *fm_eth)
369 {
370 	struct fm_port_global_pram *pram;
371 
372 	pram = fm_eth->tx_pram;
373 	/* graceful stop transmission of frames */
374 	pram->mode |= PRAM_MODE_GRACEFUL_STOP;
375 	sync();
376 }
377 
378 static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth)
379 {
380 	struct fm_port_global_pram *pram;
381 
382 	pram = fm_eth->tx_pram;
383 	/* re-enable transmission of frames */
384 	pram->mode &= ~PRAM_MODE_GRACEFUL_STOP;
385 	sync();
386 }
387 
388 static int fm_eth_open(struct eth_device *dev, bd_t *bd)
389 {
390 	struct fm_eth *fm_eth;
391 	struct fsl_enet_mac *mac;
392 #ifdef CONFIG_PHYLIB
393 	int ret;
394 #endif
395 
396 	fm_eth = (struct fm_eth *)dev->priv;
397 	mac = fm_eth->mac;
398 
399 	/* setup the MAC address */
400 	if (dev->enetaddr[0] & 0x01) {
401 		printf("%s: MacAddress is multcast address\n",	__func__);
402 		return 1;
403 	}
404 	mac->set_mac_addr(mac, dev->enetaddr);
405 
406 	/* enable bmi Rx port */
407 	setbits_be32(&fm_eth->rx_port->fmbm_rcfg, FMBM_RCFG_EN);
408 	/* enable MAC rx/tx port */
409 	mac->enable_mac(mac);
410 	/* enable bmi Tx port */
411 	setbits_be32(&fm_eth->tx_port->fmbm_tcfg, FMBM_TCFG_EN);
412 	/* re-enable transmission of frame */
413 	fmc_tx_port_graceful_stop_disable(fm_eth);
414 
415 #ifdef CONFIG_PHYLIB
416 	ret = phy_startup(fm_eth->phydev);
417 	if (ret) {
418 		printf("%s: Could not initialize\n", fm_eth->phydev->dev->name);
419 		return ret;
420 	}
421 #else
422 	fm_eth->phydev->speed = SPEED_1000;
423 	fm_eth->phydev->link = 1;
424 	fm_eth->phydev->duplex = DUPLEX_FULL;
425 #endif
426 
427 	/* set the MAC-PHY mode */
428 	mac->set_if_mode(mac, fm_eth->enet_if, fm_eth->phydev->speed);
429 
430 	if (!fm_eth->phydev->link)
431 		printf("%s: No link.\n", fm_eth->phydev->dev->name);
432 
433 	return fm_eth->phydev->link ? 0 : -1;
434 }
435 
436 static void fm_eth_halt(struct eth_device *dev)
437 {
438 	struct fm_eth *fm_eth;
439 	struct fsl_enet_mac *mac;
440 
441 	fm_eth = (struct fm_eth *)dev->priv;
442 	mac = fm_eth->mac;
443 
444 	/* graceful stop the transmission of frames */
445 	fmc_tx_port_graceful_stop_enable(fm_eth);
446 	/* disable bmi Tx port */
447 	bmi_tx_port_disable(fm_eth->tx_port);
448 	/* disable MAC rx/tx port */
449 	mac->disable_mac(mac);
450 	/* disable bmi Rx port */
451 	bmi_rx_port_disable(fm_eth->rx_port);
452 
453 	phy_shutdown(fm_eth->phydev);
454 }
455 
456 static int fm_eth_send(struct eth_device *dev, void *buf, int len)
457 {
458 	struct fm_eth *fm_eth;
459 	struct fm_port_global_pram *pram;
460 	struct fm_port_bd *txbd, *txbd_base;
461 	u16 offset_in;
462 	int i;
463 
464 	fm_eth = (struct fm_eth *)dev->priv;
465 	pram = fm_eth->tx_pram;
466 	txbd = fm_eth->cur_txbd;
467 
468 	/* find one empty TxBD */
469 	for (i = 0; txbd->status & TxBD_READY; i++) {
470 		udelay(100);
471 		if (i > 0x1000) {
472 			printf("%s: Tx buffer not ready\n", dev->name);
473 			return 0;
474 		}
475 	}
476 	/* setup TxBD */
477 	txbd->buf_ptr_hi = 0;
478 	txbd->buf_ptr_lo = (u32)buf;
479 	txbd->len = len;
480 	sync();
481 	txbd->status = TxBD_READY | TxBD_LAST;
482 	sync();
483 
484 	/* update TxQD, let RISC to send the packet */
485 	offset_in = muram_readw(&pram->txqd.offset_in);
486 	offset_in += sizeof(struct fm_port_bd);
487 	if (offset_in >= muram_readw(&pram->txqd.bd_ring_size))
488 		offset_in = 0;
489 	muram_writew(&pram->txqd.offset_in, offset_in);
490 	sync();
491 
492 	/* wait for buffer to be transmitted */
493 	for (i = 0; txbd->status & TxBD_READY; i++) {
494 		udelay(100);
495 		if (i > 0x10000) {
496 			printf("%s: Tx error\n", dev->name);
497 			return 0;
498 		}
499 	}
500 
501 	/* advance the TxBD */
502 	txbd++;
503 	txbd_base = (struct fm_port_bd *)fm_eth->tx_bd_ring;
504 	if (txbd >= (txbd_base + TX_BD_RING_SIZE))
505 		txbd = txbd_base;
506 	/* update current txbd */
507 	fm_eth->cur_txbd = (void *)txbd;
508 
509 	return 1;
510 }
511 
512 static int fm_eth_recv(struct eth_device *dev)
513 {
514 	struct fm_eth *fm_eth;
515 	struct fm_port_global_pram *pram;
516 	struct fm_port_bd *rxbd, *rxbd_base;
517 	u16 status, len;
518 	u8 *data;
519 	u16 offset_out;
520 
521 	fm_eth = (struct fm_eth *)dev->priv;
522 	pram = fm_eth->rx_pram;
523 	rxbd = fm_eth->cur_rxbd;
524 	status = rxbd->status;
525 
526 	while (!(status & RxBD_EMPTY)) {
527 		if (!(status & RxBD_ERROR)) {
528 			data = (u8 *)rxbd->buf_ptr_lo;
529 			len = rxbd->len;
530 			NetReceive(data, len);
531 		} else {
532 			printf("%s: Rx error\n", dev->name);
533 			return 0;
534 		}
535 
536 		/* clear the RxBDs */
537 		rxbd->status = RxBD_EMPTY;
538 		rxbd->len = 0;
539 		sync();
540 
541 		/* advance RxBD */
542 		rxbd++;
543 		rxbd_base = (struct fm_port_bd *)fm_eth->rx_bd_ring;
544 		if (rxbd >= (rxbd_base + RX_BD_RING_SIZE))
545 			rxbd = rxbd_base;
546 		/* read next status */
547 		status = rxbd->status;
548 
549 		/* update RxQD */
550 		offset_out = muram_readw(&pram->rxqd.offset_out);
551 		offset_out += sizeof(struct fm_port_bd);
552 		if (offset_out >= muram_readw(&pram->rxqd.bd_ring_size))
553 			offset_out = 0;
554 		muram_writew(&pram->rxqd.offset_out, offset_out);
555 		sync();
556 	}
557 	fm_eth->cur_rxbd = (void *)rxbd;
558 
559 	return 1;
560 }
561 
562 static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
563 {
564 	struct fsl_enet_mac *mac;
565 	int num;
566 	void *base, *phyregs = NULL;
567 
568 	num = fm_eth->num;
569 
570 #ifdef CONFIG_SYS_FMAN_V3
571 	base = &reg->memac[num].fm_memac;
572 	phyregs = &reg->memac[num].fm_memac_mdio;
573 #else
574 	/* Get the mac registers base address */
575 	if (fm_eth->type == FM_ETH_1G_E) {
576 		base = &reg->mac_1g[num].fm_dtesc;
577 		phyregs = &reg->mac_1g[num].fm_mdio.miimcfg;
578 	} else {
579 		base = &reg->mac_10g[num].fm_10gec;
580 		phyregs = &reg->mac_10g[num].fm_10gec_mdio;
581 	}
582 #endif
583 
584 	/* alloc mac controller */
585 	mac = malloc(sizeof(struct fsl_enet_mac));
586 	if (!mac)
587 		return 0;
588 	memset(mac, 0, sizeof(struct fsl_enet_mac));
589 
590 	/* save the mac to fm_eth struct */
591 	fm_eth->mac = mac;
592 
593 #ifdef CONFIG_SYS_FMAN_V3
594 	init_memac(mac, base, phyregs, MAX_RXBUF_LEN);
595 #else
596 	if (fm_eth->type == FM_ETH_1G_E)
597 		init_dtsec(mac, base, phyregs, MAX_RXBUF_LEN);
598 	else
599 		init_tgec(mac, base, phyregs, MAX_RXBUF_LEN);
600 #endif
601 
602 	return 1;
603 }
604 
605 static int init_phy(struct eth_device *dev)
606 {
607 	struct fm_eth *fm_eth = dev->priv;
608 	struct phy_device *phydev = NULL;
609 	u32 supported;
610 
611 #ifdef CONFIG_PHYLIB
612 	if (fm_eth->type == FM_ETH_1G_E)
613 		dtsec_init_phy(dev);
614 
615 	if (fm_eth->bus) {
616 		phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, dev,
617 					fm_eth->enet_if);
618 	}
619 
620 	if (!phydev) {
621 		printf("Failed to connect\n");
622 		return -1;
623 	}
624 
625 	if (fm_eth->type == FM_ETH_1G_E) {
626 		supported = (SUPPORTED_10baseT_Half |
627 				SUPPORTED_10baseT_Full |
628 				SUPPORTED_100baseT_Half |
629 				SUPPORTED_100baseT_Full |
630 				SUPPORTED_1000baseT_Full);
631 	} else {
632 		supported = SUPPORTED_10000baseT_Full;
633 
634 		if (tgec_is_fibre(dev))
635 			phydev->port = PORT_FIBRE;
636 	}
637 
638 	phydev->supported &= supported;
639 	phydev->advertising = phydev->supported;
640 
641 	fm_eth->phydev = phydev;
642 
643 	phy_config(phydev);
644 #endif
645 
646 	return 0;
647 }
648 
649 int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
650 {
651 	struct eth_device *dev;
652 	struct fm_eth *fm_eth;
653 	int i, num = info->num;
654 
655 	/* alloc eth device */
656 	dev = (struct eth_device *)malloc(sizeof(struct eth_device));
657 	if (!dev)
658 		return 0;
659 	memset(dev, 0, sizeof(struct eth_device));
660 
661 	/* alloc the FMan ethernet private struct */
662 	fm_eth = (struct fm_eth *)malloc(sizeof(struct fm_eth));
663 	if (!fm_eth)
664 		return 0;
665 	memset(fm_eth, 0, sizeof(struct fm_eth));
666 
667 	/* save off some things we need from the info struct */
668 	fm_eth->fm_index = info->index - 1; /* keep as 0 based for muram */
669 	fm_eth->num = num;
670 	fm_eth->type = info->type;
671 
672 	fm_eth->rx_port = (void *)&reg->port[info->rx_port_id - 1].fm_bmi;
673 	fm_eth->tx_port = (void *)&reg->port[info->tx_port_id - 1].fm_bmi;
674 
675 	/* set the ethernet max receive length */
676 	fm_eth->max_rx_len = MAX_RXBUF_LEN;
677 
678 	/* init global mac structure */
679 	if (!fm_eth_init_mac(fm_eth, reg))
680 		return 0;
681 
682 	/* keep same as the manual, we call FMAN1, FMAN2, DTSEC1, DTSEC2, etc */
683 	if (fm_eth->type == FM_ETH_1G_E)
684 		sprintf(dev->name, "FM%d@DTSEC%d", info->index, num + 1);
685 	else
686 		sprintf(dev->name, "FM%d@TGEC%d", info->index, num + 1);
687 
688 	devlist[num_controllers++] = dev;
689 	dev->iobase = 0;
690 	dev->priv = (void *)fm_eth;
691 	dev->init = fm_eth_open;
692 	dev->halt = fm_eth_halt;
693 	dev->send = fm_eth_send;
694 	dev->recv = fm_eth_recv;
695 	fm_eth->dev = dev;
696 	fm_eth->bus = info->bus;
697 	fm_eth->phyaddr = info->phy_addr;
698 	fm_eth->enet_if = info->enet_if;
699 
700 	/* startup the FM im */
701 	if (!fm_eth_startup(fm_eth))
702 		return 0;
703 
704 	if (init_phy(dev))
705 		return 0;
706 
707 	/* clear the ethernet address */
708 	for (i = 0; i < 6; i++)
709 		dev->enetaddr[i] = 0;
710 	eth_register(dev);
711 
712 	return 1;
713 }
714