1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * Dave Liu <daveliu@freescale.com> 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 of 8 * the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 18 * MA 02111-1307 USA 19 */ 20 #include <common.h> 21 #include <asm/io.h> 22 #include <malloc.h> 23 #include <net.h> 24 #include <hwconfig.h> 25 #include <fm_eth.h> 26 #include <fsl_mdio.h> 27 #include <miiphy.h> 28 #include <phy.h> 29 #include <asm/fsl_dtsec.h> 30 #include <asm/fsl_tgec.h> 31 32 #include "fm.h" 33 34 static struct eth_device *devlist[NUM_FM_PORTS]; 35 static int num_controllers; 36 37 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII) 38 39 #define TBIANA_SETTINGS (TBIANA_ASYMMETRIC_PAUSE | TBIANA_SYMMETRIC_PAUSE | \ 40 TBIANA_FULL_DUPLEX) 41 42 #define TBIANA_SGMII_ACK 0x4001 43 44 #define TBICR_SETTINGS (TBICR_ANEG_ENABLE | TBICR_RESTART_ANEG | \ 45 TBICR_FULL_DUPLEX | TBICR_SPEED1_SET) 46 47 /* Configure the TBI for SGMII operation */ 48 void dtsec_configure_serdes(struct fm_eth *priv) 49 { 50 struct dtsec *regs = priv->mac->base; 51 struct tsec_mii_mng *phyregs = priv->mac->phyregs; 52 53 /* 54 * Access TBI PHY registers at given TSEC register offset as 55 * opposed to the register offset used for external PHY accesses 56 */ 57 tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0, TBI_TBICON, 58 TBICON_CLK_SELECT); 59 tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0, TBI_ANA, 60 TBIANA_SGMII_ACK); 61 tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0, 62 TBI_CR, TBICR_SETTINGS); 63 } 64 65 static void dtsec_init_phy(struct eth_device *dev) 66 { 67 struct fm_eth *fm_eth = dev->priv; 68 struct dtsec *regs = (struct dtsec *)fm_eth->mac->base; 69 70 /* Assign a Physical address to the TBI */ 71 out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE); 72 73 if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) 74 dtsec_configure_serdes(fm_eth); 75 } 76 77 static int tgec_is_fibre(struct eth_device *dev) 78 { 79 struct fm_eth *fm = dev->priv; 80 char phyopt[20]; 81 82 sprintf(phyopt, "fsl_fm%d_xaui_phy", fm->fm_index + 1); 83 84 return hwconfig_arg_cmp(phyopt, "xfi"); 85 } 86 #endif 87 88 static u16 muram_readw(u16 *addr) 89 { 90 u32 base = (u32)addr & ~0x3; 91 u32 val32 = *(u32 *)base; 92 int byte_pos; 93 u16 ret; 94 95 byte_pos = (u32)addr & 0x3; 96 if (byte_pos) 97 ret = (u16)(val32 & 0x0000ffff); 98 else 99 ret = (u16)((val32 & 0xffff0000) >> 16); 100 101 return ret; 102 } 103 104 static void muram_writew(u16 *addr, u16 val) 105 { 106 u32 base = (u32)addr & ~0x3; 107 u32 org32 = *(u32 *)base; 108 u32 val32; 109 int byte_pos; 110 111 byte_pos = (u32)addr & 0x3; 112 if (byte_pos) 113 val32 = (org32 & 0xffff0000) | val; 114 else 115 val32 = (org32 & 0x0000ffff) | ((u32)val << 16); 116 117 *(u32 *)base = val32; 118 } 119 120 static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port) 121 { 122 int timeout = 1000000; 123 124 clrbits_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_EN); 125 126 /* wait until the rx port is not busy */ 127 while ((in_be32(&rx_port->fmbm_rst) & FMBM_RST_BSY) && timeout--) 128 ; 129 } 130 131 static void bmi_rx_port_init(struct fm_bmi_rx_port *rx_port) 132 { 133 /* set BMI to independent mode, Rx port disable */ 134 out_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_IM); 135 /* clear FOF in IM case */ 136 out_be32(&rx_port->fmbm_rim, 0); 137 /* Rx frame next engine -RISC */ 138 out_be32(&rx_port->fmbm_rfne, NIA_ENG_RISC | NIA_RISC_AC_IM_RX); 139 /* Rx command attribute - no order, MR[3] = 1 */ 140 clrbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_ORDER | FMBM_RFCA_MR_MASK); 141 setbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_MR(4)); 142 /* enable Rx statistic counters */ 143 out_be32(&rx_port->fmbm_rstc, FMBM_RSTC_EN); 144 /* disable Rx performance counters */ 145 out_be32(&rx_port->fmbm_rpc, 0); 146 } 147 148 static void bmi_tx_port_disable(struct fm_bmi_tx_port *tx_port) 149 { 150 int timeout = 1000000; 151 152 clrbits_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_EN); 153 154 /* wait until the tx port is not busy */ 155 while ((in_be32(&tx_port->fmbm_tst) & FMBM_TST_BSY) && timeout--) 156 ; 157 } 158 159 static void bmi_tx_port_init(struct fm_bmi_tx_port *tx_port) 160 { 161 /* set BMI to independent mode, Tx port disable */ 162 out_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_IM); 163 /* Tx frame next engine -RISC */ 164 out_be32(&tx_port->fmbm_tfne, NIA_ENG_RISC | NIA_RISC_AC_IM_TX); 165 out_be32(&tx_port->fmbm_tfene, NIA_ENG_RISC | NIA_RISC_AC_IM_TX); 166 /* Tx command attribute - no order, MR[3] = 1 */ 167 clrbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_ORDER | FMBM_TFCA_MR_MASK); 168 setbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_MR(4)); 169 /* enable Tx statistic counters */ 170 out_be32(&tx_port->fmbm_tstc, FMBM_TSTC_EN); 171 /* disable Tx performance counters */ 172 out_be32(&tx_port->fmbm_tpc, 0); 173 } 174 175 static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth) 176 { 177 struct fm_port_global_pram *pram; 178 u32 pram_page_offset; 179 void *rx_bd_ring_base; 180 void *rx_buf_pool; 181 struct fm_port_bd *rxbd; 182 struct fm_port_qd *rxqd; 183 struct fm_bmi_rx_port *bmi_rx_port = fm_eth->rx_port; 184 int i; 185 186 /* alloc global parameter ram at MURAM */ 187 pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index, 188 FM_PRAM_SIZE, FM_PRAM_ALIGN); 189 fm_eth->rx_pram = pram; 190 191 /* parameter page offset to MURAM */ 192 pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index); 193 194 /* enable global mode- snooping data buffers and BDs */ 195 pram->mode = PRAM_MODE_GLOBAL; 196 197 /* init the Rx queue descriptor pionter */ 198 pram->rxqd_ptr = pram_page_offset + 0x20; 199 200 /* set the max receive buffer length, power of 2 */ 201 muram_writew(&pram->mrblr, MAX_RXBUF_LOG2); 202 203 /* alloc Rx buffer descriptors from main memory */ 204 rx_bd_ring_base = malloc(sizeof(struct fm_port_bd) 205 * RX_BD_RING_SIZE); 206 if (!rx_bd_ring_base) 207 return 0; 208 memset(rx_bd_ring_base, 0, sizeof(struct fm_port_bd) 209 * RX_BD_RING_SIZE); 210 211 /* alloc Rx buffer from main memory */ 212 rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE); 213 if (!rx_buf_pool) 214 return 0; 215 memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE); 216 217 /* save them to fm_eth */ 218 fm_eth->rx_bd_ring = rx_bd_ring_base; 219 fm_eth->cur_rxbd = rx_bd_ring_base; 220 fm_eth->rx_buf = rx_buf_pool; 221 222 /* init Rx BDs ring */ 223 rxbd = (struct fm_port_bd *)rx_bd_ring_base; 224 for (i = 0; i < RX_BD_RING_SIZE; i++) { 225 rxbd->status = RxBD_EMPTY; 226 rxbd->len = 0; 227 rxbd->buf_ptr_hi = 0; 228 rxbd->buf_ptr_lo = (u32)rx_buf_pool + i * MAX_RXBUF_LEN; 229 rxbd++; 230 } 231 232 /* set the Rx queue descriptor */ 233 rxqd = &pram->rxqd; 234 muram_writew(&rxqd->gen, 0); 235 muram_writew(&rxqd->bd_ring_base_hi, 0); 236 rxqd->bd_ring_base_lo = (u32)rx_bd_ring_base; 237 muram_writew(&rxqd->bd_ring_size, sizeof(struct fm_port_bd) 238 * RX_BD_RING_SIZE); 239 muram_writew(&rxqd->offset_in, 0); 240 muram_writew(&rxqd->offset_out, 0); 241 242 /* set IM parameter ram pointer to Rx Frame Queue ID */ 243 out_be32(&bmi_rx_port->fmbm_rfqid, pram_page_offset); 244 245 return 1; 246 } 247 248 static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth) 249 { 250 struct fm_port_global_pram *pram; 251 u32 pram_page_offset; 252 void *tx_bd_ring_base; 253 struct fm_port_bd *txbd; 254 struct fm_port_qd *txqd; 255 struct fm_bmi_tx_port *bmi_tx_port = fm_eth->tx_port; 256 int i; 257 258 /* alloc global parameter ram at MURAM */ 259 pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index, 260 FM_PRAM_SIZE, FM_PRAM_ALIGN); 261 fm_eth->tx_pram = pram; 262 263 /* parameter page offset to MURAM */ 264 pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index); 265 266 /* enable global mode- snooping data buffers and BDs */ 267 pram->mode = PRAM_MODE_GLOBAL; 268 269 /* init the Tx queue descriptor pionter */ 270 pram->txqd_ptr = pram_page_offset + 0x40; 271 272 /* alloc Tx buffer descriptors from main memory */ 273 tx_bd_ring_base = malloc(sizeof(struct fm_port_bd) 274 * TX_BD_RING_SIZE); 275 if (!tx_bd_ring_base) 276 return 0; 277 memset(tx_bd_ring_base, 0, sizeof(struct fm_port_bd) 278 * TX_BD_RING_SIZE); 279 /* save it to fm_eth */ 280 fm_eth->tx_bd_ring = tx_bd_ring_base; 281 fm_eth->cur_txbd = tx_bd_ring_base; 282 283 /* init Tx BDs ring */ 284 txbd = (struct fm_port_bd *)tx_bd_ring_base; 285 for (i = 0; i < TX_BD_RING_SIZE; i++) { 286 txbd->status = TxBD_LAST; 287 txbd->len = 0; 288 txbd->buf_ptr_hi = 0; 289 txbd->buf_ptr_lo = 0; 290 } 291 292 /* set the Tx queue decriptor */ 293 txqd = &pram->txqd; 294 muram_writew(&txqd->bd_ring_base_hi, 0); 295 txqd->bd_ring_base_lo = (u32)tx_bd_ring_base; 296 muram_writew(&txqd->bd_ring_size, sizeof(struct fm_port_bd) 297 * TX_BD_RING_SIZE); 298 muram_writew(&txqd->offset_in, 0); 299 muram_writew(&txqd->offset_out, 0); 300 301 /* set IM parameter ram pointer to Tx Confirmation Frame Queue ID */ 302 out_be32(&bmi_tx_port->fmbm_tcfqid, pram_page_offset); 303 304 return 1; 305 } 306 307 static int fm_eth_init(struct fm_eth *fm_eth) 308 { 309 310 if (!fm_eth_rx_port_parameter_init(fm_eth)) 311 return 0; 312 313 if (!fm_eth_tx_port_parameter_init(fm_eth)) 314 return 0; 315 316 return 1; 317 } 318 319 static int fm_eth_startup(struct fm_eth *fm_eth) 320 { 321 struct fsl_enet_mac *mac; 322 mac = fm_eth->mac; 323 324 /* Rx/TxBDs, Rx/TxQDs, Rx buff and parameter ram init */ 325 if (!fm_eth_init(fm_eth)) 326 return 0; 327 /* setup the MAC controller */ 328 mac->init_mac(mac); 329 330 /* For some reason we need to set SPEED_100 */ 331 if ((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) && mac->set_if_mode) 332 mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100); 333 334 /* init bmi rx port, IM mode and disable */ 335 bmi_rx_port_init(fm_eth->rx_port); 336 /* init bmi tx port, IM mode and disable */ 337 bmi_tx_port_init(fm_eth->tx_port); 338 339 return 1; 340 } 341 342 static void fmc_tx_port_graceful_stop_enable(struct fm_eth *fm_eth) 343 { 344 struct fm_port_global_pram *pram; 345 346 pram = fm_eth->tx_pram; 347 /* graceful stop transmission of frames */ 348 pram->mode |= PRAM_MODE_GRACEFUL_STOP; 349 sync(); 350 } 351 352 static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth) 353 { 354 struct fm_port_global_pram *pram; 355 356 pram = fm_eth->tx_pram; 357 /* re-enable transmission of frames */ 358 pram->mode &= ~PRAM_MODE_GRACEFUL_STOP; 359 sync(); 360 } 361 362 static int fm_eth_open(struct eth_device *dev, bd_t *bd) 363 { 364 struct fm_eth *fm_eth; 365 struct fsl_enet_mac *mac; 366 #ifdef CONFIG_PHYLIB 367 int ret; 368 #endif 369 370 fm_eth = (struct fm_eth *)dev->priv; 371 mac = fm_eth->mac; 372 373 /* setup the MAC address */ 374 if (dev->enetaddr[0] & 0x01) { 375 printf("%s: MacAddress is multcast address\n", __func__); 376 return 1; 377 } 378 mac->set_mac_addr(mac, dev->enetaddr); 379 380 /* enable bmi Rx port */ 381 setbits_be32(&fm_eth->rx_port->fmbm_rcfg, FMBM_RCFG_EN); 382 /* enable MAC rx/tx port */ 383 mac->enable_mac(mac); 384 /* enable bmi Tx port */ 385 setbits_be32(&fm_eth->tx_port->fmbm_tcfg, FMBM_TCFG_EN); 386 /* re-enable transmission of frame */ 387 fmc_tx_port_graceful_stop_disable(fm_eth); 388 389 #ifdef CONFIG_PHYLIB 390 ret = phy_startup(fm_eth->phydev); 391 if (ret) { 392 printf("%s: Could not initialize\n", fm_eth->phydev->dev->name); 393 return ret; 394 } 395 #else 396 fm_eth->phydev->speed = SPEED_1000; 397 fm_eth->phydev->link = 1; 398 fm_eth->phydev->duplex = DUPLEX_FULL; 399 #endif 400 401 /* set the MAC-PHY mode */ 402 mac->set_if_mode(mac, fm_eth->enet_if, fm_eth->phydev->speed); 403 404 if (!fm_eth->phydev->link) 405 printf("%s: No link.\n", fm_eth->phydev->dev->name); 406 407 return fm_eth->phydev->link ? 0 : -1; 408 } 409 410 static void fm_eth_halt(struct eth_device *dev) 411 { 412 struct fm_eth *fm_eth; 413 struct fsl_enet_mac *mac; 414 415 fm_eth = (struct fm_eth *)dev->priv; 416 mac = fm_eth->mac; 417 418 /* graceful stop the transmission of frames */ 419 fmc_tx_port_graceful_stop_enable(fm_eth); 420 /* disable bmi Tx port */ 421 bmi_tx_port_disable(fm_eth->tx_port); 422 /* disable MAC rx/tx port */ 423 mac->disable_mac(mac); 424 /* disable bmi Rx port */ 425 bmi_rx_port_disable(fm_eth->rx_port); 426 427 phy_shutdown(fm_eth->phydev); 428 } 429 430 static int fm_eth_send(struct eth_device *dev, void *buf, int len) 431 { 432 struct fm_eth *fm_eth; 433 struct fm_port_global_pram *pram; 434 struct fm_port_bd *txbd, *txbd_base; 435 u16 offset_in; 436 int i; 437 438 fm_eth = (struct fm_eth *)dev->priv; 439 pram = fm_eth->tx_pram; 440 txbd = fm_eth->cur_txbd; 441 442 /* find one empty TxBD */ 443 for (i = 0; txbd->status & TxBD_READY; i++) { 444 udelay(100); 445 if (i > 0x1000) { 446 printf("%s: Tx buffer not ready\n", dev->name); 447 return 0; 448 } 449 } 450 /* setup TxBD */ 451 txbd->buf_ptr_hi = 0; 452 txbd->buf_ptr_lo = (u32)buf; 453 txbd->len = len; 454 sync(); 455 txbd->status = TxBD_READY | TxBD_LAST; 456 sync(); 457 458 /* update TxQD, let RISC to send the packet */ 459 offset_in = muram_readw(&pram->txqd.offset_in); 460 offset_in += sizeof(struct fm_port_bd); 461 if (offset_in >= muram_readw(&pram->txqd.bd_ring_size)) 462 offset_in = 0; 463 muram_writew(&pram->txqd.offset_in, offset_in); 464 sync(); 465 466 /* wait for buffer to be transmitted */ 467 for (i = 0; txbd->status & TxBD_READY; i++) { 468 udelay(100); 469 if (i > 0x10000) { 470 printf("%s: Tx error\n", dev->name); 471 return 0; 472 } 473 } 474 475 /* advance the TxBD */ 476 txbd++; 477 txbd_base = (struct fm_port_bd *)fm_eth->tx_bd_ring; 478 if (txbd >= (txbd_base + TX_BD_RING_SIZE)) 479 txbd = txbd_base; 480 /* update current txbd */ 481 fm_eth->cur_txbd = (void *)txbd; 482 483 return 1; 484 } 485 486 static int fm_eth_recv(struct eth_device *dev) 487 { 488 struct fm_eth *fm_eth; 489 struct fm_port_global_pram *pram; 490 struct fm_port_bd *rxbd, *rxbd_base; 491 u16 status, len; 492 u8 *data; 493 u16 offset_out; 494 495 fm_eth = (struct fm_eth *)dev->priv; 496 pram = fm_eth->rx_pram; 497 rxbd = fm_eth->cur_rxbd; 498 status = rxbd->status; 499 500 while (!(status & RxBD_EMPTY)) { 501 if (!(status & RxBD_ERROR)) { 502 data = (u8 *)rxbd->buf_ptr_lo; 503 len = rxbd->len; 504 NetReceive(data, len); 505 } else { 506 printf("%s: Rx error\n", dev->name); 507 return 0; 508 } 509 510 /* clear the RxBDs */ 511 rxbd->status = RxBD_EMPTY; 512 rxbd->len = 0; 513 sync(); 514 515 /* advance RxBD */ 516 rxbd++; 517 rxbd_base = (struct fm_port_bd *)fm_eth->rx_bd_ring; 518 if (rxbd >= (rxbd_base + RX_BD_RING_SIZE)) 519 rxbd = rxbd_base; 520 /* read next status */ 521 status = rxbd->status; 522 523 /* update RxQD */ 524 offset_out = muram_readw(&pram->rxqd.offset_out); 525 offset_out += sizeof(struct fm_port_bd); 526 if (offset_out >= muram_readw(&pram->rxqd.bd_ring_size)) 527 offset_out = 0; 528 muram_writew(&pram->rxqd.offset_out, offset_out); 529 sync(); 530 } 531 fm_eth->cur_rxbd = (void *)rxbd; 532 533 return 1; 534 } 535 536 static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg) 537 { 538 struct fsl_enet_mac *mac; 539 int num; 540 void *base, *phyregs = NULL; 541 542 num = fm_eth->num; 543 544 /* Get the mac registers base address */ 545 if (fm_eth->type == FM_ETH_1G_E) { 546 base = ®->mac_1g[num].fm_dtesc; 547 phyregs = ®->mac_1g[num].fm_mdio.miimcfg; 548 } else { 549 base = ®->mac_10g[num].fm_10gec; 550 phyregs = ®->mac_10g[num].fm_10gec_mdio; 551 } 552 553 /* alloc mac controller */ 554 mac = malloc(sizeof(struct fsl_enet_mac)); 555 if (!mac) 556 return 0; 557 memset(mac, 0, sizeof(struct fsl_enet_mac)); 558 559 /* save the mac to fm_eth struct */ 560 fm_eth->mac = mac; 561 562 if (fm_eth->type == FM_ETH_1G_E) 563 init_dtsec(mac, base, phyregs, MAX_RXBUF_LEN); 564 else 565 init_tgec(mac, base, phyregs, MAX_RXBUF_LEN); 566 567 return 1; 568 } 569 570 static int init_phy(struct eth_device *dev) 571 { 572 struct fm_eth *fm_eth = dev->priv; 573 struct phy_device *phydev = NULL; 574 u32 supported; 575 576 #ifdef CONFIG_PHYLIB 577 if (fm_eth->type == FM_ETH_1G_E) 578 dtsec_init_phy(dev); 579 580 if (fm_eth->bus) { 581 phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, dev, 582 fm_eth->enet_if); 583 } 584 585 if (!phydev) { 586 printf("Failed to connect\n"); 587 return -1; 588 } 589 590 if (fm_eth->type == FM_ETH_1G_E) { 591 supported = (SUPPORTED_10baseT_Half | 592 SUPPORTED_10baseT_Full | 593 SUPPORTED_100baseT_Half | 594 SUPPORTED_100baseT_Full | 595 SUPPORTED_1000baseT_Full); 596 } else { 597 supported = SUPPORTED_10000baseT_Full; 598 599 if (tgec_is_fibre(dev)) 600 phydev->port = PORT_FIBRE; 601 } 602 603 phydev->supported &= supported; 604 phydev->advertising = phydev->supported; 605 606 fm_eth->phydev = phydev; 607 608 phy_config(phydev); 609 #endif 610 611 return 0; 612 } 613 614 int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info) 615 { 616 struct eth_device *dev; 617 struct fm_eth *fm_eth; 618 int i, num = info->num; 619 620 /* alloc eth device */ 621 dev = (struct eth_device *)malloc(sizeof(struct eth_device)); 622 if (!dev) 623 return 0; 624 memset(dev, 0, sizeof(struct eth_device)); 625 626 /* alloc the FMan ethernet private struct */ 627 fm_eth = (struct fm_eth *)malloc(sizeof(struct fm_eth)); 628 if (!fm_eth) 629 return 0; 630 memset(fm_eth, 0, sizeof(struct fm_eth)); 631 632 /* save off some things we need from the info struct */ 633 fm_eth->fm_index = info->index - 1; /* keep as 0 based for muram */ 634 fm_eth->num = num; 635 fm_eth->type = info->type; 636 637 fm_eth->rx_port = (void *)®->port[info->rx_port_id - 1].fm_bmi; 638 fm_eth->tx_port = (void *)®->port[info->tx_port_id - 1].fm_bmi; 639 640 /* set the ethernet max receive length */ 641 fm_eth->max_rx_len = MAX_RXBUF_LEN; 642 643 /* init global mac structure */ 644 if (!fm_eth_init_mac(fm_eth, reg)) 645 return 0; 646 647 /* keep same as the manual, we call FMAN1, FMAN2, DTSEC1, DTSEC2, etc */ 648 if (fm_eth->type == FM_ETH_1G_E) 649 sprintf(dev->name, "FM%d@DTSEC%d", info->index, num + 1); 650 else 651 sprintf(dev->name, "FM%d@TGEC%d", info->index, num + 1); 652 653 devlist[num_controllers++] = dev; 654 dev->iobase = 0; 655 dev->priv = (void *)fm_eth; 656 dev->init = fm_eth_open; 657 dev->halt = fm_eth_halt; 658 dev->send = fm_eth_send; 659 dev->recv = fm_eth_recv; 660 fm_eth->dev = dev; 661 fm_eth->bus = info->bus; 662 fm_eth->phyaddr = info->phy_addr; 663 fm_eth->enet_if = info->enet_if; 664 665 /* startup the FM im */ 666 if (!fm_eth_startup(fm_eth)) 667 return 0; 668 669 if (init_phy(dev)) 670 return 0; 671 672 /* clear the ethernet address */ 673 for (i = 0; i < 6; i++) 674 dev->enetaddr[i] = 0; 675 eth_register(dev); 676 677 return 1; 678 } 679