1 /* 2 * Copyright 2012 Freescale Semiconductor, Inc. 3 * Roy Zang <tie-fei.zang@freescale.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 #include <common.h> 8 #include <phy.h> 9 #include <fm_eth.h> 10 #include <asm/io.h> 11 #include <asm/immap_85xx.h> 12 #include <asm/fsl_serdes.h> 13 14 u32 port_to_devdisr[] = { 15 [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, 16 [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, 17 [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, 18 [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, 19 [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5, 20 [FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6, 21 [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1, 22 [FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2, 23 }; 24 25 static int is_device_disabled(enum fm_port port) 26 { 27 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 28 u32 devdisr2 = in_be32(&gur->devdisr2); 29 30 return port_to_devdisr[port] & devdisr2; 31 } 32 33 void fman_disable_port(enum fm_port port) 34 { 35 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 36 37 setbits_be32(&gur->devdisr2, port_to_devdisr[port]); 38 } 39 40 void fman_enable_port(enum fm_port port) 41 { 42 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 43 44 clrbits_be32(&gur->devdisr2, port_to_devdisr[port]); 45 } 46 47 phy_interface_t fman_port_enet_if(enum fm_port port) 48 { 49 if (is_device_disabled(port)) 50 return PHY_INTERFACE_MODE_NONE; 51 52 /*B4860 has two 10Gig Mac*/ 53 if ((port == FM1_10GEC1 || port == FM1_10GEC2) && 54 ((is_serdes_configured(XAUI_FM1_MAC9)) || 55 (is_serdes_configured(XAUI_FM1_MAC10)))) 56 return PHY_INTERFACE_MODE_XGMII; 57 58 /* Fix me need to handle RGMII here first */ 59 60 switch (port) { 61 case FM1_DTSEC1: 62 case FM1_DTSEC2: 63 case FM1_DTSEC3: 64 case FM1_DTSEC4: 65 case FM1_DTSEC5: 66 case FM1_DTSEC6: 67 if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) 68 return PHY_INTERFACE_MODE_SGMII; 69 break; 70 default: 71 return PHY_INTERFACE_MODE_NONE; 72 } 73 74 return PHY_INTERFACE_MODE_NONE; 75 } 76