1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com> 4 * (C) Copyright 2008 Armadeus Systems, nc 5 * (C) Copyright 2008 Eric Jarrige <eric.jarrige@armadeus.org> 6 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 7 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de> 8 * 9 * (C) Copyright 2003 10 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 11 * 12 * This file is based on mpc4200fec.h 13 * (C) Copyright Motorola, Inc., 2000 14 */ 15 16 #ifndef __FEC_MXC_H 17 #define __FEC_MXC_H 18 19 /* Layout description of the FEC */ 20 struct ethernet_regs { 21 /* [10:2]addr = 00 */ 22 23 /* Control and status Registers (offset 000-1FF) */ 24 uint32_t res0[1]; /* MBAR_ETH + 0x000 */ 25 uint32_t ievent; /* MBAR_ETH + 0x004 */ 26 uint32_t imask; /* MBAR_ETH + 0x008 */ 27 28 uint32_t res1[1]; /* MBAR_ETH + 0x00C */ 29 uint32_t r_des_active; /* MBAR_ETH + 0x010 */ 30 uint32_t x_des_active; /* MBAR_ETH + 0x014 */ 31 uint32_t res2[3]; /* MBAR_ETH + 0x018-20 */ 32 uint32_t ecntrl; /* MBAR_ETH + 0x024 */ 33 34 uint32_t res3[6]; /* MBAR_ETH + 0x028-03C */ 35 uint32_t mii_data; /* MBAR_ETH + 0x040 */ 36 uint32_t mii_speed; /* MBAR_ETH + 0x044 */ 37 uint32_t res4[7]; /* MBAR_ETH + 0x048-60 */ 38 uint32_t mib_control; /* MBAR_ETH + 0x064 */ 39 40 uint32_t res5[7]; /* MBAR_ETH + 0x068-80 */ 41 uint32_t r_cntrl; /* MBAR_ETH + 0x084 */ 42 uint32_t res6[15]; /* MBAR_ETH + 0x088-C0 */ 43 uint32_t x_cntrl; /* MBAR_ETH + 0x0C4 */ 44 uint32_t res7[7]; /* MBAR_ETH + 0x0C8-E0 */ 45 uint32_t paddr1; /* MBAR_ETH + 0x0E4 */ 46 uint32_t paddr2; /* MBAR_ETH + 0x0E8 */ 47 uint32_t op_pause; /* MBAR_ETH + 0x0EC */ 48 49 uint32_t res8[10]; /* MBAR_ETH + 0x0F0-114 */ 50 uint32_t iaddr1; /* MBAR_ETH + 0x118 */ 51 uint32_t iaddr2; /* MBAR_ETH + 0x11C */ 52 uint32_t gaddr1; /* MBAR_ETH + 0x120 */ 53 uint32_t gaddr2; /* MBAR_ETH + 0x124 */ 54 uint32_t res9[7]; /* MBAR_ETH + 0x128-140 */ 55 56 uint32_t x_wmrk; /* MBAR_ETH + 0x144 */ 57 uint32_t res10[1]; /* MBAR_ETH + 0x148 */ 58 uint32_t r_bound; /* MBAR_ETH + 0x14C */ 59 uint32_t r_fstart; /* MBAR_ETH + 0x150 */ 60 uint32_t res11[11]; /* MBAR_ETH + 0x154-17C */ 61 uint32_t erdsr; /* MBAR_ETH + 0x180 */ 62 uint32_t etdsr; /* MBAR_ETH + 0x184 */ 63 uint32_t emrbr; /* MBAR_ETH + 0x188 */ 64 uint32_t res12[29]; /* MBAR_ETH + 0x18C-1FC */ 65 66 /* MIB COUNTERS (Offset 200-2FF) */ 67 uint32_t rmon_t_drop; /* MBAR_ETH + 0x200 */ 68 uint32_t rmon_t_packets; /* MBAR_ETH + 0x204 */ 69 uint32_t rmon_t_bc_pkt; /* MBAR_ETH + 0x208 */ 70 uint32_t rmon_t_mc_pkt; /* MBAR_ETH + 0x20C */ 71 uint32_t rmon_t_crc_align; /* MBAR_ETH + 0x210 */ 72 uint32_t rmon_t_undersize; /* MBAR_ETH + 0x214 */ 73 uint32_t rmon_t_oversize; /* MBAR_ETH + 0x218 */ 74 uint32_t rmon_t_frag; /* MBAR_ETH + 0x21C */ 75 uint32_t rmon_t_jab; /* MBAR_ETH + 0x220 */ 76 uint32_t rmon_t_col; /* MBAR_ETH + 0x224 */ 77 uint32_t rmon_t_p64; /* MBAR_ETH + 0x228 */ 78 uint32_t rmon_t_p65to127; /* MBAR_ETH + 0x22C */ 79 uint32_t rmon_t_p128to255; /* MBAR_ETH + 0x230 */ 80 uint32_t rmon_t_p256to511; /* MBAR_ETH + 0x234 */ 81 uint32_t rmon_t_p512to1023; /* MBAR_ETH + 0x238 */ 82 uint32_t rmon_t_p1024to2047; /* MBAR_ETH + 0x23C */ 83 uint32_t rmon_t_p_gte2048; /* MBAR_ETH + 0x240 */ 84 uint32_t rmon_t_octets; /* MBAR_ETH + 0x244 */ 85 uint32_t ieee_t_drop; /* MBAR_ETH + 0x248 */ 86 uint32_t ieee_t_frame_ok; /* MBAR_ETH + 0x24C */ 87 uint32_t ieee_t_1col; /* MBAR_ETH + 0x250 */ 88 uint32_t ieee_t_mcol; /* MBAR_ETH + 0x254 */ 89 uint32_t ieee_t_def; /* MBAR_ETH + 0x258 */ 90 uint32_t ieee_t_lcol; /* MBAR_ETH + 0x25C */ 91 uint32_t ieee_t_excol; /* MBAR_ETH + 0x260 */ 92 uint32_t ieee_t_macerr; /* MBAR_ETH + 0x264 */ 93 uint32_t ieee_t_cserr; /* MBAR_ETH + 0x268 */ 94 uint32_t ieee_t_sqe; /* MBAR_ETH + 0x26C */ 95 uint32_t t_fdxfc; /* MBAR_ETH + 0x270 */ 96 uint32_t ieee_t_octets_ok; /* MBAR_ETH + 0x274 */ 97 98 uint32_t res13[2]; /* MBAR_ETH + 0x278-27C */ 99 uint32_t rmon_r_drop; /* MBAR_ETH + 0x280 */ 100 uint32_t rmon_r_packets; /* MBAR_ETH + 0x284 */ 101 uint32_t rmon_r_bc_pkt; /* MBAR_ETH + 0x288 */ 102 uint32_t rmon_r_mc_pkt; /* MBAR_ETH + 0x28C */ 103 uint32_t rmon_r_crc_align; /* MBAR_ETH + 0x290 */ 104 uint32_t rmon_r_undersize; /* MBAR_ETH + 0x294 */ 105 uint32_t rmon_r_oversize; /* MBAR_ETH + 0x298 */ 106 uint32_t rmon_r_frag; /* MBAR_ETH + 0x29C */ 107 uint32_t rmon_r_jab; /* MBAR_ETH + 0x2A0 */ 108 109 uint32_t rmon_r_resvd_0; /* MBAR_ETH + 0x2A4 */ 110 111 uint32_t rmon_r_p64; /* MBAR_ETH + 0x2A8 */ 112 uint32_t rmon_r_p65to127; /* MBAR_ETH + 0x2AC */ 113 uint32_t rmon_r_p128to255; /* MBAR_ETH + 0x2B0 */ 114 uint32_t rmon_r_p256to511; /* MBAR_ETH + 0x2B4 */ 115 uint32_t rmon_r_p512to1023; /* MBAR_ETH + 0x2B8 */ 116 uint32_t rmon_r_p1024to2047; /* MBAR_ETH + 0x2BC */ 117 uint32_t rmon_r_p_gte2048; /* MBAR_ETH + 0x2C0 */ 118 uint32_t rmon_r_octets; /* MBAR_ETH + 0x2C4 */ 119 uint32_t ieee_r_drop; /* MBAR_ETH + 0x2C8 */ 120 uint32_t ieee_r_frame_ok; /* MBAR_ETH + 0x2CC */ 121 uint32_t ieee_r_crc; /* MBAR_ETH + 0x2D0 */ 122 uint32_t ieee_r_align; /* MBAR_ETH + 0x2D4 */ 123 uint32_t r_macerr; /* MBAR_ETH + 0x2D8 */ 124 uint32_t r_fdxfc; /* MBAR_ETH + 0x2DC */ 125 uint32_t ieee_r_octets_ok; /* MBAR_ETH + 0x2E0 */ 126 127 uint32_t res14[7]; /* MBAR_ETH + 0x2E4-2FC */ 128 129 #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL) 130 uint16_t miigsk_cfgr; /* MBAR_ETH + 0x300 */ 131 uint16_t res15[3]; /* MBAR_ETH + 0x302-306 */ 132 uint16_t miigsk_enr; /* MBAR_ETH + 0x308 */ 133 uint16_t res16[3]; /* MBAR_ETH + 0x30a-30e */ 134 uint32_t res17[60]; /* MBAR_ETH + 0x300-3FF */ 135 #else 136 uint32_t res15[64]; /* MBAR_ETH + 0x300-3FF */ 137 #endif 138 }; 139 140 #define FEC_IEVENT_HBERR 0x80000000 141 #define FEC_IEVENT_BABR 0x40000000 142 #define FEC_IEVENT_BABT 0x20000000 143 #define FEC_IEVENT_GRA 0x10000000 144 #define FEC_IEVENT_TXF 0x08000000 145 #define FEC_IEVENT_TXB 0x04000000 146 #define FEC_IEVENT_RXF 0x02000000 147 #define FEC_IEVENT_RXB 0x01000000 148 #define FEC_IEVENT_MII 0x00800000 149 #define FEC_IEVENT_EBERR 0x00400000 150 #define FEC_IEVENT_LC 0x00200000 151 #define FEC_IEVENT_RL 0x00100000 152 #define FEC_IEVENT_UN 0x00080000 153 154 #define FEC_IMASK_HBERR 0x80000000 155 #define FEC_IMASK_BABR 0x40000000 156 #define FEC_IMASKT_BABT 0x20000000 157 #define FEC_IMASK_GRA 0x10000000 158 #define FEC_IMASKT_TXF 0x08000000 159 #define FEC_IMASK_TXB 0x04000000 160 #define FEC_IMASKT_RXF 0x02000000 161 #define FEC_IMASK_RXB 0x01000000 162 #define FEC_IMASK_MII 0x00800000 163 #define FEC_IMASK_EBERR 0x00400000 164 #define FEC_IMASK_LC 0x00200000 165 #define FEC_IMASKT_RL 0x00100000 166 #define FEC_IMASK_UN 0x00080000 167 168 #define FEC_RCNTRL_MAX_FL_SHIFT 16 169 #define FEC_RCNTRL_LOOP 0x00000001 170 #define FEC_RCNTRL_DRT 0x00000002 171 #define FEC_RCNTRL_MII_MODE 0x00000004 172 #define FEC_RCNTRL_PROM 0x00000008 173 #define FEC_RCNTRL_BC_REJ 0x00000010 174 #define FEC_RCNTRL_FCE 0x00000020 175 #define FEC_RCNTRL_RGMII 0x00000040 176 #define FEC_RCNTRL_RMII 0x00000100 177 #define FEC_RCNTRL_RMII_10T 0x00000200 178 179 #define FEC_TCNTRL_GTS 0x00000001 180 #define FEC_TCNTRL_HBC 0x00000002 181 #define FEC_TCNTRL_FDEN 0x00000004 182 #define FEC_TCNTRL_TFC_PAUSE 0x00000008 183 #define FEC_TCNTRL_RFC_PAUSE 0x00000010 184 185 #define FEC_ECNTRL_RESET 0x00000001 /* reset the FEC */ 186 #define FEC_ECNTRL_ETHER_EN 0x00000002 /* enable the FEC */ 187 #define FEC_ECNTRL_SPEED 0x00000020 188 #define FEC_ECNTRL_DBSWAP 0x00000100 189 190 #define FEC_X_WMRK_STRFWD 0x00000100 191 192 #define FEC_X_DES_ACTIVE_TDAR 0x01000000 193 #define FEC_R_DES_ACTIVE_RDAR 0x01000000 194 195 #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL) 196 /* defines for MIIGSK */ 197 /* RMII frequency control: 0=50MHz, 1=5MHz */ 198 #define MIIGSK_CFGR_FRCONT (1 << 6) 199 /* loopback mode */ 200 #define MIIGSK_CFGR_LBMODE (1 << 4) 201 /* echo mode */ 202 #define MIIGSK_CFGR_EMODE (1 << 3) 203 /* MII gasket mode field */ 204 #define MIIGSK_CFGR_IF_MODE_MASK (3 << 0) 205 /* MMI/7-Wire mode */ 206 #define MIIGSK_CFGR_IF_MODE_MII (0 << 0) 207 /* RMII mode */ 208 #define MIIGSK_CFGR_IF_MODE_RMII (1 << 0) 209 /* reflects MIIGSK Enable bit (RO) */ 210 #define MIIGSK_ENR_READY (1 << 2) 211 /* enable MIGSK (set by default) */ 212 #define MIIGSK_ENR_EN (1 << 1) 213 #endif 214 215 /** 216 * @brief Receive & Transmit Buffer Descriptor definitions 217 * 218 * Note: The first BD must be aligned (see DB_ALIGNMENT) 219 */ 220 struct fec_bd { 221 uint16_t data_length; /* payload's length in bytes */ 222 uint16_t status; /* BD's staus (see datasheet) */ 223 uint32_t data_pointer; /* payload's buffer address */ 224 }; 225 226 /* Supported phy types on this platform */ 227 enum xceiver_type { 228 SEVENWIRE, /* 7-wire */ 229 MII10, /* MII 10Mbps */ 230 MII100, /* MII 100Mbps */ 231 RMII, /* RMII */ 232 RGMII, /* RGMII */ 233 }; 234 235 /* @brief i.MX27-FEC private structure */ 236 struct fec_priv { 237 struct ethernet_regs *eth; /* pointer to register'S base */ 238 enum xceiver_type xcv_type; /* transceiver type */ 239 struct fec_bd *rbd_base; /* RBD ring */ 240 int rbd_index; /* next receive BD to read */ 241 struct fec_bd *tbd_base; /* TBD ring */ 242 int tbd_index; /* next transmit BD to write */ 243 bd_t *bd; 244 uint8_t *tdb_ptr; 245 int dev_id; 246 struct mii_dev *bus; 247 #ifdef CONFIG_PHYLIB 248 struct phy_device *phydev; 249 #else 250 int phy_id; 251 int (*mii_postcall)(int); 252 #endif 253 #ifdef CONFIG_DM_GPIO 254 struct gpio_desc phy_reset_gpio; 255 uint32_t reset_delay; 256 #endif 257 #ifdef CONFIG_DM_ETH 258 u32 interface; 259 #endif 260 }; 261 262 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); 263 264 /** 265 * @brief Numbers of buffer descriptors for receiving 266 * 267 * The number defines the stocked memory buffers for the receiving task. 268 * Larger values makes no sense in this limited environment. 269 */ 270 #define FEC_RBD_NUM 64 271 272 /** 273 * @brief Define the ethernet packet size limit in memory 274 * 275 * Note: Do not shrink this number. This will force the FEC to spread larger 276 * frames in more than one BD. This is nothing to worry about, but the current 277 * driver can't handle it. 278 */ 279 #define FEC_MAX_PKT_SIZE 1536 280 281 /* Receive BD status bits */ 282 #define FEC_RBD_EMPTY 0x8000 /* Receive BD status: Buffer is empty */ 283 #define FEC_RBD_WRAP 0x2000 /* Receive BD status: Last BD in ring */ 284 /* Receive BD status: Buffer is last in frame (useless here!) */ 285 #define FEC_RBD_LAST 0x0800 286 #define FEC_RBD_MISS 0x0100 /* Receive BD status: Miss bit for prom mode */ 287 /* Receive BD status: The received frame is broadcast frame */ 288 #define FEC_RBD_BC 0x0080 289 /* Receive BD status: The received frame is multicast frame */ 290 #define FEC_RBD_MC 0x0040 291 #define FEC_RBD_LG 0x0020 /* Receive BD status: Frame length violation */ 292 #define FEC_RBD_NO 0x0010 /* Receive BD status: Nonoctet align frame */ 293 #define FEC_RBD_CR 0x0004 /* Receive BD status: CRC error */ 294 #define FEC_RBD_OV 0x0002 /* Receive BD status: Receive FIFO overrun */ 295 #define FEC_RBD_TR 0x0001 /* Receive BD status: Frame is truncated */ 296 #define FEC_RBD_ERR (FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \ 297 FEC_RBD_OV | FEC_RBD_TR) 298 299 /* Transmit BD status bits */ 300 #define FEC_TBD_READY 0x8000 /* Tansmit BD status: Buffer is ready */ 301 #define FEC_TBD_WRAP 0x2000 /* Tansmit BD status: Mark as last BD in ring */ 302 #define FEC_TBD_LAST 0x0800 /* Tansmit BD status: Buffer is last in frame */ 303 #define FEC_TBD_TC 0x0400 /* Tansmit BD status: Transmit the CRC */ 304 #define FEC_TBD_ABC 0x0200 /* Tansmit BD status: Append bad CRC */ 305 306 /* MII-related definitios */ 307 #define FEC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */ 308 #define FEC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */ 309 #define FEC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */ 310 #define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */ 311 #define FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */ 312 #define FEC_MII_DATA_TA 0x00020000 /* Turnaround */ 313 #define FEC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */ 314 315 #define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */ 316 #define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */ 317 318 #endif /* __FEC_MXC_H */ 319