xref: /openbmc/u-boot/drivers/net/fec_mxc.h (revision 0f3864a966cc88ac90d8e403aa634254657d874d)
1  /*
2   * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
3   * (C) Copyright 2008 Armadeus Systems, nc
4   * (C) Copyright 2008 Eric Jarrige <eric.jarrige@armadeus.org>
5   * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6   * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
7   *
8   * (C) Copyright 2003
9   * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10   *
11   * This file is based on mpc4200fec.h
12   * (C) Copyright Motorola, Inc., 2000
13   *
14   * This program is free software; you can redistribute it and/or
15   * modify it under the terms of the GNU General Public License as
16   * published by the Free Software Foundation; either version 2 of
17   * the License, or (at your option) any later version.
18   *
19   * This program is distributed in the hope that it will be useful,
20   * but WITHOUT ANY WARRANTY; without even the implied warranty of
21   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
22   * GNU General Public License for more details.
23   *
24   * You should have received a copy of the GNU General Public License
25   * along with this program; if not, write to the Free Software
26   * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27   * MA 02111-1307 USA
28   *
29   */
30  
31  
32  #ifndef __FEC_MXC_H
33  #define __FEC_MXC_H
34  
35  void imx_get_mac_from_fuse(unsigned char *mac);
36  
37  /**
38   * Layout description of the FEC
39   */
40  struct ethernet_regs {
41  
42  /* [10:2]addr = 00 */
43  
44  /*  Control and status Registers (offset 000-1FF) */
45  
46  	uint32_t res0[1];		/* MBAR_ETH + 0x000 */
47  	uint32_t ievent;		/* MBAR_ETH + 0x004 */
48  	uint32_t imask;			/* MBAR_ETH + 0x008 */
49  
50  	uint32_t res1[1];		/* MBAR_ETH + 0x00C */
51  	uint32_t r_des_active;		/* MBAR_ETH + 0x010 */
52  	uint32_t x_des_active;		/* MBAR_ETH + 0x014 */
53  	uint32_t res2[3];		/* MBAR_ETH + 0x018-20 */
54  	uint32_t ecntrl;		/* MBAR_ETH + 0x024 */
55  
56  	uint32_t res3[6];		/* MBAR_ETH + 0x028-03C */
57  	uint32_t mii_data;		/* MBAR_ETH + 0x040 */
58  	uint32_t mii_speed;		/* MBAR_ETH + 0x044 */
59  	uint32_t res4[7];		/* MBAR_ETH + 0x048-60 */
60  	uint32_t mib_control;		/* MBAR_ETH + 0x064 */
61  
62  	uint32_t res5[7];		/* MBAR_ETH + 0x068-80 */
63  	uint32_t r_cntrl;		/* MBAR_ETH + 0x084 */
64  	uint32_t res6[15];		/* MBAR_ETH + 0x088-C0 */
65  	uint32_t x_cntrl;		/* MBAR_ETH + 0x0C4 */
66  	uint32_t res7[7];		/* MBAR_ETH + 0x0C8-E0 */
67  	uint32_t paddr1;		/* MBAR_ETH + 0x0E4 */
68  	uint32_t paddr2;		/* MBAR_ETH + 0x0E8 */
69  	uint32_t op_pause;		/* MBAR_ETH + 0x0EC */
70  
71  	uint32_t res8[10];		/* MBAR_ETH + 0x0F0-114 */
72  	uint32_t iaddr1;		/* MBAR_ETH + 0x118 */
73  	uint32_t iaddr2;		/* MBAR_ETH + 0x11C */
74  	uint32_t gaddr1;		/* MBAR_ETH + 0x120 */
75  	uint32_t gaddr2;		/* MBAR_ETH + 0x124 */
76  	uint32_t res9[7];		/* MBAR_ETH + 0x128-140 */
77  
78  	uint32_t x_wmrk;		/* MBAR_ETH + 0x144 */
79  	uint32_t res10[1];		/* MBAR_ETH + 0x148 */
80  	uint32_t r_bound;		/* MBAR_ETH + 0x14C */
81  	uint32_t r_fstart;		/* MBAR_ETH + 0x150 */
82  	uint32_t res11[11];		/* MBAR_ETH + 0x154-17C */
83  	uint32_t erdsr;			/* MBAR_ETH + 0x180 */
84  	uint32_t etdsr;			/* MBAR_ETH + 0x184 */
85  	uint32_t emrbr;			/* MBAR_ETH + 0x188 */
86  	uint32_t res12[29];		/* MBAR_ETH + 0x18C-1FC */
87  
88  /*  MIB COUNTERS (Offset 200-2FF) */
89  
90  	uint32_t rmon_t_drop;		/* MBAR_ETH + 0x200 */
91  	uint32_t rmon_t_packets;	/* MBAR_ETH + 0x204 */
92  	uint32_t rmon_t_bc_pkt;		/* MBAR_ETH + 0x208 */
93  	uint32_t rmon_t_mc_pkt;		/* MBAR_ETH + 0x20C */
94  	uint32_t rmon_t_crc_align;	/* MBAR_ETH + 0x210 */
95  	uint32_t rmon_t_undersize;	/* MBAR_ETH + 0x214 */
96  	uint32_t rmon_t_oversize;	/* MBAR_ETH + 0x218 */
97  	uint32_t rmon_t_frag;		/* MBAR_ETH + 0x21C */
98  	uint32_t rmon_t_jab;		/* MBAR_ETH + 0x220 */
99  	uint32_t rmon_t_col;		/* MBAR_ETH + 0x224 */
100  	uint32_t rmon_t_p64;		/* MBAR_ETH + 0x228 */
101  	uint32_t rmon_t_p65to127;	/* MBAR_ETH + 0x22C */
102  	uint32_t rmon_t_p128to255;	/* MBAR_ETH + 0x230 */
103  	uint32_t rmon_t_p256to511;	/* MBAR_ETH + 0x234 */
104  	uint32_t rmon_t_p512to1023;	/* MBAR_ETH + 0x238 */
105  	uint32_t rmon_t_p1024to2047;	/* MBAR_ETH + 0x23C */
106  	uint32_t rmon_t_p_gte2048;	/* MBAR_ETH + 0x240 */
107  	uint32_t rmon_t_octets;		/* MBAR_ETH + 0x244 */
108  	uint32_t ieee_t_drop;		/* MBAR_ETH + 0x248 */
109  	uint32_t ieee_t_frame_ok;	/* MBAR_ETH + 0x24C */
110  	uint32_t ieee_t_1col;		/* MBAR_ETH + 0x250 */
111  	uint32_t ieee_t_mcol;		/* MBAR_ETH + 0x254 */
112  	uint32_t ieee_t_def;		/* MBAR_ETH + 0x258 */
113  	uint32_t ieee_t_lcol;		/* MBAR_ETH + 0x25C */
114  	uint32_t ieee_t_excol;		/* MBAR_ETH + 0x260 */
115  	uint32_t ieee_t_macerr;		/* MBAR_ETH + 0x264 */
116  	uint32_t ieee_t_cserr;		/* MBAR_ETH + 0x268 */
117  	uint32_t ieee_t_sqe;		/* MBAR_ETH + 0x26C */
118  	uint32_t t_fdxfc;		/* MBAR_ETH + 0x270 */
119  	uint32_t ieee_t_octets_ok;	/* MBAR_ETH + 0x274 */
120  
121  	uint32_t res13[2];		/* MBAR_ETH + 0x278-27C */
122  	uint32_t rmon_r_drop;		/* MBAR_ETH + 0x280 */
123  	uint32_t rmon_r_packets;	/* MBAR_ETH + 0x284 */
124  	uint32_t rmon_r_bc_pkt;		/* MBAR_ETH + 0x288 */
125  	uint32_t rmon_r_mc_pkt;		/* MBAR_ETH + 0x28C */
126  	uint32_t rmon_r_crc_align;	/* MBAR_ETH + 0x290 */
127  	uint32_t rmon_r_undersize;	/* MBAR_ETH + 0x294 */
128  	uint32_t rmon_r_oversize;	/* MBAR_ETH + 0x298 */
129  	uint32_t rmon_r_frag;		/* MBAR_ETH + 0x29C */
130  	uint32_t rmon_r_jab;		/* MBAR_ETH + 0x2A0 */
131  
132  	uint32_t rmon_r_resvd_0;	/* MBAR_ETH + 0x2A4 */
133  
134  	uint32_t rmon_r_p64;		/* MBAR_ETH + 0x2A8 */
135  	uint32_t rmon_r_p65to127;	/* MBAR_ETH + 0x2AC */
136  	uint32_t rmon_r_p128to255;	/* MBAR_ETH + 0x2B0 */
137  	uint32_t rmon_r_p256to511;	/* MBAR_ETH + 0x2B4 */
138  	uint32_t rmon_r_p512to1023;	/* MBAR_ETH + 0x2B8 */
139  	uint32_t rmon_r_p1024to2047;	/* MBAR_ETH + 0x2BC */
140  	uint32_t rmon_r_p_gte2048;	/* MBAR_ETH + 0x2C0 */
141  	uint32_t rmon_r_octets;		/* MBAR_ETH + 0x2C4 */
142  	uint32_t ieee_r_drop;		/* MBAR_ETH + 0x2C8 */
143  	uint32_t ieee_r_frame_ok;	/* MBAR_ETH + 0x2CC */
144  	uint32_t ieee_r_crc;		/* MBAR_ETH + 0x2D0 */
145  	uint32_t ieee_r_align;		/* MBAR_ETH + 0x2D4 */
146  	uint32_t r_macerr;		/* MBAR_ETH + 0x2D8 */
147  	uint32_t r_fdxfc;		/* MBAR_ETH + 0x2DC */
148  	uint32_t ieee_r_octets_ok;	/* MBAR_ETH + 0x2E0 */
149  
150  	uint32_t res14[7];		/* MBAR_ETH + 0x2E4-2FC */
151  
152  #if defined(CONFIG_MX25) || defined(CONFIG_MX53)
153  	uint16_t miigsk_cfgr;		/* MBAR_ETH + 0x300 */
154  	uint16_t res15[3];		/* MBAR_ETH + 0x302-306 */
155  	uint16_t miigsk_enr;		/* MBAR_ETH + 0x308 */
156  	uint16_t res16[3];		/* MBAR_ETH + 0x30a-30e */
157  	uint32_t res17[60];		/* MBAR_ETH + 0x300-3FF */
158  #else
159  	uint32_t res15[64];		/* MBAR_ETH + 0x300-3FF */
160  #endif
161  };
162  
163  #define FEC_IEVENT_HBERR		0x80000000
164  #define FEC_IEVENT_BABR			0x40000000
165  #define FEC_IEVENT_BABT			0x20000000
166  #define FEC_IEVENT_GRA			0x10000000
167  #define FEC_IEVENT_TXF			0x08000000
168  #define FEC_IEVENT_TXB			0x04000000
169  #define FEC_IEVENT_RXF			0x02000000
170  #define FEC_IEVENT_RXB			0x01000000
171  #define FEC_IEVENT_MII			0x00800000
172  #define FEC_IEVENT_EBERR		0x00400000
173  #define FEC_IEVENT_LC			0x00200000
174  #define FEC_IEVENT_RL			0x00100000
175  #define FEC_IEVENT_UN			0x00080000
176  
177  #define FEC_IMASK_HBERR			0x80000000
178  #define FEC_IMASK_BABR			0x40000000
179  #define FEC_IMASKT_BABT			0x20000000
180  #define FEC_IMASK_GRA			0x10000000
181  #define FEC_IMASKT_TXF			0x08000000
182  #define FEC_IMASK_TXB			0x04000000
183  #define FEC_IMASKT_RXF			0x02000000
184  #define FEC_IMASK_RXB			0x01000000
185  #define FEC_IMASK_MII			0x00800000
186  #define FEC_IMASK_EBERR			0x00400000
187  #define FEC_IMASK_LC			0x00200000
188  #define FEC_IMASKT_RL			0x00100000
189  #define FEC_IMASK_UN			0x00080000
190  
191  
192  #define FEC_RCNTRL_MAX_FL_SHIFT		16
193  #define FEC_RCNTRL_LOOP			0x00000001
194  #define FEC_RCNTRL_DRT			0x00000002
195  #define FEC_RCNTRL_MII_MODE		0x00000004
196  #define FEC_RCNTRL_PROM			0x00000008
197  #define FEC_RCNTRL_BC_REJ		0x00000010
198  #define FEC_RCNTRL_FCE			0x00000020
199  #define FEC_RCNTRL_RMII			0x00000100
200  
201  #define FEC_TCNTRL_GTS			0x00000001
202  #define FEC_TCNTRL_HBC			0x00000002
203  #define FEC_TCNTRL_FDEN			0x00000004
204  #define FEC_TCNTRL_TFC_PAUSE		0x00000008
205  #define FEC_TCNTRL_RFC_PAUSE		0x00000010
206  
207  #define FEC_ECNTRL_RESET		0x00000001	/* reset the FEC */
208  #define FEC_ECNTRL_ETHER_EN		0x00000002	/* enable the FEC */
209  
210  #if defined(CONFIG_MX25) || defined(CONFIG_MX53)
211  /* defines for MIIGSK */
212  /* RMII frequency control: 0=50MHz, 1=5MHz */
213  #define MIIGSK_CFGR_FRCONT		(1 << 6)
214  /* loopback mode */
215  #define MIIGSK_CFGR_LBMODE		(1 << 4)
216  /* echo mode */
217  #define MIIGSK_CFGR_EMODE		(1 << 3)
218  /* MII gasket mode field */
219  #define MIIGSK_CFGR_IF_MODE_MASK	(3 << 0)
220  /* MMI/7-Wire mode */
221  #define MIIGSK_CFGR_IF_MODE_MII		(0 << 0)
222  /* RMII mode */
223  #define MIIGSK_CFGR_IF_MODE_RMII	(1 << 0)
224  /* reflects MIIGSK Enable bit (RO) */
225  #define MIIGSK_ENR_READY		(1 << 2)
226  /* enable MIGSK (set by default) */
227  #define MIIGSK_ENR_EN			(1 << 1)
228  #endif
229  
230  /**
231   * @brief Descriptor buffer alignment
232   *
233   * i.MX27 requires a 16 byte alignment (but for the first element only)
234   */
235  #define DB_ALIGNMENT		16
236  
237  /**
238   * @brief Data buffer alignment
239   *
240   * i.MX27 requires a four byte alignment for transmit and 16 bits
241   * alignment for receive so take 16
242   * Note: Valid for member data_pointer in struct buffer_descriptor
243   */
244  #define DB_DATA_ALIGNMENT	16
245  
246  /**
247   * @brief Receive & Transmit Buffer Descriptor definitions
248   *
249   * Note: The first BD must be aligned (see DB_ALIGNMENT)
250   */
251  struct fec_bd {
252  	uint16_t data_length;		/* payload's length in bytes */
253  	uint16_t status;		/* BD's staus (see datasheet) */
254  	uint32_t data_pointer;		/* payload's buffer address */
255  };
256  
257  /**
258   * Supported phy types on this platform
259   */
260  enum xceiver_type {
261  	SEVENWIRE,	/* 7-wire       */
262  	MII10,		/* MII 10Mbps   */
263  	MII100,		/* MII 100Mbps  */
264  	RMII		/* RMII */
265  };
266  
267  /**
268   * @brief i.MX27-FEC private structure
269   */
270  struct fec_priv {
271  	struct ethernet_regs *eth;	/* pointer to register'S base */
272  	enum xceiver_type xcv_type;	/* transceiver type */
273  	struct fec_bd *rbd_base;	/* RBD ring */
274  	int rbd_index;			/* next receive BD to read */
275  	struct fec_bd *tbd_base;	/* TBD ring */
276  	int tbd_index;			/* next transmit BD to write */
277  	bd_t *bd;
278  	void *rdb_ptr;
279  	void *base_ptr;
280  	int dev_id;
281  	int phy_id;
282  	int (*mii_postcall)(int);
283  };
284  
285  /**
286   * @brief Numbers of buffer descriptors for receiving
287   *
288   * The number defines the stocked memory buffers for the receiving task.
289   * Larger values makes no sense in this limited environment.
290   */
291  #define FEC_RBD_NUM		64
292  
293  /**
294   * @brief Define the ethernet packet size limit in memory
295   *
296   * Note: Do not shrink this number. This will force the FEC to spread larger
297   * frames in more than one BD. This is nothing to worry about, but the current
298   * driver can't handle it.
299   */
300  #define FEC_MAX_PKT_SIZE	1536
301  
302  /* Receive BD status bits */
303  #define FEC_RBD_EMPTY	0x8000	/* Receive BD status: Buffer is empty */
304  #define FEC_RBD_WRAP	0x2000	/* Receive BD status: Last BD in ring */
305  /* Receive BD status: Buffer is last in frame (useless here!) */
306  #define FEC_RBD_LAST	0x0800
307  #define FEC_RBD_MISS	0x0100	/* Receive BD status: Miss bit for prom mode */
308  /* Receive BD status: The received frame is broadcast frame */
309  #define FEC_RBD_BC	0x0080
310  /* Receive BD status: The received frame is multicast frame */
311  #define FEC_RBD_MC	0x0040
312  #define FEC_RBD_LG	0x0020	/* Receive BD status: Frame length violation */
313  #define FEC_RBD_NO	0x0010	/* Receive BD status: Nonoctet align frame */
314  #define FEC_RBD_CR	0x0004	/* Receive BD status: CRC error */
315  #define FEC_RBD_OV	0x0002	/* Receive BD status: Receive FIFO overrun */
316  #define FEC_RBD_TR	0x0001	/* Receive BD status: Frame is truncated */
317  #define FEC_RBD_ERR	(FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \
318  			FEC_RBD_OV | FEC_RBD_TR)
319  
320  /* Transmit BD status bits */
321  #define FEC_TBD_READY	0x8000	/* Tansmit BD status: Buffer is ready */
322  #define FEC_TBD_WRAP	0x2000	/* Tansmit BD status: Mark as last BD in ring */
323  #define FEC_TBD_LAST	0x0800	/* Tansmit BD status: Buffer is last in frame */
324  #define FEC_TBD_TC	0x0400	/* Tansmit BD status: Transmit the CRC */
325  #define FEC_TBD_ABC	0x0200	/* Tansmit BD status: Append bad CRC */
326  
327  /* MII-related definitios */
328  #define FEC_MII_DATA_ST		0x40000000	/* Start of frame delimiter */
329  #define FEC_MII_DATA_OP_RD	0x20000000	/* Perform a read operation */
330  #define FEC_MII_DATA_OP_WR	0x10000000	/* Perform a write operation */
331  #define FEC_MII_DATA_PA_MSK	0x0f800000	/* PHY Address field mask */
332  #define FEC_MII_DATA_RA_MSK	0x007c0000	/* PHY Register field mask */
333  #define FEC_MII_DATA_TA		0x00020000	/* Turnaround */
334  #define FEC_MII_DATA_DATAMSK	0x0000ffff	/* PHY data field */
335  
336  #define FEC_MII_DATA_RA_SHIFT	18	/* MII Register address bits */
337  #define FEC_MII_DATA_PA_SHIFT	23	/* MII PHY address bits */
338  
339  #endif	/* __FEC_MXC_H */
340