1 /* 2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com> 3 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org> 4 * (C) Copyright 2008 Armadeus Systems nc 5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <malloc.h> 26 #include <net.h> 27 #include <miiphy.h> 28 #include "fec_mxc.h" 29 30 #include <asm/arch/clock.h> 31 #include <asm/arch/imx-regs.h> 32 #include <asm/io.h> 33 #include <asm/errno.h> 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 #ifndef CONFIG_MII 38 #error "CONFIG_MII has to be defined!" 39 #endif 40 41 #ifndef CONFIG_FEC_XCV_TYPE 42 #define CONFIG_FEC_XCV_TYPE MII100 43 #endif 44 45 /* 46 * The i.MX28 operates with packets in big endian. We need to swap them before 47 * sending and after receiving. 48 */ 49 #ifdef CONFIG_MX28 50 #define CONFIG_FEC_MXC_SWAP_PACKET 51 #endif 52 53 #undef DEBUG 54 55 struct nbuf { 56 uint8_t data[1500]; /**< actual data */ 57 int length; /**< actual length */ 58 int used; /**< buffer in use or not */ 59 uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */ 60 }; 61 62 #ifdef CONFIG_FEC_MXC_SWAP_PACKET 63 static void swap_packet(uint32_t *packet, int length) 64 { 65 int i; 66 67 for (i = 0; i < DIV_ROUND_UP(length, 4); i++) 68 packet[i] = __swab32(packet[i]); 69 } 70 #endif 71 72 /* 73 * The i.MX28 has two ethernet interfaces, but they are not equal. 74 * Only the first one can access the MDIO bus. 75 */ 76 #ifdef CONFIG_MX28 77 static inline struct ethernet_regs *fec_miiphy_fec_to_eth(struct fec_priv *fec) 78 { 79 return (struct ethernet_regs *)MXS_ENET0_BASE; 80 } 81 #else 82 static inline struct ethernet_regs *fec_miiphy_fec_to_eth(struct fec_priv *fec) 83 { 84 return fec->eth; 85 } 86 #endif 87 88 /* 89 * MII-interface related functions 90 */ 91 static int fec_miiphy_read(const char *dev, uint8_t phyAddr, uint8_t regAddr, 92 uint16_t *retVal) 93 { 94 struct eth_device *edev = eth_get_dev_by_name(dev); 95 struct fec_priv *fec = (struct fec_priv *)edev->priv; 96 struct ethernet_regs *eth = fec_miiphy_fec_to_eth(fec); 97 98 uint32_t reg; /* convenient holder for the PHY register */ 99 uint32_t phy; /* convenient holder for the PHY */ 100 uint32_t start; 101 102 /* 103 * reading from any PHY's register is done by properly 104 * programming the FEC's MII data register. 105 */ 106 writel(FEC_IEVENT_MII, ð->ievent); 107 reg = regAddr << FEC_MII_DATA_RA_SHIFT; 108 phy = phyAddr << FEC_MII_DATA_PA_SHIFT; 109 110 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | 111 phy | reg, ð->mii_data); 112 113 /* 114 * wait for the related interrupt 115 */ 116 start = get_timer(0); 117 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { 118 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { 119 printf("Read MDIO failed...\n"); 120 return -1; 121 } 122 } 123 124 /* 125 * clear mii interrupt bit 126 */ 127 writel(FEC_IEVENT_MII, ð->ievent); 128 129 /* 130 * it's now safe to read the PHY's register 131 */ 132 *retVal = readl(ð->mii_data); 133 debug("fec_miiphy_read: phy: %02x reg:%02x val:%#x\n", phyAddr, 134 regAddr, *retVal); 135 return 0; 136 } 137 138 static void fec_mii_setspeed(struct fec_priv *fec) 139 { 140 /* 141 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock 142 * and do not drop the Preamble. 143 */ 144 writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1, 145 &fec->eth->mii_speed); 146 debug("fec_init: mii_speed %08x\n", 147 readl(&fec->eth->mii_speed)); 148 } 149 static int fec_miiphy_write(const char *dev, uint8_t phyAddr, uint8_t regAddr, 150 uint16_t data) 151 { 152 struct eth_device *edev = eth_get_dev_by_name(dev); 153 struct fec_priv *fec = (struct fec_priv *)edev->priv; 154 struct ethernet_regs *eth = fec_miiphy_fec_to_eth(fec); 155 156 uint32_t reg; /* convenient holder for the PHY register */ 157 uint32_t phy; /* convenient holder for the PHY */ 158 uint32_t start; 159 160 reg = regAddr << FEC_MII_DATA_RA_SHIFT; 161 phy = phyAddr << FEC_MII_DATA_PA_SHIFT; 162 163 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | 164 FEC_MII_DATA_TA | phy | reg | data, ð->mii_data); 165 166 /* 167 * wait for the MII interrupt 168 */ 169 start = get_timer(0); 170 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { 171 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { 172 printf("Write MDIO failed...\n"); 173 return -1; 174 } 175 } 176 177 /* 178 * clear MII interrupt bit 179 */ 180 writel(FEC_IEVENT_MII, ð->ievent); 181 debug("fec_miiphy_write: phy: %02x reg:%02x val:%#x\n", phyAddr, 182 regAddr, data); 183 184 return 0; 185 } 186 187 static int miiphy_restart_aneg(struct eth_device *dev) 188 { 189 struct fec_priv *fec = (struct fec_priv *)dev->priv; 190 int ret = 0; 191 192 /* 193 * Wake up from sleep if necessary 194 * Reset PHY, then delay 300ns 195 */ 196 #ifdef CONFIG_MX27 197 miiphy_write(dev->name, fec->phy_id, MII_DCOUNTER, 0x00FF); 198 #endif 199 miiphy_write(dev->name, fec->phy_id, MII_BMCR, 200 BMCR_RESET); 201 udelay(1000); 202 203 /* 204 * Set the auto-negotiation advertisement register bits 205 */ 206 miiphy_write(dev->name, fec->phy_id, MII_ADVERTISE, 207 LPA_100FULL | LPA_100HALF | LPA_10FULL | 208 LPA_10HALF | PHY_ANLPAR_PSB_802_3); 209 miiphy_write(dev->name, fec->phy_id, MII_BMCR, 210 BMCR_ANENABLE | BMCR_ANRESTART); 211 212 if (fec->mii_postcall) 213 ret = fec->mii_postcall(fec->phy_id); 214 215 return ret; 216 } 217 218 static int miiphy_wait_aneg(struct eth_device *dev) 219 { 220 uint32_t start; 221 uint16_t status; 222 struct fec_priv *fec = (struct fec_priv *)dev->priv; 223 224 /* 225 * Wait for AN completion 226 */ 227 start = get_timer(0); 228 do { 229 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { 230 printf("%s: Autonegotiation timeout\n", dev->name); 231 return -1; 232 } 233 234 if (miiphy_read(dev->name, fec->phy_id, 235 MII_BMSR, &status)) { 236 printf("%s: Autonegotiation failed. status: 0x%04x\n", 237 dev->name, status); 238 return -1; 239 } 240 } while (!(status & BMSR_LSTATUS)); 241 242 return 0; 243 } 244 static int fec_rx_task_enable(struct fec_priv *fec) 245 { 246 writel(1 << 24, &fec->eth->r_des_active); 247 return 0; 248 } 249 250 static int fec_rx_task_disable(struct fec_priv *fec) 251 { 252 return 0; 253 } 254 255 static int fec_tx_task_enable(struct fec_priv *fec) 256 { 257 writel(1 << 24, &fec->eth->x_des_active); 258 return 0; 259 } 260 261 static int fec_tx_task_disable(struct fec_priv *fec) 262 { 263 return 0; 264 } 265 266 /** 267 * Initialize receive task's buffer descriptors 268 * @param[in] fec all we know about the device yet 269 * @param[in] count receive buffer count to be allocated 270 * @param[in] size size of each receive buffer 271 * @return 0 on success 272 * 273 * For this task we need additional memory for the data buffers. And each 274 * data buffer requires some alignment. Thy must be aligned to a specific 275 * boundary each (DB_DATA_ALIGNMENT). 276 */ 277 static int fec_rbd_init(struct fec_priv *fec, int count, int size) 278 { 279 int ix; 280 uint32_t p = 0; 281 282 /* reserve data memory and consider alignment */ 283 if (fec->rdb_ptr == NULL) 284 fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT); 285 p = (uint32_t)fec->rdb_ptr; 286 if (!p) { 287 puts("fec_mxc: not enough malloc memory\n"); 288 return -ENOMEM; 289 } 290 memset((void *)p, 0, size * count + DB_DATA_ALIGNMENT); 291 p += DB_DATA_ALIGNMENT-1; 292 p &= ~(DB_DATA_ALIGNMENT-1); 293 294 for (ix = 0; ix < count; ix++) { 295 writel(p, &fec->rbd_base[ix].data_pointer); 296 p += size; 297 writew(FEC_RBD_EMPTY, &fec->rbd_base[ix].status); 298 writew(0, &fec->rbd_base[ix].data_length); 299 } 300 /* 301 * mark the last RBD to close the ring 302 */ 303 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[ix - 1].status); 304 fec->rbd_index = 0; 305 306 return 0; 307 } 308 309 /** 310 * Initialize transmit task's buffer descriptors 311 * @param[in] fec all we know about the device yet 312 * 313 * Transmit buffers are created externally. We only have to init the BDs here.\n 314 * Note: There is a race condition in the hardware. When only one BD is in 315 * use it must be marked with the WRAP bit to use it for every transmitt. 316 * This bit in combination with the READY bit results into double transmit 317 * of each data buffer. It seems the state machine checks READY earlier then 318 * resetting it after the first transfer. 319 * Using two BDs solves this issue. 320 */ 321 static void fec_tbd_init(struct fec_priv *fec) 322 { 323 writew(0x0000, &fec->tbd_base[0].status); 324 writew(FEC_TBD_WRAP, &fec->tbd_base[1].status); 325 fec->tbd_index = 0; 326 } 327 328 /** 329 * Mark the given read buffer descriptor as free 330 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0 331 * @param[in] pRbd buffer descriptor to mark free again 332 */ 333 static void fec_rbd_clean(int last, struct fec_bd *pRbd) 334 { 335 /* 336 * Reset buffer descriptor as empty 337 */ 338 if (last) 339 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &pRbd->status); 340 else 341 writew(FEC_RBD_EMPTY, &pRbd->status); 342 /* 343 * no data in it 344 */ 345 writew(0, &pRbd->data_length); 346 } 347 348 static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac) 349 { 350 imx_get_mac_from_fuse(mac); 351 return !is_valid_ether_addr(mac); 352 } 353 354 static int fec_set_hwaddr(struct eth_device *dev) 355 { 356 uchar *mac = dev->enetaddr; 357 struct fec_priv *fec = (struct fec_priv *)dev->priv; 358 359 writel(0, &fec->eth->iaddr1); 360 writel(0, &fec->eth->iaddr2); 361 writel(0, &fec->eth->gaddr1); 362 writel(0, &fec->eth->gaddr2); 363 364 /* 365 * Set physical address 366 */ 367 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3], 368 &fec->eth->paddr1); 369 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2); 370 371 return 0; 372 } 373 374 /** 375 * Start the FEC engine 376 * @param[in] dev Our device to handle 377 */ 378 static int fec_open(struct eth_device *edev) 379 { 380 struct fec_priv *fec = (struct fec_priv *)edev->priv; 381 382 debug("fec_open: fec_open(dev)\n"); 383 /* full-duplex, heartbeat disabled */ 384 writel(1 << 2, &fec->eth->x_cntrl); 385 fec->rbd_index = 0; 386 387 /* 388 * Enable FEC-Lite controller 389 */ 390 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, 391 &fec->eth->ecntrl); 392 #if defined(CONFIG_MX25) || defined(CONFIG_MX53) 393 udelay(100); 394 /* 395 * setup the MII gasket for RMII mode 396 */ 397 398 /* disable the gasket */ 399 writew(0, &fec->eth->miigsk_enr); 400 401 /* wait for the gasket to be disabled */ 402 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) 403 udelay(2); 404 405 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */ 406 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr); 407 408 /* re-enable the gasket */ 409 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr); 410 411 /* wait until MII gasket is ready */ 412 int max_loops = 10; 413 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) { 414 if (--max_loops <= 0) { 415 printf("WAIT for MII Gasket ready timed out\n"); 416 break; 417 } 418 } 419 #endif 420 421 miiphy_wait_aneg(edev); 422 miiphy_speed(edev->name, fec->phy_id); 423 miiphy_duplex(edev->name, fec->phy_id); 424 425 /* 426 * Enable SmartDMA receive task 427 */ 428 fec_rx_task_enable(fec); 429 430 udelay(100000); 431 return 0; 432 } 433 434 static int fec_init(struct eth_device *dev, bd_t* bd) 435 { 436 uint32_t base; 437 struct fec_priv *fec = (struct fec_priv *)dev->priv; 438 uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop; 439 uint32_t rcntrl; 440 int i; 441 442 /* Initialize MAC address */ 443 fec_set_hwaddr(dev); 444 445 /* 446 * reserve memory for both buffer descriptor chains at once 447 * Datasheet forces the startaddress of each chain is 16 byte 448 * aligned 449 */ 450 if (fec->base_ptr == NULL) 451 fec->base_ptr = malloc((2 + FEC_RBD_NUM) * 452 sizeof(struct fec_bd) + DB_ALIGNMENT); 453 base = (uint32_t)fec->base_ptr; 454 if (!base) { 455 puts("fec_mxc: not enough malloc memory\n"); 456 return -ENOMEM; 457 } 458 memset((void *)base, 0, (2 + FEC_RBD_NUM) * 459 sizeof(struct fec_bd) + DB_ALIGNMENT); 460 base += (DB_ALIGNMENT-1); 461 base &= ~(DB_ALIGNMENT-1); 462 463 fec->rbd_base = (struct fec_bd *)base; 464 465 base += FEC_RBD_NUM * sizeof(struct fec_bd); 466 467 fec->tbd_base = (struct fec_bd *)base; 468 469 /* 470 * Set interrupt mask register 471 */ 472 writel(0x00000000, &fec->eth->imask); 473 474 /* 475 * Clear FEC-Lite interrupt event register(IEVENT) 476 */ 477 writel(0xffffffff, &fec->eth->ievent); 478 479 480 /* 481 * Set FEC-Lite receive control register(R_CNTRL): 482 */ 483 484 /* Start with frame length = 1518, common for all modes. */ 485 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT; 486 if (fec->xcv_type == SEVENWIRE) 487 rcntrl |= FEC_RCNTRL_FCE; 488 else if (fec->xcv_type == RMII) 489 rcntrl |= FEC_RCNTRL_RMII; 490 else /* MII mode */ 491 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE; 492 493 writel(rcntrl, &fec->eth->r_cntrl); 494 495 if (fec->xcv_type == MII10 || fec->xcv_type == MII100) 496 fec_mii_setspeed(fec); 497 498 /* 499 * Set Opcode/Pause Duration Register 500 */ 501 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */ 502 writel(0x2, &fec->eth->x_wmrk); 503 /* 504 * Set multicast address filter 505 */ 506 writel(0x00000000, &fec->eth->gaddr1); 507 writel(0x00000000, &fec->eth->gaddr2); 508 509 510 /* clear MIB RAM */ 511 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) 512 writel(0, i); 513 514 /* FIFO receive start register */ 515 writel(0x520, &fec->eth->r_fstart); 516 517 /* size and address of each buffer */ 518 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr); 519 writel((uint32_t)fec->tbd_base, &fec->eth->etdsr); 520 writel((uint32_t)fec->rbd_base, &fec->eth->erdsr); 521 522 /* 523 * Initialize RxBD/TxBD rings 524 */ 525 if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) { 526 free(fec->base_ptr); 527 fec->base_ptr = NULL; 528 return -ENOMEM; 529 } 530 fec_tbd_init(fec); 531 532 533 if (fec->xcv_type != SEVENWIRE) 534 miiphy_restart_aneg(dev); 535 536 fec_open(dev); 537 return 0; 538 } 539 540 /** 541 * Halt the FEC engine 542 * @param[in] dev Our device to handle 543 */ 544 static void fec_halt(struct eth_device *dev) 545 { 546 struct fec_priv *fec = (struct fec_priv *)dev->priv; 547 int counter = 0xffff; 548 549 /* 550 * issue graceful stop command to the FEC transmitter if necessary 551 */ 552 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl), 553 &fec->eth->x_cntrl); 554 555 debug("eth_halt: wait for stop regs\n"); 556 /* 557 * wait for graceful stop to register 558 */ 559 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA))) 560 udelay(1); 561 562 /* 563 * Disable SmartDMA tasks 564 */ 565 fec_tx_task_disable(fec); 566 fec_rx_task_disable(fec); 567 568 /* 569 * Disable the Ethernet Controller 570 * Note: this will also reset the BD index counter! 571 */ 572 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN, 573 &fec->eth->ecntrl); 574 fec->rbd_index = 0; 575 fec->tbd_index = 0; 576 debug("eth_halt: done\n"); 577 } 578 579 /** 580 * Transmit one frame 581 * @param[in] dev Our ethernet device to handle 582 * @param[in] packet Pointer to the data to be transmitted 583 * @param[in] length Data count in bytes 584 * @return 0 on success 585 */ 586 static int fec_send(struct eth_device *dev, volatile void* packet, int length) 587 { 588 unsigned int status; 589 590 /* 591 * This routine transmits one frame. This routine only accepts 592 * 6-byte Ethernet addresses. 593 */ 594 struct fec_priv *fec = (struct fec_priv *)dev->priv; 595 596 /* 597 * Check for valid length of data. 598 */ 599 if ((length > 1500) || (length <= 0)) { 600 printf("Payload (%d) too large\n", length); 601 return -1; 602 } 603 604 /* 605 * Setup the transmit buffer 606 * Note: We are always using the first buffer for transmission, 607 * the second will be empty and only used to stop the DMA engine 608 */ 609 #ifdef CONFIG_FEC_MXC_SWAP_PACKET 610 swap_packet((uint32_t *)packet, length); 611 #endif 612 writew(length, &fec->tbd_base[fec->tbd_index].data_length); 613 writel((uint32_t)packet, &fec->tbd_base[fec->tbd_index].data_pointer); 614 /* 615 * update BD's status now 616 * This block: 617 * - is always the last in a chain (means no chain) 618 * - should transmitt the CRC 619 * - might be the last BD in the list, so the address counter should 620 * wrap (-> keep the WRAP flag) 621 */ 622 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP; 623 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; 624 writew(status, &fec->tbd_base[fec->tbd_index].status); 625 626 /* 627 * Enable SmartDMA transmit task 628 */ 629 fec_tx_task_enable(fec); 630 631 /* 632 * wait until frame is sent . 633 */ 634 while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) { 635 udelay(1); 636 } 637 debug("fec_send: status 0x%x index %d\n", 638 readw(&fec->tbd_base[fec->tbd_index].status), 639 fec->tbd_index); 640 /* for next transmission use the other buffer */ 641 if (fec->tbd_index) 642 fec->tbd_index = 0; 643 else 644 fec->tbd_index = 1; 645 646 return 0; 647 } 648 649 /** 650 * Pull one frame from the card 651 * @param[in] dev Our ethernet device to handle 652 * @return Length of packet read 653 */ 654 static int fec_recv(struct eth_device *dev) 655 { 656 struct fec_priv *fec = (struct fec_priv *)dev->priv; 657 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index]; 658 unsigned long ievent; 659 int frame_length, len = 0; 660 struct nbuf *frame; 661 uint16_t bd_status; 662 uchar buff[FEC_MAX_PKT_SIZE]; 663 664 /* 665 * Check if any critical events have happened 666 */ 667 ievent = readl(&fec->eth->ievent); 668 writel(ievent, &fec->eth->ievent); 669 debug("fec_recv: ievent 0x%lx\n", ievent); 670 if (ievent & FEC_IEVENT_BABR) { 671 fec_halt(dev); 672 fec_init(dev, fec->bd); 673 printf("some error: 0x%08lx\n", ievent); 674 return 0; 675 } 676 if (ievent & FEC_IEVENT_HBERR) { 677 /* Heartbeat error */ 678 writel(0x00000001 | readl(&fec->eth->x_cntrl), 679 &fec->eth->x_cntrl); 680 } 681 if (ievent & FEC_IEVENT_GRA) { 682 /* Graceful stop complete */ 683 if (readl(&fec->eth->x_cntrl) & 0x00000001) { 684 fec_halt(dev); 685 writel(~0x00000001 & readl(&fec->eth->x_cntrl), 686 &fec->eth->x_cntrl); 687 fec_init(dev, fec->bd); 688 } 689 } 690 691 /* 692 * ensure reading the right buffer status 693 */ 694 bd_status = readw(&rbd->status); 695 debug("fec_recv: status 0x%x\n", bd_status); 696 697 if (!(bd_status & FEC_RBD_EMPTY)) { 698 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) && 699 ((readw(&rbd->data_length) - 4) > 14)) { 700 /* 701 * Get buffer address and size 702 */ 703 frame = (struct nbuf *)readl(&rbd->data_pointer); 704 frame_length = readw(&rbd->data_length) - 4; 705 /* 706 * Fill the buffer and pass it to upper layers 707 */ 708 #ifdef CONFIG_FEC_MXC_SWAP_PACKET 709 swap_packet((uint32_t *)frame->data, frame_length); 710 #endif 711 memcpy(buff, frame->data, frame_length); 712 NetReceive(buff, frame_length); 713 len = frame_length; 714 } else { 715 if (bd_status & FEC_RBD_ERR) 716 printf("error frame: 0x%08lx 0x%08x\n", 717 (ulong)rbd->data_pointer, 718 bd_status); 719 } 720 /* 721 * free the current buffer, restart the engine 722 * and move forward to the next buffer 723 */ 724 fec_rbd_clean(fec->rbd_index == (FEC_RBD_NUM - 1) ? 1 : 0, rbd); 725 fec_rx_task_enable(fec); 726 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM; 727 } 728 debug("fec_recv: stop\n"); 729 730 return len; 731 } 732 733 static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr) 734 { 735 struct eth_device *edev; 736 struct fec_priv *fec; 737 unsigned char ethaddr[6]; 738 uint32_t start; 739 int ret = 0; 740 741 /* create and fill edev struct */ 742 edev = (struct eth_device *)malloc(sizeof(struct eth_device)); 743 if (!edev) { 744 puts("fec_mxc: not enough malloc memory for eth_device\n"); 745 ret = -ENOMEM; 746 goto err1; 747 } 748 749 fec = (struct fec_priv *)malloc(sizeof(struct fec_priv)); 750 if (!fec) { 751 puts("fec_mxc: not enough malloc memory for fec_priv\n"); 752 ret = -ENOMEM; 753 goto err2; 754 } 755 756 memset(edev, 0, sizeof(*edev)); 757 memset(fec, 0, sizeof(*fec)); 758 759 edev->priv = fec; 760 edev->init = fec_init; 761 edev->send = fec_send; 762 edev->recv = fec_recv; 763 edev->halt = fec_halt; 764 edev->write_hwaddr = fec_set_hwaddr; 765 766 fec->eth = (struct ethernet_regs *)base_addr; 767 fec->bd = bd; 768 769 fec->xcv_type = CONFIG_FEC_XCV_TYPE; 770 771 /* Reset chip. */ 772 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl); 773 start = get_timer(0); 774 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) { 775 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { 776 printf("FEC MXC: Timeout reseting chip\n"); 777 goto err3; 778 } 779 udelay(10); 780 } 781 782 /* 783 * Set interrupt mask register 784 */ 785 writel(0x00000000, &fec->eth->imask); 786 787 /* 788 * Clear FEC-Lite interrupt event register(IEVENT) 789 */ 790 writel(0xffffffff, &fec->eth->ievent); 791 792 /* 793 * Set FEC-Lite receive control register(R_CNTRL): 794 */ 795 /* 796 * Frame length=1518; MII mode; 797 */ 798 writel((PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT) | FEC_RCNTRL_FCE | 799 FEC_RCNTRL_MII_MODE, &fec->eth->r_cntrl); 800 fec_mii_setspeed(fec); 801 802 if (dev_id == -1) { 803 sprintf(edev->name, "FEC"); 804 fec->dev_id = 0; 805 } else { 806 sprintf(edev->name, "FEC%i", dev_id); 807 fec->dev_id = dev_id; 808 } 809 fec->phy_id = phy_id; 810 811 miiphy_register(edev->name, fec_miiphy_read, fec_miiphy_write); 812 813 eth_register(edev); 814 815 if (fec_get_hwaddr(edev, ethaddr) == 0) { 816 debug("got MAC address from fuse: %pM\n", ethaddr); 817 memcpy(edev->enetaddr, ethaddr, 6); 818 } 819 820 return ret; 821 822 err3: 823 free(fec); 824 err2: 825 free(edev); 826 err1: 827 return ret; 828 } 829 830 #ifndef CONFIG_FEC_MXC_MULTI 831 int fecmxc_initialize(bd_t *bd) 832 { 833 int lout = 1; 834 835 debug("eth_init: fec_probe(bd)\n"); 836 lout = fec_probe(bd, -1, CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); 837 838 return lout; 839 } 840 #endif 841 842 int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr) 843 { 844 int lout = 1; 845 846 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr); 847 lout = fec_probe(bd, dev_id, phy_id, addr); 848 849 return lout; 850 } 851 852 int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)) 853 { 854 struct fec_priv *fec = (struct fec_priv *)dev->priv; 855 fec->mii_postcall = cb; 856 return 0; 857 } 858