1 /* 2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com> 3 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org> 4 * (C) Copyright 2008 Armadeus Systems nc 5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <malloc.h> 26 #include <net.h> 27 #include <miiphy.h> 28 #include "fec_mxc.h" 29 30 #include <asm/arch/clock.h> 31 #include <asm/arch/imx-regs.h> 32 #include <asm/io.h> 33 #include <asm/errno.h> 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 #ifndef CONFIG_MII 38 #error "CONFIG_MII has to be defined!" 39 #endif 40 41 #ifndef CONFIG_FEC_XCV_TYPE 42 #define CONFIG_FEC_XCV_TYPE MII100 43 #endif 44 45 /* 46 * The i.MX28 operates with packets in big endian. We need to swap them before 47 * sending and after receiving. 48 */ 49 #ifdef CONFIG_MX28 50 #define CONFIG_FEC_MXC_SWAP_PACKET 51 #endif 52 53 #undef DEBUG 54 55 struct nbuf { 56 uint8_t data[1500]; /**< actual data */ 57 int length; /**< actual length */ 58 int used; /**< buffer in use or not */ 59 uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */ 60 }; 61 62 #ifdef CONFIG_FEC_MXC_SWAP_PACKET 63 static void swap_packet(uint32_t *packet, int length) 64 { 65 int i; 66 67 for (i = 0; i < DIV_ROUND_UP(length, 4); i++) 68 packet[i] = __swab32(packet[i]); 69 } 70 #endif 71 72 /* 73 * MII-interface related functions 74 */ 75 static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr, 76 uint8_t regAddr) 77 { 78 uint32_t reg; /* convenient holder for the PHY register */ 79 uint32_t phy; /* convenient holder for the PHY */ 80 uint32_t start; 81 int val; 82 83 /* 84 * reading from any PHY's register is done by properly 85 * programming the FEC's MII data register. 86 */ 87 writel(FEC_IEVENT_MII, ð->ievent); 88 reg = regAddr << FEC_MII_DATA_RA_SHIFT; 89 phy = phyAddr << FEC_MII_DATA_PA_SHIFT; 90 91 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | 92 phy | reg, ð->mii_data); 93 94 /* 95 * wait for the related interrupt 96 */ 97 start = get_timer(0); 98 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { 99 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { 100 printf("Read MDIO failed...\n"); 101 return -1; 102 } 103 } 104 105 /* 106 * clear mii interrupt bit 107 */ 108 writel(FEC_IEVENT_MII, ð->ievent); 109 110 /* 111 * it's now safe to read the PHY's register 112 */ 113 val = (unsigned short)readl(ð->mii_data); 114 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr, 115 regAddr, val); 116 return val; 117 } 118 119 static void fec_mii_setspeed(struct fec_priv *fec) 120 { 121 /* 122 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock 123 * and do not drop the Preamble. 124 */ 125 writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1, 126 &fec->eth->mii_speed); 127 debug("%s: mii_speed %08x\n", __func__, readl(&fec->eth->mii_speed)); 128 } 129 130 static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr, 131 uint8_t regAddr, uint16_t data) 132 { 133 uint32_t reg; /* convenient holder for the PHY register */ 134 uint32_t phy; /* convenient holder for the PHY */ 135 uint32_t start; 136 137 reg = regAddr << FEC_MII_DATA_RA_SHIFT; 138 phy = phyAddr << FEC_MII_DATA_PA_SHIFT; 139 140 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | 141 FEC_MII_DATA_TA | phy | reg | data, ð->mii_data); 142 143 /* 144 * wait for the MII interrupt 145 */ 146 start = get_timer(0); 147 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { 148 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { 149 printf("Write MDIO failed...\n"); 150 return -1; 151 } 152 } 153 154 /* 155 * clear MII interrupt bit 156 */ 157 writel(FEC_IEVENT_MII, ð->ievent); 158 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr, 159 regAddr, data); 160 161 return 0; 162 } 163 164 int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr) 165 { 166 return fec_mdio_read(bus->priv, phyAddr, regAddr); 167 } 168 169 int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr, 170 u16 data) 171 { 172 return fec_mdio_write(bus->priv, phyAddr, regAddr, data); 173 } 174 175 #ifndef CONFIG_PHYLIB 176 static int miiphy_restart_aneg(struct eth_device *dev) 177 { 178 struct fec_priv *fec = (struct fec_priv *)dev->priv; 179 struct ethernet_regs *eth = fec->bus->priv; 180 int ret = 0; 181 182 /* 183 * Wake up from sleep if necessary 184 * Reset PHY, then delay 300ns 185 */ 186 #ifdef CONFIG_MX27 187 fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF); 188 #endif 189 fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET); 190 udelay(1000); 191 192 /* 193 * Set the auto-negotiation advertisement register bits 194 */ 195 fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE, 196 LPA_100FULL | LPA_100HALF | LPA_10FULL | 197 LPA_10HALF | PHY_ANLPAR_PSB_802_3); 198 fec_mdio_write(eth, fec->phy_id, MII_BMCR, 199 BMCR_ANENABLE | BMCR_ANRESTART); 200 201 if (fec->mii_postcall) 202 ret = fec->mii_postcall(fec->phy_id); 203 204 return ret; 205 } 206 207 static int miiphy_wait_aneg(struct eth_device *dev) 208 { 209 uint32_t start; 210 int status; 211 struct fec_priv *fec = (struct fec_priv *)dev->priv; 212 struct ethernet_regs *eth = fec->bus->priv; 213 214 /* 215 * Wait for AN completion 216 */ 217 start = get_timer(0); 218 do { 219 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { 220 printf("%s: Autonegotiation timeout\n", dev->name); 221 return -1; 222 } 223 224 status = fec_mdio_read(eth, fec->phy_id, MII_BMSR); 225 if (status < 0) { 226 printf("%s: Autonegotiation failed. status: %d\n", 227 dev->name, status); 228 return -1; 229 } 230 } while (!(status & BMSR_LSTATUS)); 231 232 return 0; 233 } 234 #endif 235 236 static int fec_rx_task_enable(struct fec_priv *fec) 237 { 238 writel(1 << 24, &fec->eth->r_des_active); 239 return 0; 240 } 241 242 static int fec_rx_task_disable(struct fec_priv *fec) 243 { 244 return 0; 245 } 246 247 static int fec_tx_task_enable(struct fec_priv *fec) 248 { 249 writel(1 << 24, &fec->eth->x_des_active); 250 return 0; 251 } 252 253 static int fec_tx_task_disable(struct fec_priv *fec) 254 { 255 return 0; 256 } 257 258 /** 259 * Initialize receive task's buffer descriptors 260 * @param[in] fec all we know about the device yet 261 * @param[in] count receive buffer count to be allocated 262 * @param[in] size size of each receive buffer 263 * @return 0 on success 264 * 265 * For this task we need additional memory for the data buffers. And each 266 * data buffer requires some alignment. Thy must be aligned to a specific 267 * boundary each (DB_DATA_ALIGNMENT). 268 */ 269 static int fec_rbd_init(struct fec_priv *fec, int count, int size) 270 { 271 int ix; 272 uint32_t p = 0; 273 274 /* reserve data memory and consider alignment */ 275 if (fec->rdb_ptr == NULL) 276 fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT); 277 p = (uint32_t)fec->rdb_ptr; 278 if (!p) { 279 puts("fec_mxc: not enough malloc memory\n"); 280 return -ENOMEM; 281 } 282 memset((void *)p, 0, size * count + DB_DATA_ALIGNMENT); 283 p += DB_DATA_ALIGNMENT-1; 284 p &= ~(DB_DATA_ALIGNMENT-1); 285 286 for (ix = 0; ix < count; ix++) { 287 writel(p, &fec->rbd_base[ix].data_pointer); 288 p += size; 289 writew(FEC_RBD_EMPTY, &fec->rbd_base[ix].status); 290 writew(0, &fec->rbd_base[ix].data_length); 291 } 292 /* 293 * mark the last RBD to close the ring 294 */ 295 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[ix - 1].status); 296 fec->rbd_index = 0; 297 298 return 0; 299 } 300 301 /** 302 * Initialize transmit task's buffer descriptors 303 * @param[in] fec all we know about the device yet 304 * 305 * Transmit buffers are created externally. We only have to init the BDs here.\n 306 * Note: There is a race condition in the hardware. When only one BD is in 307 * use it must be marked with the WRAP bit to use it for every transmitt. 308 * This bit in combination with the READY bit results into double transmit 309 * of each data buffer. It seems the state machine checks READY earlier then 310 * resetting it after the first transfer. 311 * Using two BDs solves this issue. 312 */ 313 static void fec_tbd_init(struct fec_priv *fec) 314 { 315 writew(0x0000, &fec->tbd_base[0].status); 316 writew(FEC_TBD_WRAP, &fec->tbd_base[1].status); 317 fec->tbd_index = 0; 318 } 319 320 /** 321 * Mark the given read buffer descriptor as free 322 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0 323 * @param[in] pRbd buffer descriptor to mark free again 324 */ 325 static void fec_rbd_clean(int last, struct fec_bd *pRbd) 326 { 327 /* 328 * Reset buffer descriptor as empty 329 */ 330 if (last) 331 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &pRbd->status); 332 else 333 writew(FEC_RBD_EMPTY, &pRbd->status); 334 /* 335 * no data in it 336 */ 337 writew(0, &pRbd->data_length); 338 } 339 340 static int fec_get_hwaddr(struct eth_device *dev, int dev_id, 341 unsigned char *mac) 342 { 343 imx_get_mac_from_fuse(dev_id, mac); 344 return !is_valid_ether_addr(mac); 345 } 346 347 static int fec_set_hwaddr(struct eth_device *dev) 348 { 349 uchar *mac = dev->enetaddr; 350 struct fec_priv *fec = (struct fec_priv *)dev->priv; 351 352 writel(0, &fec->eth->iaddr1); 353 writel(0, &fec->eth->iaddr2); 354 writel(0, &fec->eth->gaddr1); 355 writel(0, &fec->eth->gaddr2); 356 357 /* 358 * Set physical address 359 */ 360 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3], 361 &fec->eth->paddr1); 362 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2); 363 364 return 0; 365 } 366 367 static void fec_eth_phy_config(struct eth_device *dev) 368 { 369 #ifdef CONFIG_PHYLIB 370 struct fec_priv *fec = (struct fec_priv *)dev->priv; 371 struct phy_device *phydev; 372 373 phydev = phy_connect(fec->bus, fec->phy_id, dev, 374 PHY_INTERFACE_MODE_RGMII); 375 if (phydev) { 376 fec->phydev = phydev; 377 phy_config(phydev); 378 } 379 #endif 380 } 381 382 /** 383 * Start the FEC engine 384 * @param[in] dev Our device to handle 385 */ 386 static int fec_open(struct eth_device *edev) 387 { 388 struct fec_priv *fec = (struct fec_priv *)edev->priv; 389 int speed; 390 391 debug("fec_open: fec_open(dev)\n"); 392 /* full-duplex, heartbeat disabled */ 393 writel(1 << 2, &fec->eth->x_cntrl); 394 fec->rbd_index = 0; 395 396 #ifdef FEC_QUIRK_ENET_MAC 397 /* Enable ENET HW endian SWAP */ 398 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP, 399 &fec->eth->ecntrl); 400 /* Enable ENET store and forward mode */ 401 writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD, 402 &fec->eth->x_wmrk); 403 #endif 404 /* 405 * Enable FEC-Lite controller 406 */ 407 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, 408 &fec->eth->ecntrl); 409 #if defined(CONFIG_MX25) || defined(CONFIG_MX53) 410 udelay(100); 411 /* 412 * setup the MII gasket for RMII mode 413 */ 414 415 /* disable the gasket */ 416 writew(0, &fec->eth->miigsk_enr); 417 418 /* wait for the gasket to be disabled */ 419 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) 420 udelay(2); 421 422 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */ 423 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr); 424 425 /* re-enable the gasket */ 426 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr); 427 428 /* wait until MII gasket is ready */ 429 int max_loops = 10; 430 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) { 431 if (--max_loops <= 0) { 432 printf("WAIT for MII Gasket ready timed out\n"); 433 break; 434 } 435 } 436 #endif 437 438 #ifdef CONFIG_PHYLIB 439 if (!fec->phydev) 440 fec_eth_phy_config(edev); 441 if (fec->phydev) { 442 /* Start up the PHY */ 443 phy_startup(fec->phydev); 444 speed = fec->phydev->speed; 445 } else { 446 speed = _100BASET; 447 } 448 #else 449 miiphy_wait_aneg(edev); 450 speed = miiphy_speed(edev->name, fec->phy_id); 451 miiphy_duplex(edev->name, fec->phy_id); 452 #endif 453 454 #ifdef FEC_QUIRK_ENET_MAC 455 { 456 u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED; 457 u32 rcr = (readl(&fec->eth->r_cntrl) & 458 ~(FEC_RCNTRL_RMII | FEC_RCNTRL_RMII_10T)) | 459 FEC_RCNTRL_RGMII | FEC_RCNTRL_MII_MODE; 460 if (speed == _1000BASET) 461 ecr |= FEC_ECNTRL_SPEED; 462 else if (speed != _100BASET) 463 rcr |= FEC_RCNTRL_RMII_10T; 464 writel(ecr, &fec->eth->ecntrl); 465 writel(rcr, &fec->eth->r_cntrl); 466 } 467 #endif 468 debug("%s:Speed=%i\n", __func__, speed); 469 470 /* 471 * Enable SmartDMA receive task 472 */ 473 fec_rx_task_enable(fec); 474 475 udelay(100000); 476 return 0; 477 } 478 479 static int fec_init(struct eth_device *dev, bd_t* bd) 480 { 481 uint32_t base; 482 struct fec_priv *fec = (struct fec_priv *)dev->priv; 483 uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop; 484 uint32_t rcntrl; 485 int i; 486 487 /* Initialize MAC address */ 488 fec_set_hwaddr(dev); 489 490 /* 491 * reserve memory for both buffer descriptor chains at once 492 * Datasheet forces the startaddress of each chain is 16 byte 493 * aligned 494 */ 495 if (fec->base_ptr == NULL) 496 fec->base_ptr = malloc((2 + FEC_RBD_NUM) * 497 sizeof(struct fec_bd) + DB_ALIGNMENT); 498 base = (uint32_t)fec->base_ptr; 499 if (!base) { 500 puts("fec_mxc: not enough malloc memory\n"); 501 return -ENOMEM; 502 } 503 memset((void *)base, 0, (2 + FEC_RBD_NUM) * 504 sizeof(struct fec_bd) + DB_ALIGNMENT); 505 base += (DB_ALIGNMENT-1); 506 base &= ~(DB_ALIGNMENT-1); 507 508 fec->rbd_base = (struct fec_bd *)base; 509 510 base += FEC_RBD_NUM * sizeof(struct fec_bd); 511 512 fec->tbd_base = (struct fec_bd *)base; 513 514 /* 515 * Set interrupt mask register 516 */ 517 writel(0x00000000, &fec->eth->imask); 518 519 /* 520 * Clear FEC-Lite interrupt event register(IEVENT) 521 */ 522 writel(0xffffffff, &fec->eth->ievent); 523 524 525 /* 526 * Set FEC-Lite receive control register(R_CNTRL): 527 */ 528 529 /* Start with frame length = 1518, common for all modes. */ 530 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT; 531 if (fec->xcv_type == SEVENWIRE) 532 rcntrl |= FEC_RCNTRL_FCE; 533 else if (fec->xcv_type == RGMII) 534 rcntrl |= FEC_RCNTRL_RGMII; 535 else if (fec->xcv_type == RMII) 536 rcntrl |= FEC_RCNTRL_RMII; 537 else /* MII mode */ 538 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE; 539 540 writel(rcntrl, &fec->eth->r_cntrl); 541 542 if (fec->xcv_type == MII10 || fec->xcv_type == MII100) 543 fec_mii_setspeed(fec); 544 545 /* 546 * Set Opcode/Pause Duration Register 547 */ 548 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */ 549 writel(0x2, &fec->eth->x_wmrk); 550 /* 551 * Set multicast address filter 552 */ 553 writel(0x00000000, &fec->eth->gaddr1); 554 writel(0x00000000, &fec->eth->gaddr2); 555 556 557 /* clear MIB RAM */ 558 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) 559 writel(0, i); 560 561 /* FIFO receive start register */ 562 writel(0x520, &fec->eth->r_fstart); 563 564 /* size and address of each buffer */ 565 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr); 566 writel((uint32_t)fec->tbd_base, &fec->eth->etdsr); 567 writel((uint32_t)fec->rbd_base, &fec->eth->erdsr); 568 569 /* 570 * Initialize RxBD/TxBD rings 571 */ 572 if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) { 573 free(fec->base_ptr); 574 fec->base_ptr = NULL; 575 return -ENOMEM; 576 } 577 fec_tbd_init(fec); 578 579 580 #ifndef CONFIG_PHYLIB 581 if (fec->xcv_type != SEVENWIRE) 582 miiphy_restart_aneg(dev); 583 #endif 584 fec_open(dev); 585 return 0; 586 } 587 588 /** 589 * Halt the FEC engine 590 * @param[in] dev Our device to handle 591 */ 592 static void fec_halt(struct eth_device *dev) 593 { 594 struct fec_priv *fec = (struct fec_priv *)dev->priv; 595 int counter = 0xffff; 596 597 /* 598 * issue graceful stop command to the FEC transmitter if necessary 599 */ 600 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl), 601 &fec->eth->x_cntrl); 602 603 debug("eth_halt: wait for stop regs\n"); 604 /* 605 * wait for graceful stop to register 606 */ 607 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA))) 608 udelay(1); 609 610 /* 611 * Disable SmartDMA tasks 612 */ 613 fec_tx_task_disable(fec); 614 fec_rx_task_disable(fec); 615 616 /* 617 * Disable the Ethernet Controller 618 * Note: this will also reset the BD index counter! 619 */ 620 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN, 621 &fec->eth->ecntrl); 622 fec->rbd_index = 0; 623 fec->tbd_index = 0; 624 debug("eth_halt: done\n"); 625 } 626 627 /** 628 * Transmit one frame 629 * @param[in] dev Our ethernet device to handle 630 * @param[in] packet Pointer to the data to be transmitted 631 * @param[in] length Data count in bytes 632 * @return 0 on success 633 */ 634 static int fec_send(struct eth_device *dev, volatile void* packet, int length) 635 { 636 unsigned int status; 637 638 /* 639 * This routine transmits one frame. This routine only accepts 640 * 6-byte Ethernet addresses. 641 */ 642 struct fec_priv *fec = (struct fec_priv *)dev->priv; 643 644 /* 645 * Check for valid length of data. 646 */ 647 if ((length > 1500) || (length <= 0)) { 648 printf("Payload (%d) too large\n", length); 649 return -1; 650 } 651 652 /* 653 * Setup the transmit buffer 654 * Note: We are always using the first buffer for transmission, 655 * the second will be empty and only used to stop the DMA engine 656 */ 657 #ifdef CONFIG_FEC_MXC_SWAP_PACKET 658 swap_packet((uint32_t *)packet, length); 659 #endif 660 writew(length, &fec->tbd_base[fec->tbd_index].data_length); 661 writel((uint32_t)packet, &fec->tbd_base[fec->tbd_index].data_pointer); 662 /* 663 * update BD's status now 664 * This block: 665 * - is always the last in a chain (means no chain) 666 * - should transmitt the CRC 667 * - might be the last BD in the list, so the address counter should 668 * wrap (-> keep the WRAP flag) 669 */ 670 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP; 671 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; 672 writew(status, &fec->tbd_base[fec->tbd_index].status); 673 674 /* 675 * Enable SmartDMA transmit task 676 */ 677 fec_tx_task_enable(fec); 678 679 /* 680 * wait until frame is sent . 681 */ 682 while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) { 683 udelay(1); 684 } 685 debug("fec_send: status 0x%x index %d\n", 686 readw(&fec->tbd_base[fec->tbd_index].status), 687 fec->tbd_index); 688 /* for next transmission use the other buffer */ 689 if (fec->tbd_index) 690 fec->tbd_index = 0; 691 else 692 fec->tbd_index = 1; 693 694 return 0; 695 } 696 697 /** 698 * Pull one frame from the card 699 * @param[in] dev Our ethernet device to handle 700 * @return Length of packet read 701 */ 702 static int fec_recv(struct eth_device *dev) 703 { 704 struct fec_priv *fec = (struct fec_priv *)dev->priv; 705 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index]; 706 unsigned long ievent; 707 int frame_length, len = 0; 708 struct nbuf *frame; 709 uint16_t bd_status; 710 uchar buff[FEC_MAX_PKT_SIZE]; 711 712 /* 713 * Check if any critical events have happened 714 */ 715 ievent = readl(&fec->eth->ievent); 716 writel(ievent, &fec->eth->ievent); 717 debug("fec_recv: ievent 0x%lx\n", ievent); 718 if (ievent & FEC_IEVENT_BABR) { 719 fec_halt(dev); 720 fec_init(dev, fec->bd); 721 printf("some error: 0x%08lx\n", ievent); 722 return 0; 723 } 724 if (ievent & FEC_IEVENT_HBERR) { 725 /* Heartbeat error */ 726 writel(0x00000001 | readl(&fec->eth->x_cntrl), 727 &fec->eth->x_cntrl); 728 } 729 if (ievent & FEC_IEVENT_GRA) { 730 /* Graceful stop complete */ 731 if (readl(&fec->eth->x_cntrl) & 0x00000001) { 732 fec_halt(dev); 733 writel(~0x00000001 & readl(&fec->eth->x_cntrl), 734 &fec->eth->x_cntrl); 735 fec_init(dev, fec->bd); 736 } 737 } 738 739 /* 740 * ensure reading the right buffer status 741 */ 742 bd_status = readw(&rbd->status); 743 debug("fec_recv: status 0x%x\n", bd_status); 744 745 if (!(bd_status & FEC_RBD_EMPTY)) { 746 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) && 747 ((readw(&rbd->data_length) - 4) > 14)) { 748 /* 749 * Get buffer address and size 750 */ 751 frame = (struct nbuf *)readl(&rbd->data_pointer); 752 frame_length = readw(&rbd->data_length) - 4; 753 /* 754 * Fill the buffer and pass it to upper layers 755 */ 756 #ifdef CONFIG_FEC_MXC_SWAP_PACKET 757 swap_packet((uint32_t *)frame->data, frame_length); 758 #endif 759 memcpy(buff, frame->data, frame_length); 760 NetReceive(buff, frame_length); 761 len = frame_length; 762 } else { 763 if (bd_status & FEC_RBD_ERR) 764 printf("error frame: 0x%08lx 0x%08x\n", 765 (ulong)rbd->data_pointer, 766 bd_status); 767 } 768 /* 769 * free the current buffer, restart the engine 770 * and move forward to the next buffer 771 */ 772 fec_rbd_clean(fec->rbd_index == (FEC_RBD_NUM - 1) ? 1 : 0, rbd); 773 fec_rx_task_enable(fec); 774 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM; 775 } 776 debug("fec_recv: stop\n"); 777 778 return len; 779 } 780 781 static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr) 782 { 783 struct eth_device *edev; 784 struct fec_priv *fec; 785 struct mii_dev *bus; 786 unsigned char ethaddr[6]; 787 uint32_t start; 788 int ret = 0; 789 790 /* create and fill edev struct */ 791 edev = (struct eth_device *)malloc(sizeof(struct eth_device)); 792 if (!edev) { 793 puts("fec_mxc: not enough malloc memory for eth_device\n"); 794 ret = -ENOMEM; 795 goto err1; 796 } 797 798 fec = (struct fec_priv *)malloc(sizeof(struct fec_priv)); 799 if (!fec) { 800 puts("fec_mxc: not enough malloc memory for fec_priv\n"); 801 ret = -ENOMEM; 802 goto err2; 803 } 804 805 memset(edev, 0, sizeof(*edev)); 806 memset(fec, 0, sizeof(*fec)); 807 808 edev->priv = fec; 809 edev->init = fec_init; 810 edev->send = fec_send; 811 edev->recv = fec_recv; 812 edev->halt = fec_halt; 813 edev->write_hwaddr = fec_set_hwaddr; 814 815 fec->eth = (struct ethernet_regs *)base_addr; 816 fec->bd = bd; 817 818 fec->xcv_type = CONFIG_FEC_XCV_TYPE; 819 820 /* Reset chip. */ 821 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl); 822 start = get_timer(0); 823 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) { 824 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { 825 printf("FEC MXC: Timeout reseting chip\n"); 826 goto err3; 827 } 828 udelay(10); 829 } 830 831 /* 832 * Set interrupt mask register 833 */ 834 writel(0x00000000, &fec->eth->imask); 835 836 /* 837 * Clear FEC-Lite interrupt event register(IEVENT) 838 */ 839 writel(0xffffffff, &fec->eth->ievent); 840 841 /* 842 * Set FEC-Lite receive control register(R_CNTRL): 843 */ 844 /* 845 * Frame length=1518; MII mode; 846 */ 847 writel((PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT) | FEC_RCNTRL_FCE | 848 FEC_RCNTRL_MII_MODE, &fec->eth->r_cntrl); 849 fec_mii_setspeed(fec); 850 851 if (dev_id == -1) { 852 sprintf(edev->name, "FEC"); 853 fec->dev_id = 0; 854 } else { 855 sprintf(edev->name, "FEC%i", dev_id); 856 fec->dev_id = dev_id; 857 } 858 fec->phy_id = phy_id; 859 860 bus = mdio_alloc(); 861 if (!bus) { 862 printf("mdio_alloc failed\n"); 863 ret = -ENOMEM; 864 goto err3; 865 } 866 bus->read = fec_phy_read; 867 bus->write = fec_phy_write; 868 sprintf(bus->name, edev->name); 869 #ifdef CONFIG_MX28 870 /* 871 * The i.MX28 has two ethernet interfaces, but they are not equal. 872 * Only the first one can access the MDIO bus. 873 */ 874 bus->priv = (struct ethernet_regs *)MXS_ENET0_BASE; 875 #else 876 bus->priv = fec->eth; 877 #endif 878 ret = mdio_register(bus); 879 if (ret) { 880 printf("mdio_register failed\n"); 881 free(bus); 882 ret = -ENOMEM; 883 goto err3; 884 } 885 fec->bus = bus; 886 eth_register(edev); 887 888 if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) { 889 debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr); 890 memcpy(edev->enetaddr, ethaddr, 6); 891 } 892 /* Configure phy */ 893 fec_eth_phy_config(edev); 894 return ret; 895 896 err3: 897 free(fec); 898 err2: 899 free(edev); 900 err1: 901 return ret; 902 } 903 904 #ifndef CONFIG_FEC_MXC_MULTI 905 int fecmxc_initialize(bd_t *bd) 906 { 907 int lout = 1; 908 909 debug("eth_init: fec_probe(bd)\n"); 910 lout = fec_probe(bd, -1, CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); 911 912 return lout; 913 } 914 #endif 915 916 int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr) 917 { 918 int lout = 1; 919 920 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr); 921 lout = fec_probe(bd, dev_id, phy_id, addr); 922 923 return lout; 924 } 925 926 #ifndef CONFIG_PHYLIB 927 int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)) 928 { 929 struct fec_priv *fec = (struct fec_priv *)dev->priv; 930 fec->mii_postcall = cb; 931 return 0; 932 } 933 #endif 934