1 /* 2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com> 3 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org> 4 * (C) Copyright 2008 Armadeus Systems nc 5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <malloc.h> 26 #include <net.h> 27 #include <miiphy.h> 28 #include "fec_mxc.h" 29 30 #include <asm/arch/clock.h> 31 #include <asm/arch/imx-regs.h> 32 #include <asm/io.h> 33 #include <asm/errno.h> 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 #ifndef CONFIG_MII 38 #error "CONFIG_MII has to be defined!" 39 #endif 40 41 #ifndef CONFIG_FEC_XCV_TYPE 42 #define CONFIG_FEC_XCV_TYPE MII100 43 #endif 44 45 /* 46 * The i.MX28 operates with packets in big endian. We need to swap them before 47 * sending and after receiving. 48 */ 49 #ifdef CONFIG_MX28 50 #define CONFIG_FEC_MXC_SWAP_PACKET 51 #endif 52 53 #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd)) 54 55 /* Check various alignment issues at compile time */ 56 #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0)) 57 #error "ARCH_DMA_MINALIGN must be multiple of 16!" 58 #endif 59 60 #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \ 61 (PKTALIGN % ARCH_DMA_MINALIGN != 0)) 62 #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!" 63 #endif 64 65 #undef DEBUG 66 67 struct nbuf { 68 uint8_t data[1500]; /**< actual data */ 69 int length; /**< actual length */ 70 int used; /**< buffer in use or not */ 71 uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */ 72 }; 73 74 #ifdef CONFIG_FEC_MXC_SWAP_PACKET 75 static void swap_packet(uint32_t *packet, int length) 76 { 77 int i; 78 79 for (i = 0; i < DIV_ROUND_UP(length, 4); i++) 80 packet[i] = __swab32(packet[i]); 81 } 82 #endif 83 84 /* 85 * MII-interface related functions 86 */ 87 static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr, 88 uint8_t regAddr) 89 { 90 uint32_t reg; /* convenient holder for the PHY register */ 91 uint32_t phy; /* convenient holder for the PHY */ 92 uint32_t start; 93 int val; 94 95 /* 96 * reading from any PHY's register is done by properly 97 * programming the FEC's MII data register. 98 */ 99 writel(FEC_IEVENT_MII, ð->ievent); 100 reg = regAddr << FEC_MII_DATA_RA_SHIFT; 101 phy = phyAddr << FEC_MII_DATA_PA_SHIFT; 102 103 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | 104 phy | reg, ð->mii_data); 105 106 /* 107 * wait for the related interrupt 108 */ 109 start = get_timer(0); 110 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { 111 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { 112 printf("Read MDIO failed...\n"); 113 return -1; 114 } 115 } 116 117 /* 118 * clear mii interrupt bit 119 */ 120 writel(FEC_IEVENT_MII, ð->ievent); 121 122 /* 123 * it's now safe to read the PHY's register 124 */ 125 val = (unsigned short)readl(ð->mii_data); 126 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr, 127 regAddr, val); 128 return val; 129 } 130 131 static void fec_mii_setspeed(struct fec_priv *fec) 132 { 133 /* 134 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock 135 * and do not drop the Preamble. 136 */ 137 writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1, 138 &fec->eth->mii_speed); 139 debug("%s: mii_speed %08x\n", __func__, readl(&fec->eth->mii_speed)); 140 } 141 142 static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr, 143 uint8_t regAddr, uint16_t data) 144 { 145 uint32_t reg; /* convenient holder for the PHY register */ 146 uint32_t phy; /* convenient holder for the PHY */ 147 uint32_t start; 148 149 reg = regAddr << FEC_MII_DATA_RA_SHIFT; 150 phy = phyAddr << FEC_MII_DATA_PA_SHIFT; 151 152 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | 153 FEC_MII_DATA_TA | phy | reg | data, ð->mii_data); 154 155 /* 156 * wait for the MII interrupt 157 */ 158 start = get_timer(0); 159 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { 160 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { 161 printf("Write MDIO failed...\n"); 162 return -1; 163 } 164 } 165 166 /* 167 * clear MII interrupt bit 168 */ 169 writel(FEC_IEVENT_MII, ð->ievent); 170 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr, 171 regAddr, data); 172 173 return 0; 174 } 175 176 int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr) 177 { 178 return fec_mdio_read(bus->priv, phyAddr, regAddr); 179 } 180 181 int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr, 182 u16 data) 183 { 184 return fec_mdio_write(bus->priv, phyAddr, regAddr, data); 185 } 186 187 #ifndef CONFIG_PHYLIB 188 static int miiphy_restart_aneg(struct eth_device *dev) 189 { 190 int ret = 0; 191 #if !defined(CONFIG_FEC_MXC_NO_ANEG) 192 struct fec_priv *fec = (struct fec_priv *)dev->priv; 193 struct ethernet_regs *eth = fec->bus->priv; 194 195 /* 196 * Wake up from sleep if necessary 197 * Reset PHY, then delay 300ns 198 */ 199 #ifdef CONFIG_MX27 200 fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF); 201 #endif 202 fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET); 203 udelay(1000); 204 205 /* 206 * Set the auto-negotiation advertisement register bits 207 */ 208 fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE, 209 LPA_100FULL | LPA_100HALF | LPA_10FULL | 210 LPA_10HALF | PHY_ANLPAR_PSB_802_3); 211 fec_mdio_write(eth, fec->phy_id, MII_BMCR, 212 BMCR_ANENABLE | BMCR_ANRESTART); 213 214 if (fec->mii_postcall) 215 ret = fec->mii_postcall(fec->phy_id); 216 217 #endif 218 return ret; 219 } 220 221 static int miiphy_wait_aneg(struct eth_device *dev) 222 { 223 uint32_t start; 224 int status; 225 struct fec_priv *fec = (struct fec_priv *)dev->priv; 226 struct ethernet_regs *eth = fec->bus->priv; 227 228 /* 229 * Wait for AN completion 230 */ 231 start = get_timer(0); 232 do { 233 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { 234 printf("%s: Autonegotiation timeout\n", dev->name); 235 return -1; 236 } 237 238 status = fec_mdio_read(eth, fec->phy_id, MII_BMSR); 239 if (status < 0) { 240 printf("%s: Autonegotiation failed. status: %d\n", 241 dev->name, status); 242 return -1; 243 } 244 } while (!(status & BMSR_LSTATUS)); 245 246 return 0; 247 } 248 #endif 249 250 static int fec_rx_task_enable(struct fec_priv *fec) 251 { 252 writel(1 << 24, &fec->eth->r_des_active); 253 return 0; 254 } 255 256 static int fec_rx_task_disable(struct fec_priv *fec) 257 { 258 return 0; 259 } 260 261 static int fec_tx_task_enable(struct fec_priv *fec) 262 { 263 writel(1 << 24, &fec->eth->x_des_active); 264 return 0; 265 } 266 267 static int fec_tx_task_disable(struct fec_priv *fec) 268 { 269 return 0; 270 } 271 272 /** 273 * Initialize receive task's buffer descriptors 274 * @param[in] fec all we know about the device yet 275 * @param[in] count receive buffer count to be allocated 276 * @param[in] dsize desired size of each receive buffer 277 * @return 0 on success 278 * 279 * For this task we need additional memory for the data buffers. And each 280 * data buffer requires some alignment. Thy must be aligned to a specific 281 * boundary each. 282 */ 283 static int fec_rbd_init(struct fec_priv *fec, int count, int dsize) 284 { 285 uint32_t size; 286 int i; 287 288 /* 289 * Allocate memory for the buffers. This allocation respects the 290 * alignment 291 */ 292 size = roundup(dsize, ARCH_DMA_MINALIGN); 293 for (i = 0; i < count; i++) { 294 uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer); 295 if (data_ptr == 0) { 296 uint8_t *data = memalign(ARCH_DMA_MINALIGN, 297 size); 298 if (!data) { 299 printf("%s: error allocating rxbuf %d\n", 300 __func__, i); 301 goto err; 302 } 303 writel((uint32_t)data, &fec->rbd_base[i].data_pointer); 304 } /* needs allocation */ 305 writew(FEC_RBD_EMPTY, &fec->rbd_base[i].status); 306 writew(0, &fec->rbd_base[i].data_length); 307 } 308 309 /* Mark the last RBD to close the ring. */ 310 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[i - 1].status); 311 fec->rbd_index = 0; 312 313 return 0; 314 315 err: 316 for (; i >= 0; i--) { 317 uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer); 318 free((void *)data_ptr); 319 } 320 321 return -ENOMEM; 322 } 323 324 /** 325 * Initialize transmit task's buffer descriptors 326 * @param[in] fec all we know about the device yet 327 * 328 * Transmit buffers are created externally. We only have to init the BDs here.\n 329 * Note: There is a race condition in the hardware. When only one BD is in 330 * use it must be marked with the WRAP bit to use it for every transmitt. 331 * This bit in combination with the READY bit results into double transmit 332 * of each data buffer. It seems the state machine checks READY earlier then 333 * resetting it after the first transfer. 334 * Using two BDs solves this issue. 335 */ 336 static void fec_tbd_init(struct fec_priv *fec) 337 { 338 unsigned addr = (unsigned)fec->tbd_base; 339 unsigned size = roundup(2 * sizeof(struct fec_bd), 340 ARCH_DMA_MINALIGN); 341 writew(0x0000, &fec->tbd_base[0].status); 342 writew(FEC_TBD_WRAP, &fec->tbd_base[1].status); 343 fec->tbd_index = 0; 344 flush_dcache_range(addr, addr+size); 345 } 346 347 /** 348 * Mark the given read buffer descriptor as free 349 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0 350 * @param[in] pRbd buffer descriptor to mark free again 351 */ 352 static void fec_rbd_clean(int last, struct fec_bd *pRbd) 353 { 354 unsigned short flags = FEC_RBD_EMPTY; 355 if (last) 356 flags |= FEC_RBD_WRAP; 357 writew(flags, &pRbd->status); 358 writew(0, &pRbd->data_length); 359 } 360 361 static int fec_get_hwaddr(struct eth_device *dev, int dev_id, 362 unsigned char *mac) 363 { 364 imx_get_mac_from_fuse(dev_id, mac); 365 return !is_valid_ether_addr(mac); 366 } 367 368 static int fec_set_hwaddr(struct eth_device *dev) 369 { 370 uchar *mac = dev->enetaddr; 371 struct fec_priv *fec = (struct fec_priv *)dev->priv; 372 373 writel(0, &fec->eth->iaddr1); 374 writel(0, &fec->eth->iaddr2); 375 writel(0, &fec->eth->gaddr1); 376 writel(0, &fec->eth->gaddr2); 377 378 /* 379 * Set physical address 380 */ 381 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3], 382 &fec->eth->paddr1); 383 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2); 384 385 return 0; 386 } 387 388 static void fec_eth_phy_config(struct eth_device *dev) 389 { 390 #ifdef CONFIG_PHYLIB 391 struct fec_priv *fec = (struct fec_priv *)dev->priv; 392 struct phy_device *phydev; 393 394 phydev = phy_connect(fec->bus, fec->phy_id, dev, 395 PHY_INTERFACE_MODE_RGMII); 396 if (phydev) { 397 fec->phydev = phydev; 398 phy_config(phydev); 399 } 400 #endif 401 } 402 403 /* 404 * Do initial configuration of the FEC registers 405 */ 406 static void fec_reg_setup(struct fec_priv *fec) 407 { 408 uint32_t rcntrl; 409 410 /* 411 * Set interrupt mask register 412 */ 413 writel(0x00000000, &fec->eth->imask); 414 415 /* 416 * Clear FEC-Lite interrupt event register(IEVENT) 417 */ 418 writel(0xffffffff, &fec->eth->ievent); 419 420 421 /* 422 * Set FEC-Lite receive control register(R_CNTRL): 423 */ 424 425 /* Start with frame length = 1518, common for all modes. */ 426 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT; 427 if (fec->xcv_type != SEVENWIRE) /* xMII modes */ 428 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE; 429 if (fec->xcv_type == RGMII) 430 rcntrl |= FEC_RCNTRL_RGMII; 431 else if (fec->xcv_type == RMII) 432 rcntrl |= FEC_RCNTRL_RMII; 433 434 writel(rcntrl, &fec->eth->r_cntrl); 435 } 436 437 /** 438 * Start the FEC engine 439 * @param[in] dev Our device to handle 440 */ 441 static int fec_open(struct eth_device *edev) 442 { 443 struct fec_priv *fec = (struct fec_priv *)edev->priv; 444 int speed; 445 uint32_t addr, size; 446 int i; 447 448 debug("fec_open: fec_open(dev)\n"); 449 /* full-duplex, heartbeat disabled */ 450 writel(1 << 2, &fec->eth->x_cntrl); 451 fec->rbd_index = 0; 452 453 /* Invalidate all descriptors */ 454 for (i = 0; i < FEC_RBD_NUM - 1; i++) 455 fec_rbd_clean(0, &fec->rbd_base[i]); 456 fec_rbd_clean(1, &fec->rbd_base[i]); 457 458 /* Flush the descriptors into RAM */ 459 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), 460 ARCH_DMA_MINALIGN); 461 addr = (uint32_t)fec->rbd_base; 462 flush_dcache_range(addr, addr + size); 463 464 #ifdef FEC_QUIRK_ENET_MAC 465 /* Enable ENET HW endian SWAP */ 466 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP, 467 &fec->eth->ecntrl); 468 /* Enable ENET store and forward mode */ 469 writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD, 470 &fec->eth->x_wmrk); 471 #endif 472 /* 473 * Enable FEC-Lite controller 474 */ 475 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, 476 &fec->eth->ecntrl); 477 #if defined(CONFIG_MX25) || defined(CONFIG_MX53) 478 udelay(100); 479 /* 480 * setup the MII gasket for RMII mode 481 */ 482 483 /* disable the gasket */ 484 writew(0, &fec->eth->miigsk_enr); 485 486 /* wait for the gasket to be disabled */ 487 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) 488 udelay(2); 489 490 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */ 491 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr); 492 493 /* re-enable the gasket */ 494 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr); 495 496 /* wait until MII gasket is ready */ 497 int max_loops = 10; 498 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) { 499 if (--max_loops <= 0) { 500 printf("WAIT for MII Gasket ready timed out\n"); 501 break; 502 } 503 } 504 #endif 505 506 #ifdef CONFIG_PHYLIB 507 if (!fec->phydev) 508 fec_eth_phy_config(edev); 509 if (fec->phydev) { 510 /* Start up the PHY */ 511 int ret = phy_startup(fec->phydev); 512 513 if (ret) { 514 printf("Could not initialize PHY %s\n", 515 fec->phydev->dev->name); 516 return ret; 517 } 518 speed = fec->phydev->speed; 519 } else { 520 speed = _100BASET; 521 } 522 #else 523 miiphy_wait_aneg(edev); 524 speed = miiphy_speed(edev->name, fec->phy_id); 525 miiphy_duplex(edev->name, fec->phy_id); 526 #endif 527 528 #ifdef FEC_QUIRK_ENET_MAC 529 { 530 u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED; 531 u32 rcr = (readl(&fec->eth->r_cntrl) & 532 ~(FEC_RCNTRL_RMII | FEC_RCNTRL_RMII_10T)) | 533 FEC_RCNTRL_RGMII | FEC_RCNTRL_MII_MODE; 534 if (speed == _1000BASET) 535 ecr |= FEC_ECNTRL_SPEED; 536 else if (speed != _100BASET) 537 rcr |= FEC_RCNTRL_RMII_10T; 538 writel(ecr, &fec->eth->ecntrl); 539 writel(rcr, &fec->eth->r_cntrl); 540 } 541 #endif 542 debug("%s:Speed=%i\n", __func__, speed); 543 544 /* 545 * Enable SmartDMA receive task 546 */ 547 fec_rx_task_enable(fec); 548 549 udelay(100000); 550 return 0; 551 } 552 553 static int fec_init(struct eth_device *dev, bd_t* bd) 554 { 555 struct fec_priv *fec = (struct fec_priv *)dev->priv; 556 uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop; 557 uint32_t size; 558 int i, ret; 559 560 /* Initialize MAC address */ 561 fec_set_hwaddr(dev); 562 563 /* 564 * Allocate transmit descriptors, there are two in total. This 565 * allocation respects cache alignment. 566 */ 567 if (!fec->tbd_base) { 568 size = roundup(2 * sizeof(struct fec_bd), 569 ARCH_DMA_MINALIGN); 570 fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size); 571 if (!fec->tbd_base) { 572 ret = -ENOMEM; 573 goto err1; 574 } 575 memset(fec->tbd_base, 0, size); 576 fec_tbd_init(fec); 577 flush_dcache_range((unsigned)fec->tbd_base, size); 578 } 579 580 /* 581 * Allocate receive descriptors. This allocation respects cache 582 * alignment. 583 */ 584 if (!fec->rbd_base) { 585 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), 586 ARCH_DMA_MINALIGN); 587 fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size); 588 if (!fec->rbd_base) { 589 ret = -ENOMEM; 590 goto err2; 591 } 592 memset(fec->rbd_base, 0, size); 593 /* 594 * Initialize RxBD ring 595 */ 596 if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) { 597 ret = -ENOMEM; 598 goto err3; 599 } 600 flush_dcache_range((unsigned)fec->rbd_base, 601 (unsigned)fec->rbd_base + size); 602 } 603 604 fec_reg_setup(fec); 605 606 if (fec->xcv_type != SEVENWIRE) 607 fec_mii_setspeed(fec); 608 609 /* 610 * Set Opcode/Pause Duration Register 611 */ 612 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */ 613 writel(0x2, &fec->eth->x_wmrk); 614 /* 615 * Set multicast address filter 616 */ 617 writel(0x00000000, &fec->eth->gaddr1); 618 writel(0x00000000, &fec->eth->gaddr2); 619 620 621 /* clear MIB RAM */ 622 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) 623 writel(0, i); 624 625 /* FIFO receive start register */ 626 writel(0x520, &fec->eth->r_fstart); 627 628 /* size and address of each buffer */ 629 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr); 630 writel((uint32_t)fec->tbd_base, &fec->eth->etdsr); 631 writel((uint32_t)fec->rbd_base, &fec->eth->erdsr); 632 633 #ifndef CONFIG_PHYLIB 634 if (fec->xcv_type != SEVENWIRE) 635 miiphy_restart_aneg(dev); 636 #endif 637 fec_open(dev); 638 return 0; 639 640 err3: 641 free(fec->rbd_base); 642 err2: 643 free(fec->tbd_base); 644 err1: 645 return ret; 646 } 647 648 /** 649 * Halt the FEC engine 650 * @param[in] dev Our device to handle 651 */ 652 static void fec_halt(struct eth_device *dev) 653 { 654 struct fec_priv *fec = (struct fec_priv *)dev->priv; 655 int counter = 0xffff; 656 657 /* 658 * issue graceful stop command to the FEC transmitter if necessary 659 */ 660 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl), 661 &fec->eth->x_cntrl); 662 663 debug("eth_halt: wait for stop regs\n"); 664 /* 665 * wait for graceful stop to register 666 */ 667 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA))) 668 udelay(1); 669 670 /* 671 * Disable SmartDMA tasks 672 */ 673 fec_tx_task_disable(fec); 674 fec_rx_task_disable(fec); 675 676 /* 677 * Disable the Ethernet Controller 678 * Note: this will also reset the BD index counter! 679 */ 680 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN, 681 &fec->eth->ecntrl); 682 fec->rbd_index = 0; 683 fec->tbd_index = 0; 684 debug("eth_halt: done\n"); 685 } 686 687 /** 688 * Transmit one frame 689 * @param[in] dev Our ethernet device to handle 690 * @param[in] packet Pointer to the data to be transmitted 691 * @param[in] length Data count in bytes 692 * @return 0 on success 693 */ 694 static int fec_send(struct eth_device *dev, void *packet, int length) 695 { 696 unsigned int status; 697 uint32_t size; 698 uint32_t addr; 699 700 /* 701 * This routine transmits one frame. This routine only accepts 702 * 6-byte Ethernet addresses. 703 */ 704 struct fec_priv *fec = (struct fec_priv *)dev->priv; 705 706 /* 707 * Check for valid length of data. 708 */ 709 if ((length > 1500) || (length <= 0)) { 710 printf("Payload (%d) too large\n", length); 711 return -1; 712 } 713 714 /* 715 * Setup the transmit buffer. We are always using the first buffer for 716 * transmission, the second will be empty and only used to stop the DMA 717 * engine. We also flush the packet to RAM here to avoid cache trouble. 718 */ 719 #ifdef CONFIG_FEC_MXC_SWAP_PACKET 720 swap_packet((uint32_t *)packet, length); 721 #endif 722 723 addr = (uint32_t)packet; 724 size = roundup(length, ARCH_DMA_MINALIGN); 725 flush_dcache_range(addr, addr + size); 726 727 writew(length, &fec->tbd_base[fec->tbd_index].data_length); 728 writel(addr, &fec->tbd_base[fec->tbd_index].data_pointer); 729 730 /* 731 * update BD's status now 732 * This block: 733 * - is always the last in a chain (means no chain) 734 * - should transmitt the CRC 735 * - might be the last BD in the list, so the address counter should 736 * wrap (-> keep the WRAP flag) 737 */ 738 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP; 739 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; 740 writew(status, &fec->tbd_base[fec->tbd_index].status); 741 742 /* 743 * Flush data cache. This code flushes both TX descriptors to RAM. 744 * After this code, the descriptors will be safely in RAM and we 745 * can start DMA. 746 */ 747 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); 748 addr = (uint32_t)fec->tbd_base; 749 flush_dcache_range(addr, addr + size); 750 751 /* 752 * Enable SmartDMA transmit task 753 */ 754 fec_tx_task_enable(fec); 755 756 /* 757 * Wait until frame is sent. On each turn of the wait cycle, we must 758 * invalidate data cache to see what's really in RAM. Also, we need 759 * barrier here. 760 */ 761 invalidate_dcache_range(addr, addr + size); 762 while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) { 763 udelay(1); 764 invalidate_dcache_range(addr, addr + size); 765 } 766 767 debug("fec_send: status 0x%x index %d\n", 768 readw(&fec->tbd_base[fec->tbd_index].status), 769 fec->tbd_index); 770 /* for next transmission use the other buffer */ 771 if (fec->tbd_index) 772 fec->tbd_index = 0; 773 else 774 fec->tbd_index = 1; 775 776 return 0; 777 } 778 779 /** 780 * Pull one frame from the card 781 * @param[in] dev Our ethernet device to handle 782 * @return Length of packet read 783 */ 784 static int fec_recv(struct eth_device *dev) 785 { 786 struct fec_priv *fec = (struct fec_priv *)dev->priv; 787 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index]; 788 unsigned long ievent; 789 int frame_length, len = 0; 790 struct nbuf *frame; 791 uint16_t bd_status; 792 uint32_t addr, size; 793 int i; 794 uchar buff[FEC_MAX_PKT_SIZE]; 795 796 /* 797 * Check if any critical events have happened 798 */ 799 ievent = readl(&fec->eth->ievent); 800 writel(ievent, &fec->eth->ievent); 801 debug("fec_recv: ievent 0x%lx\n", ievent); 802 if (ievent & FEC_IEVENT_BABR) { 803 fec_halt(dev); 804 fec_init(dev, fec->bd); 805 printf("some error: 0x%08lx\n", ievent); 806 return 0; 807 } 808 if (ievent & FEC_IEVENT_HBERR) { 809 /* Heartbeat error */ 810 writel(0x00000001 | readl(&fec->eth->x_cntrl), 811 &fec->eth->x_cntrl); 812 } 813 if (ievent & FEC_IEVENT_GRA) { 814 /* Graceful stop complete */ 815 if (readl(&fec->eth->x_cntrl) & 0x00000001) { 816 fec_halt(dev); 817 writel(~0x00000001 & readl(&fec->eth->x_cntrl), 818 &fec->eth->x_cntrl); 819 fec_init(dev, fec->bd); 820 } 821 } 822 823 /* 824 * Read the buffer status. Before the status can be read, the data cache 825 * must be invalidated, because the data in RAM might have been changed 826 * by DMA. The descriptors are properly aligned to cachelines so there's 827 * no need to worry they'd overlap. 828 * 829 * WARNING: By invalidating the descriptor here, we also invalidate 830 * the descriptors surrounding this one. Therefore we can NOT change the 831 * contents of this descriptor nor the surrounding ones. The problem is 832 * that in order to mark the descriptor as processed, we need to change 833 * the descriptor. The solution is to mark the whole cache line when all 834 * descriptors in the cache line are processed. 835 */ 836 addr = (uint32_t)rbd; 837 addr &= ~(ARCH_DMA_MINALIGN - 1); 838 size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN); 839 invalidate_dcache_range(addr, addr + size); 840 841 bd_status = readw(&rbd->status); 842 debug("fec_recv: status 0x%x\n", bd_status); 843 844 if (!(bd_status & FEC_RBD_EMPTY)) { 845 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) && 846 ((readw(&rbd->data_length) - 4) > 14)) { 847 /* 848 * Get buffer address and size 849 */ 850 frame = (struct nbuf *)readl(&rbd->data_pointer); 851 frame_length = readw(&rbd->data_length) - 4; 852 /* 853 * Invalidate data cache over the buffer 854 */ 855 addr = (uint32_t)frame; 856 size = roundup(frame_length, ARCH_DMA_MINALIGN); 857 invalidate_dcache_range(addr, addr + size); 858 859 /* 860 * Fill the buffer and pass it to upper layers 861 */ 862 #ifdef CONFIG_FEC_MXC_SWAP_PACKET 863 swap_packet((uint32_t *)frame->data, frame_length); 864 #endif 865 memcpy(buff, frame->data, frame_length); 866 NetReceive(buff, frame_length); 867 len = frame_length; 868 } else { 869 if (bd_status & FEC_RBD_ERR) 870 printf("error frame: 0x%08lx 0x%08x\n", 871 (ulong)rbd->data_pointer, 872 bd_status); 873 } 874 875 /* 876 * Free the current buffer, restart the engine and move forward 877 * to the next buffer. Here we check if the whole cacheline of 878 * descriptors was already processed and if so, we mark it free 879 * as whole. 880 */ 881 size = RXDESC_PER_CACHELINE - 1; 882 if ((fec->rbd_index & size) == size) { 883 i = fec->rbd_index - size; 884 addr = (uint32_t)&fec->rbd_base[i]; 885 for (; i <= fec->rbd_index ; i++) { 886 fec_rbd_clean(i == (FEC_RBD_NUM - 1), 887 &fec->rbd_base[i]); 888 } 889 flush_dcache_range(addr, 890 addr + ARCH_DMA_MINALIGN); 891 } 892 893 fec_rx_task_enable(fec); 894 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM; 895 } 896 debug("fec_recv: stop\n"); 897 898 return len; 899 } 900 901 static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr) 902 { 903 struct eth_device *edev; 904 struct fec_priv *fec; 905 struct mii_dev *bus; 906 unsigned char ethaddr[6]; 907 uint32_t start; 908 int ret = 0; 909 910 /* create and fill edev struct */ 911 edev = (struct eth_device *)malloc(sizeof(struct eth_device)); 912 if (!edev) { 913 puts("fec_mxc: not enough malloc memory for eth_device\n"); 914 ret = -ENOMEM; 915 goto err1; 916 } 917 918 fec = (struct fec_priv *)malloc(sizeof(struct fec_priv)); 919 if (!fec) { 920 puts("fec_mxc: not enough malloc memory for fec_priv\n"); 921 ret = -ENOMEM; 922 goto err2; 923 } 924 925 memset(edev, 0, sizeof(*edev)); 926 memset(fec, 0, sizeof(*fec)); 927 928 edev->priv = fec; 929 edev->init = fec_init; 930 edev->send = fec_send; 931 edev->recv = fec_recv; 932 edev->halt = fec_halt; 933 edev->write_hwaddr = fec_set_hwaddr; 934 935 fec->eth = (struct ethernet_regs *)base_addr; 936 fec->bd = bd; 937 938 fec->xcv_type = CONFIG_FEC_XCV_TYPE; 939 940 /* Reset chip. */ 941 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl); 942 start = get_timer(0); 943 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) { 944 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { 945 printf("FEC MXC: Timeout reseting chip\n"); 946 goto err3; 947 } 948 udelay(10); 949 } 950 951 fec_reg_setup(fec); 952 fec_mii_setspeed(fec); 953 954 if (dev_id == -1) { 955 sprintf(edev->name, "FEC"); 956 fec->dev_id = 0; 957 } else { 958 sprintf(edev->name, "FEC%i", dev_id); 959 fec->dev_id = dev_id; 960 } 961 fec->phy_id = phy_id; 962 963 bus = mdio_alloc(); 964 if (!bus) { 965 printf("mdio_alloc failed\n"); 966 ret = -ENOMEM; 967 goto err3; 968 } 969 bus->read = fec_phy_read; 970 bus->write = fec_phy_write; 971 sprintf(bus->name, edev->name); 972 #ifdef CONFIG_MX28 973 /* 974 * The i.MX28 has two ethernet interfaces, but they are not equal. 975 * Only the first one can access the MDIO bus. 976 */ 977 bus->priv = (struct ethernet_regs *)MXS_ENET0_BASE; 978 #else 979 bus->priv = fec->eth; 980 #endif 981 ret = mdio_register(bus); 982 if (ret) { 983 printf("mdio_register failed\n"); 984 free(bus); 985 ret = -ENOMEM; 986 goto err3; 987 } 988 fec->bus = bus; 989 eth_register(edev); 990 991 if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) { 992 debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr); 993 memcpy(edev->enetaddr, ethaddr, 6); 994 } 995 /* Configure phy */ 996 fec_eth_phy_config(edev); 997 return ret; 998 999 err3: 1000 free(fec); 1001 err2: 1002 free(edev); 1003 err1: 1004 return ret; 1005 } 1006 1007 #ifndef CONFIG_FEC_MXC_MULTI 1008 int fecmxc_initialize(bd_t *bd) 1009 { 1010 int lout = 1; 1011 1012 debug("eth_init: fec_probe(bd)\n"); 1013 lout = fec_probe(bd, -1, CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); 1014 1015 return lout; 1016 } 1017 #endif 1018 1019 int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr) 1020 { 1021 int lout = 1; 1022 1023 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr); 1024 lout = fec_probe(bd, dev_id, phy_id, addr); 1025 1026 return lout; 1027 } 1028 1029 #ifndef CONFIG_PHYLIB 1030 int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)) 1031 { 1032 struct fec_priv *fec = (struct fec_priv *)dev->priv; 1033 fec->mii_postcall = cb; 1034 return 0; 1035 } 1036 #endif 1037