1 /* 2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com> 3 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org> 4 * (C) Copyright 2008 Armadeus Systems nc 5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <malloc.h> 26 #include <net.h> 27 #include <miiphy.h> 28 #include "fec_mxc.h" 29 30 #include <asm/arch/clock.h> 31 #include <asm/arch/imx-regs.h> 32 #include <asm/io.h> 33 #include <asm/errno.h> 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 #ifndef CONFIG_MII 38 #error "CONFIG_MII has to be defined!" 39 #endif 40 41 #undef DEBUG 42 43 struct nbuf { 44 uint8_t data[1500]; /**< actual data */ 45 int length; /**< actual length */ 46 int used; /**< buffer in use or not */ 47 uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */ 48 }; 49 50 struct fec_priv gfec = { 51 .eth = (struct ethernet_regs *)IMX_FEC_BASE, 52 .xcv_type = MII100, 53 .rbd_base = NULL, 54 .rbd_index = 0, 55 .tbd_base = NULL, 56 .tbd_index = 0, 57 .bd = NULL, 58 .rdb_ptr = NULL, 59 .base_ptr = NULL, 60 }; 61 62 /* 63 * MII-interface related functions 64 */ 65 static int fec_miiphy_read(const char *dev, uint8_t phyAddr, uint8_t regAddr, 66 uint16_t *retVal) 67 { 68 struct eth_device *edev = eth_get_dev_by_name(dev); 69 struct fec_priv *fec = (struct fec_priv *)edev->priv; 70 71 uint32_t reg; /* convenient holder for the PHY register */ 72 uint32_t phy; /* convenient holder for the PHY */ 73 uint32_t start; 74 75 /* 76 * reading from any PHY's register is done by properly 77 * programming the FEC's MII data register. 78 */ 79 writel(FEC_IEVENT_MII, &fec->eth->ievent); 80 reg = regAddr << FEC_MII_DATA_RA_SHIFT; 81 phy = phyAddr << FEC_MII_DATA_PA_SHIFT; 82 83 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | 84 phy | reg, &fec->eth->mii_data); 85 86 /* 87 * wait for the related interrupt 88 */ 89 start = get_timer(0); 90 while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) { 91 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { 92 printf("Read MDIO failed...\n"); 93 return -1; 94 } 95 } 96 97 /* 98 * clear mii interrupt bit 99 */ 100 writel(FEC_IEVENT_MII, &fec->eth->ievent); 101 102 /* 103 * it's now safe to read the PHY's register 104 */ 105 *retVal = readl(&fec->eth->mii_data); 106 debug("fec_miiphy_read: phy: %02x reg:%02x val:%#x\n", phyAddr, 107 regAddr, *retVal); 108 return 0; 109 } 110 111 static void fec_mii_setspeed(struct fec_priv *fec) 112 { 113 /* 114 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock 115 * and do not drop the Preamble. 116 */ 117 writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1, 118 &fec->eth->mii_speed); 119 debug("fec_init: mii_speed %#lx\n", 120 fec->eth->mii_speed); 121 } 122 static int fec_miiphy_write(const char *dev, uint8_t phyAddr, uint8_t regAddr, 123 uint16_t data) 124 { 125 struct eth_device *edev = eth_get_dev_by_name(dev); 126 struct fec_priv *fec = (struct fec_priv *)edev->priv; 127 128 uint32_t reg; /* convenient holder for the PHY register */ 129 uint32_t phy; /* convenient holder for the PHY */ 130 uint32_t start; 131 132 reg = regAddr << FEC_MII_DATA_RA_SHIFT; 133 phy = phyAddr << FEC_MII_DATA_PA_SHIFT; 134 135 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | 136 FEC_MII_DATA_TA | phy | reg | data, &fec->eth->mii_data); 137 138 /* 139 * wait for the MII interrupt 140 */ 141 start = get_timer(0); 142 while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) { 143 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { 144 printf("Write MDIO failed...\n"); 145 return -1; 146 } 147 } 148 149 /* 150 * clear MII interrupt bit 151 */ 152 writel(FEC_IEVENT_MII, &fec->eth->ievent); 153 debug("fec_miiphy_write: phy: %02x reg:%02x val:%#x\n", phyAddr, 154 regAddr, data); 155 156 return 0; 157 } 158 159 static int miiphy_restart_aneg(struct eth_device *dev) 160 { 161 /* 162 * Wake up from sleep if necessary 163 * Reset PHY, then delay 300ns 164 */ 165 #ifdef CONFIG_MX27 166 miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, MII_DCOUNTER, 0x00FF); 167 #endif 168 miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, MII_BMCR, 169 BMCR_RESET); 170 udelay(1000); 171 172 /* 173 * Set the auto-negotiation advertisement register bits 174 */ 175 miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, MII_ADVERTISE, 176 LPA_100FULL | LPA_100HALF | LPA_10FULL | 177 LPA_10HALF | PHY_ANLPAR_PSB_802_3); 178 miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, MII_BMCR, 179 BMCR_ANENABLE | BMCR_ANRESTART); 180 181 return 0; 182 } 183 184 static int miiphy_wait_aneg(struct eth_device *dev) 185 { 186 uint32_t start; 187 uint16_t status; 188 189 /* 190 * Wait for AN completion 191 */ 192 start = get_timer(0); 193 do { 194 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { 195 printf("%s: Autonegotiation timeout\n", dev->name); 196 return -1; 197 } 198 199 if (miiphy_read(dev->name, CONFIG_FEC_MXC_PHYADDR, 200 MII_BMSR, &status)) { 201 printf("%s: Autonegotiation failed. status: 0x%04x\n", 202 dev->name, status); 203 return -1; 204 } 205 } while (!(status & BMSR_LSTATUS)); 206 207 return 0; 208 } 209 static int fec_rx_task_enable(struct fec_priv *fec) 210 { 211 writel(1 << 24, &fec->eth->r_des_active); 212 return 0; 213 } 214 215 static int fec_rx_task_disable(struct fec_priv *fec) 216 { 217 return 0; 218 } 219 220 static int fec_tx_task_enable(struct fec_priv *fec) 221 { 222 writel(1 << 24, &fec->eth->x_des_active); 223 return 0; 224 } 225 226 static int fec_tx_task_disable(struct fec_priv *fec) 227 { 228 return 0; 229 } 230 231 /** 232 * Initialize receive task's buffer descriptors 233 * @param[in] fec all we know about the device yet 234 * @param[in] count receive buffer count to be allocated 235 * @param[in] size size of each receive buffer 236 * @return 0 on success 237 * 238 * For this task we need additional memory for the data buffers. And each 239 * data buffer requires some alignment. Thy must be aligned to a specific 240 * boundary each (DB_DATA_ALIGNMENT). 241 */ 242 static int fec_rbd_init(struct fec_priv *fec, int count, int size) 243 { 244 int ix; 245 uint32_t p = 0; 246 247 /* reserve data memory and consider alignment */ 248 if (fec->rdb_ptr == NULL) 249 fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT); 250 p = (uint32_t)fec->rdb_ptr; 251 if (!p) { 252 puts("fec_mxc: not enough malloc memory\n"); 253 return -ENOMEM; 254 } 255 memset((void *)p, 0, size * count + DB_DATA_ALIGNMENT); 256 p += DB_DATA_ALIGNMENT-1; 257 p &= ~(DB_DATA_ALIGNMENT-1); 258 259 for (ix = 0; ix < count; ix++) { 260 writel(p, &fec->rbd_base[ix].data_pointer); 261 p += size; 262 writew(FEC_RBD_EMPTY, &fec->rbd_base[ix].status); 263 writew(0, &fec->rbd_base[ix].data_length); 264 } 265 /* 266 * mark the last RBD to close the ring 267 */ 268 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[ix - 1].status); 269 fec->rbd_index = 0; 270 271 return 0; 272 } 273 274 /** 275 * Initialize transmit task's buffer descriptors 276 * @param[in] fec all we know about the device yet 277 * 278 * Transmit buffers are created externally. We only have to init the BDs here.\n 279 * Note: There is a race condition in the hardware. When only one BD is in 280 * use it must be marked with the WRAP bit to use it for every transmitt. 281 * This bit in combination with the READY bit results into double transmit 282 * of each data buffer. It seems the state machine checks READY earlier then 283 * resetting it after the first transfer. 284 * Using two BDs solves this issue. 285 */ 286 static void fec_tbd_init(struct fec_priv *fec) 287 { 288 writew(0x0000, &fec->tbd_base[0].status); 289 writew(FEC_TBD_WRAP, &fec->tbd_base[1].status); 290 fec->tbd_index = 0; 291 } 292 293 /** 294 * Mark the given read buffer descriptor as free 295 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0 296 * @param[in] pRbd buffer descriptor to mark free again 297 */ 298 static void fec_rbd_clean(int last, struct fec_bd *pRbd) 299 { 300 /* 301 * Reset buffer descriptor as empty 302 */ 303 if (last) 304 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &pRbd->status); 305 else 306 writew(FEC_RBD_EMPTY, &pRbd->status); 307 /* 308 * no data in it 309 */ 310 writew(0, &pRbd->data_length); 311 } 312 313 static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac) 314 { 315 imx_get_mac_from_fuse(mac); 316 return !is_valid_ether_addr(mac); 317 } 318 319 static int fec_set_hwaddr(struct eth_device *dev) 320 { 321 uchar *mac = dev->enetaddr; 322 struct fec_priv *fec = (struct fec_priv *)dev->priv; 323 324 writel(0, &fec->eth->iaddr1); 325 writel(0, &fec->eth->iaddr2); 326 writel(0, &fec->eth->gaddr1); 327 writel(0, &fec->eth->gaddr2); 328 329 /* 330 * Set physical address 331 */ 332 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3], 333 &fec->eth->paddr1); 334 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2); 335 336 return 0; 337 } 338 339 /** 340 * Start the FEC engine 341 * @param[in] dev Our device to handle 342 */ 343 static int fec_open(struct eth_device *edev) 344 { 345 struct fec_priv *fec = (struct fec_priv *)edev->priv; 346 347 debug("fec_open: fec_open(dev)\n"); 348 /* full-duplex, heartbeat disabled */ 349 writel(1 << 2, &fec->eth->x_cntrl); 350 fec->rbd_index = 0; 351 352 /* 353 * Enable FEC-Lite controller 354 */ 355 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, 356 &fec->eth->ecntrl); 357 #if defined(CONFIG_MX25) || defined(CONFIG_MX53) 358 udelay(100); 359 /* 360 * setup the MII gasket for RMII mode 361 */ 362 363 /* disable the gasket */ 364 writew(0, &fec->eth->miigsk_enr); 365 366 /* wait for the gasket to be disabled */ 367 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) 368 udelay(2); 369 370 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */ 371 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr); 372 373 /* re-enable the gasket */ 374 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr); 375 376 /* wait until MII gasket is ready */ 377 int max_loops = 10; 378 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) { 379 if (--max_loops <= 0) { 380 printf("WAIT for MII Gasket ready timed out\n"); 381 break; 382 } 383 } 384 #endif 385 386 miiphy_wait_aneg(edev); 387 miiphy_speed(edev->name, CONFIG_FEC_MXC_PHYADDR); 388 miiphy_duplex(edev->name, CONFIG_FEC_MXC_PHYADDR); 389 390 /* 391 * Enable SmartDMA receive task 392 */ 393 fec_rx_task_enable(fec); 394 395 udelay(100000); 396 return 0; 397 } 398 399 static int fec_init(struct eth_device *dev, bd_t* bd) 400 { 401 uint32_t base; 402 struct fec_priv *fec = (struct fec_priv *)dev->priv; 403 404 /* Initialize MAC address */ 405 fec_set_hwaddr(dev); 406 407 /* 408 * reserve memory for both buffer descriptor chains at once 409 * Datasheet forces the startaddress of each chain is 16 byte 410 * aligned 411 */ 412 if (fec->base_ptr == NULL) 413 fec->base_ptr = malloc((2 + FEC_RBD_NUM) * 414 sizeof(struct fec_bd) + DB_ALIGNMENT); 415 base = (uint32_t)fec->base_ptr; 416 if (!base) { 417 puts("fec_mxc: not enough malloc memory\n"); 418 return -ENOMEM; 419 } 420 memset((void *)base, 0, (2 + FEC_RBD_NUM) * 421 sizeof(struct fec_bd) + DB_ALIGNMENT); 422 base += (DB_ALIGNMENT-1); 423 base &= ~(DB_ALIGNMENT-1); 424 425 fec->rbd_base = (struct fec_bd *)base; 426 427 base += FEC_RBD_NUM * sizeof(struct fec_bd); 428 429 fec->tbd_base = (struct fec_bd *)base; 430 431 /* 432 * Set interrupt mask register 433 */ 434 writel(0x00000000, &fec->eth->imask); 435 436 /* 437 * Clear FEC-Lite interrupt event register(IEVENT) 438 */ 439 writel(0xffffffff, &fec->eth->ievent); 440 441 442 /* 443 * Set FEC-Lite receive control register(R_CNTRL): 444 */ 445 if (fec->xcv_type == SEVENWIRE) { 446 /* 447 * Frame length=1518; 7-wire mode 448 */ 449 writel(0x05ee0020, &fec->eth->r_cntrl); /* FIXME 0x05ee0000 */ 450 } else { 451 /* 452 * Frame length=1518; MII mode; 453 */ 454 writel(0x05ee0024, &fec->eth->r_cntrl); /* FIXME 0x05ee0004 */ 455 456 fec_mii_setspeed(fec); 457 } 458 /* 459 * Set Opcode/Pause Duration Register 460 */ 461 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */ 462 writel(0x2, &fec->eth->x_wmrk); 463 /* 464 * Set multicast address filter 465 */ 466 writel(0x00000000, &fec->eth->gaddr1); 467 writel(0x00000000, &fec->eth->gaddr2); 468 469 470 /* clear MIB RAM */ 471 long *mib_ptr = (long *)(IMX_FEC_BASE + 0x200); 472 while (mib_ptr <= (long *)(IMX_FEC_BASE + 0x2FC)) 473 *mib_ptr++ = 0; 474 475 /* FIFO receive start register */ 476 writel(0x520, &fec->eth->r_fstart); 477 478 /* size and address of each buffer */ 479 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr); 480 writel((uint32_t)fec->tbd_base, &fec->eth->etdsr); 481 writel((uint32_t)fec->rbd_base, &fec->eth->erdsr); 482 483 /* 484 * Initialize RxBD/TxBD rings 485 */ 486 if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) { 487 free(fec->base_ptr); 488 fec->base_ptr = NULL; 489 return -ENOMEM; 490 } 491 fec_tbd_init(fec); 492 493 494 if (fec->xcv_type != SEVENWIRE) 495 miiphy_restart_aneg(dev); 496 497 fec_open(dev); 498 return 0; 499 } 500 501 /** 502 * Halt the FEC engine 503 * @param[in] dev Our device to handle 504 */ 505 static void fec_halt(struct eth_device *dev) 506 { 507 struct fec_priv *fec = &gfec; 508 int counter = 0xffff; 509 510 /* 511 * issue graceful stop command to the FEC transmitter if necessary 512 */ 513 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl), 514 &fec->eth->x_cntrl); 515 516 debug("eth_halt: wait for stop regs\n"); 517 /* 518 * wait for graceful stop to register 519 */ 520 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA))) 521 udelay(1); 522 523 /* 524 * Disable SmartDMA tasks 525 */ 526 fec_tx_task_disable(fec); 527 fec_rx_task_disable(fec); 528 529 /* 530 * Disable the Ethernet Controller 531 * Note: this will also reset the BD index counter! 532 */ 533 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN, 534 &fec->eth->ecntrl); 535 fec->rbd_index = 0; 536 fec->tbd_index = 0; 537 debug("eth_halt: done\n"); 538 } 539 540 /** 541 * Transmit one frame 542 * @param[in] dev Our ethernet device to handle 543 * @param[in] packet Pointer to the data to be transmitted 544 * @param[in] length Data count in bytes 545 * @return 0 on success 546 */ 547 static int fec_send(struct eth_device *dev, volatile void* packet, int length) 548 { 549 unsigned int status; 550 551 /* 552 * This routine transmits one frame. This routine only accepts 553 * 6-byte Ethernet addresses. 554 */ 555 struct fec_priv *fec = (struct fec_priv *)dev->priv; 556 557 /* 558 * Check for valid length of data. 559 */ 560 if ((length > 1500) || (length <= 0)) { 561 printf("Payload (%d) too large\n", length); 562 return -1; 563 } 564 565 /* 566 * Setup the transmit buffer 567 * Note: We are always using the first buffer for transmission, 568 * the second will be empty and only used to stop the DMA engine 569 */ 570 writew(length, &fec->tbd_base[fec->tbd_index].data_length); 571 writel((uint32_t)packet, &fec->tbd_base[fec->tbd_index].data_pointer); 572 /* 573 * update BD's status now 574 * This block: 575 * - is always the last in a chain (means no chain) 576 * - should transmitt the CRC 577 * - might be the last BD in the list, so the address counter should 578 * wrap (-> keep the WRAP flag) 579 */ 580 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP; 581 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; 582 writew(status, &fec->tbd_base[fec->tbd_index].status); 583 584 /* 585 * Enable SmartDMA transmit task 586 */ 587 fec_tx_task_enable(fec); 588 589 /* 590 * wait until frame is sent . 591 */ 592 while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) { 593 udelay(1); 594 } 595 debug("fec_send: status 0x%x index %d\n", 596 readw(&fec->tbd_base[fec->tbd_index].status), 597 fec->tbd_index); 598 /* for next transmission use the other buffer */ 599 if (fec->tbd_index) 600 fec->tbd_index = 0; 601 else 602 fec->tbd_index = 1; 603 604 return 0; 605 } 606 607 /** 608 * Pull one frame from the card 609 * @param[in] dev Our ethernet device to handle 610 * @return Length of packet read 611 */ 612 static int fec_recv(struct eth_device *dev) 613 { 614 struct fec_priv *fec = (struct fec_priv *)dev->priv; 615 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index]; 616 unsigned long ievent; 617 int frame_length, len = 0; 618 struct nbuf *frame; 619 uint16_t bd_status; 620 uchar buff[FEC_MAX_PKT_SIZE]; 621 622 /* 623 * Check if any critical events have happened 624 */ 625 ievent = readl(&fec->eth->ievent); 626 writel(ievent, &fec->eth->ievent); 627 debug("fec_recv: ievent 0x%x\n", ievent); 628 if (ievent & FEC_IEVENT_BABR) { 629 fec_halt(dev); 630 fec_init(dev, fec->bd); 631 printf("some error: 0x%08lx\n", ievent); 632 return 0; 633 } 634 if (ievent & FEC_IEVENT_HBERR) { 635 /* Heartbeat error */ 636 writel(0x00000001 | readl(&fec->eth->x_cntrl), 637 &fec->eth->x_cntrl); 638 } 639 if (ievent & FEC_IEVENT_GRA) { 640 /* Graceful stop complete */ 641 if (readl(&fec->eth->x_cntrl) & 0x00000001) { 642 fec_halt(dev); 643 writel(~0x00000001 & readl(&fec->eth->x_cntrl), 644 &fec->eth->x_cntrl); 645 fec_init(dev, fec->bd); 646 } 647 } 648 649 /* 650 * ensure reading the right buffer status 651 */ 652 bd_status = readw(&rbd->status); 653 debug("fec_recv: status 0x%x\n", bd_status); 654 655 if (!(bd_status & FEC_RBD_EMPTY)) { 656 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) && 657 ((readw(&rbd->data_length) - 4) > 14)) { 658 /* 659 * Get buffer address and size 660 */ 661 frame = (struct nbuf *)readl(&rbd->data_pointer); 662 frame_length = readw(&rbd->data_length) - 4; 663 /* 664 * Fill the buffer and pass it to upper layers 665 */ 666 memcpy(buff, frame->data, frame_length); 667 NetReceive(buff, frame_length); 668 len = frame_length; 669 } else { 670 if (bd_status & FEC_RBD_ERR) 671 printf("error frame: 0x%08lx 0x%08x\n", 672 (ulong)rbd->data_pointer, 673 bd_status); 674 } 675 /* 676 * free the current buffer, restart the engine 677 * and move forward to the next buffer 678 */ 679 fec_rbd_clean(fec->rbd_index == (FEC_RBD_NUM - 1) ? 1 : 0, rbd); 680 fec_rx_task_enable(fec); 681 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM; 682 } 683 debug("fec_recv: stop\n"); 684 685 return len; 686 } 687 688 static int fec_probe(bd_t *bd) 689 { 690 struct eth_device *edev; 691 struct fec_priv *fec = &gfec; 692 unsigned char ethaddr[6]; 693 694 /* create and fill edev struct */ 695 edev = (struct eth_device *)malloc(sizeof(struct eth_device)); 696 if (!edev) { 697 puts("fec_mxc: not enough malloc memory\n"); 698 return -ENOMEM; 699 } 700 memset(edev, 0, sizeof(*edev)); 701 edev->priv = fec; 702 edev->init = fec_init; 703 edev->send = fec_send; 704 edev->recv = fec_recv; 705 edev->halt = fec_halt; 706 edev->write_hwaddr = fec_set_hwaddr; 707 708 fec->eth = (struct ethernet_regs *)IMX_FEC_BASE; 709 fec->bd = bd; 710 711 fec->xcv_type = MII100; 712 713 /* Reset chip. */ 714 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl); 715 while (readl(&fec->eth->ecntrl) & 1) 716 udelay(10); 717 718 /* 719 * Set interrupt mask register 720 */ 721 writel(0x00000000, &fec->eth->imask); 722 723 /* 724 * Clear FEC-Lite interrupt event register(IEVENT) 725 */ 726 writel(0xffffffff, &fec->eth->ievent); 727 728 /* 729 * Set FEC-Lite receive control register(R_CNTRL): 730 */ 731 /* 732 * Frame length=1518; MII mode; 733 */ 734 writel(0x05ee0024, &fec->eth->r_cntrl); /* FIXME 0x05ee0004 */ 735 fec_mii_setspeed(fec); 736 737 sprintf(edev->name, "FEC"); 738 739 miiphy_register(edev->name, fec_miiphy_read, fec_miiphy_write); 740 741 eth_register(edev); 742 743 if (fec_get_hwaddr(edev, ethaddr) == 0) { 744 printf("got MAC address from fuse: %pM\n", ethaddr); 745 memcpy(edev->enetaddr, ethaddr, 6); 746 } 747 748 return 0; 749 } 750 751 int fecmxc_initialize(bd_t *bd) 752 { 753 int lout = 1; 754 755 debug("eth_init: fec_probe(bd)\n"); 756 lout = fec_probe(bd); 757 758 return lout; 759 } 760