1 /* 2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com> 3 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org> 4 * (C) Copyright 2008 Armadeus Systems nc 5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <malloc.h> 26 #include <net.h> 27 #include <miiphy.h> 28 #include "fec_mxc.h" 29 30 #include <asm/arch/clock.h> 31 #include <asm/arch/imx-regs.h> 32 #include <asm/io.h> 33 #include <asm/errno.h> 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 #ifndef CONFIG_MII 38 #error "CONFIG_MII has to be defined!" 39 #endif 40 41 #undef DEBUG 42 43 struct nbuf { 44 uint8_t data[1500]; /**< actual data */ 45 int length; /**< actual length */ 46 int used; /**< buffer in use or not */ 47 uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */ 48 }; 49 50 struct fec_priv gfec = { 51 .eth = (struct ethernet_regs *)IMX_FEC_BASE, 52 .xcv_type = MII100, 53 .rbd_base = NULL, 54 .rbd_index = 0, 55 .tbd_base = NULL, 56 .tbd_index = 0, 57 .bd = NULL, 58 .rdb_ptr = NULL, 59 .base_ptr = NULL, 60 }; 61 62 /* 63 * MII-interface related functions 64 */ 65 static int fec_miiphy_read(char *dev, uint8_t phyAddr, uint8_t regAddr, 66 uint16_t *retVal) 67 { 68 struct eth_device *edev = eth_get_dev_by_name(dev); 69 struct fec_priv *fec = (struct fec_priv *)edev->priv; 70 71 uint32_t reg; /* convenient holder for the PHY register */ 72 uint32_t phy; /* convenient holder for the PHY */ 73 uint32_t start; 74 75 /* 76 * reading from any PHY's register is done by properly 77 * programming the FEC's MII data register. 78 */ 79 writel(FEC_IEVENT_MII, &fec->eth->ievent); 80 reg = regAddr << FEC_MII_DATA_RA_SHIFT; 81 phy = phyAddr << FEC_MII_DATA_PA_SHIFT; 82 83 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | 84 phy | reg, &fec->eth->mii_data); 85 86 /* 87 * wait for the related interrupt 88 */ 89 start = get_timer_masked(); 90 while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) { 91 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { 92 printf("Read MDIO failed...\n"); 93 return -1; 94 } 95 } 96 97 /* 98 * clear mii interrupt bit 99 */ 100 writel(FEC_IEVENT_MII, &fec->eth->ievent); 101 102 /* 103 * it's now safe to read the PHY's register 104 */ 105 *retVal = readl(&fec->eth->mii_data); 106 debug("fec_miiphy_read: phy: %02x reg:%02x val:%#x\n", phyAddr, 107 regAddr, *retVal); 108 return 0; 109 } 110 111 static void fec_mii_setspeed(struct fec_priv *fec) 112 { 113 /* 114 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock 115 * and do not drop the Preamble. 116 */ 117 writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1, 118 &fec->eth->mii_speed); 119 debug("fec_init: mii_speed %#lx\n", 120 fec->eth->mii_speed); 121 } 122 static int fec_miiphy_write(char *dev, uint8_t phyAddr, uint8_t regAddr, 123 uint16_t data) 124 { 125 struct eth_device *edev = eth_get_dev_by_name(dev); 126 struct fec_priv *fec = (struct fec_priv *)edev->priv; 127 128 uint32_t reg; /* convenient holder for the PHY register */ 129 uint32_t phy; /* convenient holder for the PHY */ 130 uint32_t start; 131 132 reg = regAddr << FEC_MII_DATA_RA_SHIFT; 133 phy = phyAddr << FEC_MII_DATA_PA_SHIFT; 134 135 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | 136 FEC_MII_DATA_TA | phy | reg | data, &fec->eth->mii_data); 137 138 /* 139 * wait for the MII interrupt 140 */ 141 start = get_timer_masked(); 142 while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) { 143 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { 144 printf("Write MDIO failed...\n"); 145 return -1; 146 } 147 } 148 149 /* 150 * clear MII interrupt bit 151 */ 152 writel(FEC_IEVENT_MII, &fec->eth->ievent); 153 debug("fec_miiphy_write: phy: %02x reg:%02x val:%#x\n", phyAddr, 154 regAddr, data); 155 156 return 0; 157 } 158 159 static int miiphy_restart_aneg(struct eth_device *dev) 160 { 161 /* 162 * Wake up from sleep if necessary 163 * Reset PHY, then delay 300ns 164 */ 165 #ifdef CONFIG_MX27 166 miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_MIPGSR, 0x00FF); 167 #endif 168 miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR, 169 PHY_BMCR_RESET); 170 udelay(1000); 171 172 /* 173 * Set the auto-negotiation advertisement register bits 174 */ 175 miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_ANAR, 176 PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD | 177 PHY_ANLPAR_10 | PHY_ANLPAR_PSB_802_3); 178 miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR, 179 PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); 180 181 return 0; 182 } 183 184 static int miiphy_wait_aneg(struct eth_device *dev) 185 { 186 uint32_t start; 187 uint16_t status; 188 189 /* 190 * Wait for AN completion 191 */ 192 start = get_timer_masked(); 193 do { 194 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { 195 printf("%s: Autonegotiation timeout\n", dev->name); 196 return -1; 197 } 198 199 if (miiphy_read(dev->name, CONFIG_FEC_MXC_PHYADDR, 200 PHY_BMSR, &status)) { 201 printf("%s: Autonegotiation failed. status: 0x%04x\n", 202 dev->name, status); 203 return -1; 204 } 205 } while (!(status & PHY_BMSR_LS)); 206 207 return 0; 208 } 209 static int fec_rx_task_enable(struct fec_priv *fec) 210 { 211 writel(1 << 24, &fec->eth->r_des_active); 212 return 0; 213 } 214 215 static int fec_rx_task_disable(struct fec_priv *fec) 216 { 217 return 0; 218 } 219 220 static int fec_tx_task_enable(struct fec_priv *fec) 221 { 222 writel(1 << 24, &fec->eth->x_des_active); 223 return 0; 224 } 225 226 static int fec_tx_task_disable(struct fec_priv *fec) 227 { 228 return 0; 229 } 230 231 /** 232 * Initialize receive task's buffer descriptors 233 * @param[in] fec all we know about the device yet 234 * @param[in] count receive buffer count to be allocated 235 * @param[in] size size of each receive buffer 236 * @return 0 on success 237 * 238 * For this task we need additional memory for the data buffers. And each 239 * data buffer requires some alignment. Thy must be aligned to a specific 240 * boundary each (DB_DATA_ALIGNMENT). 241 */ 242 static int fec_rbd_init(struct fec_priv *fec, int count, int size) 243 { 244 int ix; 245 uint32_t p = 0; 246 247 /* reserve data memory and consider alignment */ 248 if (fec->rdb_ptr == NULL) 249 fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT); 250 p = (uint32_t)fec->rdb_ptr; 251 if (!p) { 252 puts("fec_mxc: not enough malloc memory\n"); 253 return -ENOMEM; 254 } 255 memset((void *)p, 0, size * count + DB_DATA_ALIGNMENT); 256 p += DB_DATA_ALIGNMENT-1; 257 p &= ~(DB_DATA_ALIGNMENT-1); 258 259 for (ix = 0; ix < count; ix++) { 260 writel(p, &fec->rbd_base[ix].data_pointer); 261 p += size; 262 writew(FEC_RBD_EMPTY, &fec->rbd_base[ix].status); 263 writew(0, &fec->rbd_base[ix].data_length); 264 } 265 /* 266 * mark the last RBD to close the ring 267 */ 268 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[ix - 1].status); 269 fec->rbd_index = 0; 270 271 return 0; 272 } 273 274 /** 275 * Initialize transmit task's buffer descriptors 276 * @param[in] fec all we know about the device yet 277 * 278 * Transmit buffers are created externally. We only have to init the BDs here.\n 279 * Note: There is a race condition in the hardware. When only one BD is in 280 * use it must be marked with the WRAP bit to use it for every transmitt. 281 * This bit in combination with the READY bit results into double transmit 282 * of each data buffer. It seems the state machine checks READY earlier then 283 * resetting it after the first transfer. 284 * Using two BDs solves this issue. 285 */ 286 static void fec_tbd_init(struct fec_priv *fec) 287 { 288 writew(0x0000, &fec->tbd_base[0].status); 289 writew(FEC_TBD_WRAP, &fec->tbd_base[1].status); 290 fec->tbd_index = 0; 291 } 292 293 /** 294 * Mark the given read buffer descriptor as free 295 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0 296 * @param[in] pRbd buffer descriptor to mark free again 297 */ 298 static void fec_rbd_clean(int last, struct fec_bd *pRbd) 299 { 300 /* 301 * Reset buffer descriptor as empty 302 */ 303 if (last) 304 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &pRbd->status); 305 else 306 writew(FEC_RBD_EMPTY, &pRbd->status); 307 /* 308 * no data in it 309 */ 310 writew(0, &pRbd->data_length); 311 } 312 313 static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac) 314 { 315 /* 316 * The MX27 can store the mac address in internal eeprom 317 * This mechanism is not supported now by MX51 or MX25 318 */ 319 #if defined(CONFIG_MX51) || defined(CONFIG_MX25) 320 return -1; 321 #else 322 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; 323 int i; 324 325 for (i = 0; i < 6; i++) 326 mac[6-1-i] = readl(&iim->iim_bank_area0[IIM0_MAC + i]); 327 328 return !is_valid_ether_addr(mac); 329 #endif 330 } 331 332 static int fec_set_hwaddr(struct eth_device *dev) 333 { 334 uchar *mac = dev->enetaddr; 335 struct fec_priv *fec = (struct fec_priv *)dev->priv; 336 337 writel(0, &fec->eth->iaddr1); 338 writel(0, &fec->eth->iaddr2); 339 writel(0, &fec->eth->gaddr1); 340 writel(0, &fec->eth->gaddr2); 341 342 /* 343 * Set physical address 344 */ 345 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3], 346 &fec->eth->paddr1); 347 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2); 348 349 return 0; 350 } 351 352 /** 353 * Start the FEC engine 354 * @param[in] dev Our device to handle 355 */ 356 static int fec_open(struct eth_device *edev) 357 { 358 struct fec_priv *fec = (struct fec_priv *)edev->priv; 359 360 debug("fec_open: fec_open(dev)\n"); 361 /* full-duplex, heartbeat disabled */ 362 writel(1 << 2, &fec->eth->x_cntrl); 363 fec->rbd_index = 0; 364 365 /* 366 * Enable FEC-Lite controller 367 */ 368 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, 369 &fec->eth->ecntrl); 370 #ifdef CONFIG_MX25 371 udelay(100); 372 /* 373 * setup the MII gasket for RMII mode 374 */ 375 376 /* disable the gasket */ 377 writew(0, &fec->eth->miigsk_enr); 378 379 /* wait for the gasket to be disabled */ 380 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) 381 udelay(2); 382 383 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */ 384 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr); 385 386 /* re-enable the gasket */ 387 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr); 388 389 /* wait until MII gasket is ready */ 390 int max_loops = 10; 391 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) { 392 if (--max_loops <= 0) { 393 printf("WAIT for MII Gasket ready timed out\n"); 394 break; 395 } 396 } 397 #endif 398 399 miiphy_wait_aneg(edev); 400 miiphy_speed(edev->name, CONFIG_FEC_MXC_PHYADDR); 401 miiphy_duplex(edev->name, CONFIG_FEC_MXC_PHYADDR); 402 403 /* 404 * Enable SmartDMA receive task 405 */ 406 fec_rx_task_enable(fec); 407 408 udelay(100000); 409 return 0; 410 } 411 412 static int fec_init(struct eth_device *dev, bd_t* bd) 413 { 414 uint32_t base; 415 struct fec_priv *fec = (struct fec_priv *)dev->priv; 416 417 /* 418 * reserve memory for both buffer descriptor chains at once 419 * Datasheet forces the startaddress of each chain is 16 byte 420 * aligned 421 */ 422 if (fec->base_ptr == NULL) 423 fec->base_ptr = malloc((2 + FEC_RBD_NUM) * 424 sizeof(struct fec_bd) + DB_ALIGNMENT); 425 base = (uint32_t)fec->base_ptr; 426 if (!base) { 427 puts("fec_mxc: not enough malloc memory\n"); 428 return -ENOMEM; 429 } 430 memset((void *)base, 0, (2 + FEC_RBD_NUM) * 431 sizeof(struct fec_bd) + DB_ALIGNMENT); 432 base += (DB_ALIGNMENT-1); 433 base &= ~(DB_ALIGNMENT-1); 434 435 fec->rbd_base = (struct fec_bd *)base; 436 437 base += FEC_RBD_NUM * sizeof(struct fec_bd); 438 439 fec->tbd_base = (struct fec_bd *)base; 440 441 /* 442 * Set interrupt mask register 443 */ 444 writel(0x00000000, &fec->eth->imask); 445 446 /* 447 * Clear FEC-Lite interrupt event register(IEVENT) 448 */ 449 writel(0xffffffff, &fec->eth->ievent); 450 451 452 /* 453 * Set FEC-Lite receive control register(R_CNTRL): 454 */ 455 if (fec->xcv_type == SEVENWIRE) { 456 /* 457 * Frame length=1518; 7-wire mode 458 */ 459 writel(0x05ee0020, &fec->eth->r_cntrl); /* FIXME 0x05ee0000 */ 460 } else { 461 /* 462 * Frame length=1518; MII mode; 463 */ 464 writel(0x05ee0024, &fec->eth->r_cntrl); /* FIXME 0x05ee0004 */ 465 466 fec_mii_setspeed(fec); 467 } 468 /* 469 * Set Opcode/Pause Duration Register 470 */ 471 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */ 472 writel(0x2, &fec->eth->x_wmrk); 473 /* 474 * Set multicast address filter 475 */ 476 writel(0x00000000, &fec->eth->gaddr1); 477 writel(0x00000000, &fec->eth->gaddr2); 478 479 480 /* clear MIB RAM */ 481 long *mib_ptr = (long *)(IMX_FEC_BASE + 0x200); 482 while (mib_ptr <= (long *)(IMX_FEC_BASE + 0x2FC)) 483 *mib_ptr++ = 0; 484 485 /* FIFO receive start register */ 486 writel(0x520, &fec->eth->r_fstart); 487 488 /* size and address of each buffer */ 489 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr); 490 writel((uint32_t)fec->tbd_base, &fec->eth->etdsr); 491 writel((uint32_t)fec->rbd_base, &fec->eth->erdsr); 492 493 /* 494 * Initialize RxBD/TxBD rings 495 */ 496 if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) { 497 free(fec->base_ptr); 498 fec->base_ptr = NULL; 499 return -ENOMEM; 500 } 501 fec_tbd_init(fec); 502 503 504 if (fec->xcv_type != SEVENWIRE) 505 miiphy_restart_aneg(dev); 506 507 fec_open(dev); 508 return 0; 509 } 510 511 /** 512 * Halt the FEC engine 513 * @param[in] dev Our device to handle 514 */ 515 static void fec_halt(struct eth_device *dev) 516 { 517 struct fec_priv *fec = &gfec; 518 int counter = 0xffff; 519 520 /* 521 * issue graceful stop command to the FEC transmitter if necessary 522 */ 523 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl), 524 &fec->eth->x_cntrl); 525 526 debug("eth_halt: wait for stop regs\n"); 527 /* 528 * wait for graceful stop to register 529 */ 530 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA))) 531 udelay(1); 532 533 /* 534 * Disable SmartDMA tasks 535 */ 536 fec_tx_task_disable(fec); 537 fec_rx_task_disable(fec); 538 539 /* 540 * Disable the Ethernet Controller 541 * Note: this will also reset the BD index counter! 542 */ 543 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN, 544 &fec->eth->ecntrl); 545 fec->rbd_index = 0; 546 fec->tbd_index = 0; 547 debug("eth_halt: done\n"); 548 } 549 550 /** 551 * Transmit one frame 552 * @param[in] dev Our ethernet device to handle 553 * @param[in] packet Pointer to the data to be transmitted 554 * @param[in] length Data count in bytes 555 * @return 0 on success 556 */ 557 static int fec_send(struct eth_device *dev, volatile void* packet, int length) 558 { 559 unsigned int status; 560 561 /* 562 * This routine transmits one frame. This routine only accepts 563 * 6-byte Ethernet addresses. 564 */ 565 struct fec_priv *fec = (struct fec_priv *)dev->priv; 566 567 /* 568 * Check for valid length of data. 569 */ 570 if ((length > 1500) || (length <= 0)) { 571 printf("Payload (%d) too large\n", length); 572 return -1; 573 } 574 575 /* 576 * Setup the transmit buffer 577 * Note: We are always using the first buffer for transmission, 578 * the second will be empty and only used to stop the DMA engine 579 */ 580 writew(length, &fec->tbd_base[fec->tbd_index].data_length); 581 writel((uint32_t)packet, &fec->tbd_base[fec->tbd_index].data_pointer); 582 /* 583 * update BD's status now 584 * This block: 585 * - is always the last in a chain (means no chain) 586 * - should transmitt the CRC 587 * - might be the last BD in the list, so the address counter should 588 * wrap (-> keep the WRAP flag) 589 */ 590 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP; 591 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; 592 writew(status, &fec->tbd_base[fec->tbd_index].status); 593 594 /* 595 * Enable SmartDMA transmit task 596 */ 597 fec_tx_task_enable(fec); 598 599 /* 600 * wait until frame is sent . 601 */ 602 while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) { 603 udelay(1); 604 } 605 debug("fec_send: status 0x%x index %d\n", 606 readw(&fec->tbd_base[fec->tbd_index].status), 607 fec->tbd_index); 608 /* for next transmission use the other buffer */ 609 if (fec->tbd_index) 610 fec->tbd_index = 0; 611 else 612 fec->tbd_index = 1; 613 614 return 0; 615 } 616 617 /** 618 * Pull one frame from the card 619 * @param[in] dev Our ethernet device to handle 620 * @return Length of packet read 621 */ 622 static int fec_recv(struct eth_device *dev) 623 { 624 struct fec_priv *fec = (struct fec_priv *)dev->priv; 625 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index]; 626 unsigned long ievent; 627 int frame_length, len = 0; 628 struct nbuf *frame; 629 uint16_t bd_status; 630 uchar buff[FEC_MAX_PKT_SIZE]; 631 632 /* 633 * Check if any critical events have happened 634 */ 635 ievent = readl(&fec->eth->ievent); 636 writel(ievent, &fec->eth->ievent); 637 debug("fec_recv: ievent 0x%x\n", ievent); 638 if (ievent & FEC_IEVENT_BABR) { 639 fec_halt(dev); 640 fec_init(dev, fec->bd); 641 printf("some error: 0x%08lx\n", ievent); 642 return 0; 643 } 644 if (ievent & FEC_IEVENT_HBERR) { 645 /* Heartbeat error */ 646 writel(0x00000001 | readl(&fec->eth->x_cntrl), 647 &fec->eth->x_cntrl); 648 } 649 if (ievent & FEC_IEVENT_GRA) { 650 /* Graceful stop complete */ 651 if (readl(&fec->eth->x_cntrl) & 0x00000001) { 652 fec_halt(dev); 653 writel(~0x00000001 & readl(&fec->eth->x_cntrl), 654 &fec->eth->x_cntrl); 655 fec_init(dev, fec->bd); 656 } 657 } 658 659 /* 660 * ensure reading the right buffer status 661 */ 662 bd_status = readw(&rbd->status); 663 debug("fec_recv: status 0x%x\n", bd_status); 664 665 if (!(bd_status & FEC_RBD_EMPTY)) { 666 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) && 667 ((readw(&rbd->data_length) - 4) > 14)) { 668 /* 669 * Get buffer address and size 670 */ 671 frame = (struct nbuf *)readl(&rbd->data_pointer); 672 frame_length = readw(&rbd->data_length) - 4; 673 /* 674 * Fill the buffer and pass it to upper layers 675 */ 676 memcpy(buff, frame->data, frame_length); 677 NetReceive(buff, frame_length); 678 len = frame_length; 679 } else { 680 if (bd_status & FEC_RBD_ERR) 681 printf("error frame: 0x%08lx 0x%08x\n", 682 (ulong)rbd->data_pointer, 683 bd_status); 684 } 685 /* 686 * free the current buffer, restart the engine 687 * and move forward to the next buffer 688 */ 689 fec_rbd_clean(fec->rbd_index == (FEC_RBD_NUM - 1) ? 1 : 0, rbd); 690 fec_rx_task_enable(fec); 691 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM; 692 } 693 debug("fec_recv: stop\n"); 694 695 return len; 696 } 697 698 static int fec_probe(bd_t *bd) 699 { 700 struct eth_device *edev; 701 struct fec_priv *fec = &gfec; 702 unsigned char ethaddr[6]; 703 704 /* create and fill edev struct */ 705 edev = (struct eth_device *)malloc(sizeof(struct eth_device)); 706 if (!edev) { 707 puts("fec_mxc: not enough malloc memory\n"); 708 return -ENOMEM; 709 } 710 edev->priv = fec; 711 edev->init = fec_init; 712 edev->send = fec_send; 713 edev->recv = fec_recv; 714 edev->halt = fec_halt; 715 edev->write_hwaddr = fec_set_hwaddr; 716 717 fec->eth = (struct ethernet_regs *)IMX_FEC_BASE; 718 fec->bd = bd; 719 720 fec->xcv_type = MII100; 721 722 /* Reset chip. */ 723 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl); 724 while (readl(&fec->eth->ecntrl) & 1) 725 udelay(10); 726 727 /* 728 * Set interrupt mask register 729 */ 730 writel(0x00000000, &fec->eth->imask); 731 732 /* 733 * Clear FEC-Lite interrupt event register(IEVENT) 734 */ 735 writel(0xffffffff, &fec->eth->ievent); 736 737 /* 738 * Set FEC-Lite receive control register(R_CNTRL): 739 */ 740 /* 741 * Frame length=1518; MII mode; 742 */ 743 writel(0x05ee0024, &fec->eth->r_cntrl); /* FIXME 0x05ee0004 */ 744 fec_mii_setspeed(fec); 745 746 sprintf(edev->name, "FEC_MXC"); 747 748 miiphy_register(edev->name, fec_miiphy_read, fec_miiphy_write); 749 750 eth_register(edev); 751 752 if (fec_get_hwaddr(edev, ethaddr) == 0) { 753 printf("got MAC address from EEPROM: %pM\n", ethaddr); 754 memcpy(edev->enetaddr, ethaddr, 6); 755 } 756 757 return 0; 758 } 759 760 int fecmxc_initialize(bd_t *bd) 761 { 762 int lout = 1; 763 764 debug("eth_init: fec_probe(bd)\n"); 765 lout = fec_probe(bd); 766 767 return lout; 768 } 769