1 /* 2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com> 3 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org> 4 * (C) Copyright 2008 Armadeus Systems nc 5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <malloc.h> 26 #include <net.h> 27 #include <miiphy.h> 28 #include "fec_mxc.h" 29 30 #include <asm/arch/clock.h> 31 #include <asm/arch/imx-regs.h> 32 #include <asm/io.h> 33 #include <asm/errno.h> 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 #ifndef CONFIG_MII 38 #error "CONFIG_MII has to be defined!" 39 #endif 40 41 #undef DEBUG 42 43 struct nbuf { 44 uint8_t data[1500]; /**< actual data */ 45 int length; /**< actual length */ 46 int used; /**< buffer in use or not */ 47 uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */ 48 }; 49 50 struct fec_priv gfec = { 51 .eth = (struct ethernet_regs *)IMX_FEC_BASE, 52 .xcv_type = MII100, 53 .rbd_base = NULL, 54 .rbd_index = 0, 55 .tbd_base = NULL, 56 .tbd_index = 0, 57 .bd = NULL, 58 .rdb_ptr = NULL, 59 .base_ptr = NULL, 60 }; 61 62 /* 63 * MII-interface related functions 64 */ 65 static int fec_miiphy_read(char *dev, uint8_t phyAddr, uint8_t regAddr, 66 uint16_t *retVal) 67 { 68 struct eth_device *edev = eth_get_dev_by_name(dev); 69 struct fec_priv *fec = (struct fec_priv *)edev->priv; 70 71 uint32_t reg; /* convenient holder for the PHY register */ 72 uint32_t phy; /* convenient holder for the PHY */ 73 uint32_t start; 74 75 /* 76 * reading from any PHY's register is done by properly 77 * programming the FEC's MII data register. 78 */ 79 writel(FEC_IEVENT_MII, &fec->eth->ievent); 80 reg = regAddr << FEC_MII_DATA_RA_SHIFT; 81 phy = phyAddr << FEC_MII_DATA_PA_SHIFT; 82 83 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | 84 phy | reg, &fec->eth->mii_data); 85 86 /* 87 * wait for the related interrupt 88 */ 89 start = get_timer_masked(); 90 while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) { 91 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { 92 printf("Read MDIO failed...\n"); 93 return -1; 94 } 95 } 96 97 /* 98 * clear mii interrupt bit 99 */ 100 writel(FEC_IEVENT_MII, &fec->eth->ievent); 101 102 /* 103 * it's now safe to read the PHY's register 104 */ 105 *retVal = readl(&fec->eth->mii_data); 106 debug("fec_miiphy_read: phy: %02x reg:%02x val:%#x\n", phyAddr, 107 regAddr, *retVal); 108 return 0; 109 } 110 111 static int fec_miiphy_write(char *dev, uint8_t phyAddr, uint8_t regAddr, 112 uint16_t data) 113 { 114 struct eth_device *edev = eth_get_dev_by_name(dev); 115 struct fec_priv *fec = (struct fec_priv *)edev->priv; 116 117 uint32_t reg; /* convenient holder for the PHY register */ 118 uint32_t phy; /* convenient holder for the PHY */ 119 uint32_t start; 120 121 reg = regAddr << FEC_MII_DATA_RA_SHIFT; 122 phy = phyAddr << FEC_MII_DATA_PA_SHIFT; 123 124 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | 125 FEC_MII_DATA_TA | phy | reg | data, &fec->eth->mii_data); 126 127 /* 128 * wait for the MII interrupt 129 */ 130 start = get_timer_masked(); 131 while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) { 132 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { 133 printf("Write MDIO failed...\n"); 134 return -1; 135 } 136 } 137 138 /* 139 * clear MII interrupt bit 140 */ 141 writel(FEC_IEVENT_MII, &fec->eth->ievent); 142 debug("fec_miiphy_write: phy: %02x reg:%02x val:%#x\n", phyAddr, 143 regAddr, data); 144 145 return 0; 146 } 147 148 static int miiphy_restart_aneg(struct eth_device *dev) 149 { 150 /* 151 * Wake up from sleep if necessary 152 * Reset PHY, then delay 300ns 153 */ 154 miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_MIPGSR, 0x00FF); 155 miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR, 156 PHY_BMCR_RESET); 157 udelay(1000); 158 159 /* 160 * Set the auto-negotiation advertisement register bits 161 */ 162 miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_ANAR, 163 PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD | 164 PHY_ANLPAR_10 | PHY_ANLPAR_PSB_802_3); 165 miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR, 166 PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); 167 168 return 0; 169 } 170 171 static int miiphy_wait_aneg(struct eth_device *dev) 172 { 173 uint32_t start; 174 uint16_t status; 175 176 /* 177 * Wait for AN completion 178 */ 179 start = get_timer_masked(); 180 do { 181 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { 182 printf("%s: Autonegotiation timeout\n", dev->name); 183 return -1; 184 } 185 186 if (miiphy_read(dev->name, CONFIG_FEC_MXC_PHYADDR, 187 PHY_BMSR, &status)) { 188 printf("%s: Autonegotiation failed. status: 0x%04x\n", 189 dev->name, status); 190 return -1; 191 } 192 } while (!(status & PHY_BMSR_LS)); 193 194 return 0; 195 } 196 static int fec_rx_task_enable(struct fec_priv *fec) 197 { 198 writel(1 << 24, &fec->eth->r_des_active); 199 return 0; 200 } 201 202 static int fec_rx_task_disable(struct fec_priv *fec) 203 { 204 return 0; 205 } 206 207 static int fec_tx_task_enable(struct fec_priv *fec) 208 { 209 writel(1 << 24, &fec->eth->x_des_active); 210 return 0; 211 } 212 213 static int fec_tx_task_disable(struct fec_priv *fec) 214 { 215 return 0; 216 } 217 218 /** 219 * Initialize receive task's buffer descriptors 220 * @param[in] fec all we know about the device yet 221 * @param[in] count receive buffer count to be allocated 222 * @param[in] size size of each receive buffer 223 * @return 0 on success 224 * 225 * For this task we need additional memory for the data buffers. And each 226 * data buffer requires some alignment. Thy must be aligned to a specific 227 * boundary each (DB_DATA_ALIGNMENT). 228 */ 229 static int fec_rbd_init(struct fec_priv *fec, int count, int size) 230 { 231 int ix; 232 uint32_t p = 0; 233 234 /* reserve data memory and consider alignment */ 235 if (fec->rdb_ptr == NULL) 236 fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT); 237 p = (uint32_t)fec->rdb_ptr; 238 if (!p) { 239 puts("fec_imx27: not enough malloc memory!\n"); 240 return -ENOMEM; 241 } 242 memset((void *)p, 0, size * count + DB_DATA_ALIGNMENT); 243 p += DB_DATA_ALIGNMENT-1; 244 p &= ~(DB_DATA_ALIGNMENT-1); 245 246 for (ix = 0; ix < count; ix++) { 247 writel(p, &fec->rbd_base[ix].data_pointer); 248 p += size; 249 writew(FEC_RBD_EMPTY, &fec->rbd_base[ix].status); 250 writew(0, &fec->rbd_base[ix].data_length); 251 } 252 /* 253 * mark the last RBD to close the ring 254 */ 255 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[ix - 1].status); 256 fec->rbd_index = 0; 257 258 return 0; 259 } 260 261 /** 262 * Initialize transmit task's buffer descriptors 263 * @param[in] fec all we know about the device yet 264 * 265 * Transmit buffers are created externally. We only have to init the BDs here.\n 266 * Note: There is a race condition in the hardware. When only one BD is in 267 * use it must be marked with the WRAP bit to use it for every transmitt. 268 * This bit in combination with the READY bit results into double transmit 269 * of each data buffer. It seems the state machine checks READY earlier then 270 * resetting it after the first transfer. 271 * Using two BDs solves this issue. 272 */ 273 static void fec_tbd_init(struct fec_priv *fec) 274 { 275 writew(0x0000, &fec->tbd_base[0].status); 276 writew(FEC_TBD_WRAP, &fec->tbd_base[1].status); 277 fec->tbd_index = 0; 278 } 279 280 /** 281 * Mark the given read buffer descriptor as free 282 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0 283 * @param[in] pRbd buffer descriptor to mark free again 284 */ 285 static void fec_rbd_clean(int last, struct fec_bd *pRbd) 286 { 287 /* 288 * Reset buffer descriptor as empty 289 */ 290 if (last) 291 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &pRbd->status); 292 else 293 writew(FEC_RBD_EMPTY, &pRbd->status); 294 /* 295 * no data in it 296 */ 297 writew(0, &pRbd->data_length); 298 } 299 300 static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac) 301 { 302 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; 303 int i; 304 305 for (i = 0; i < 6; i++) 306 mac[6-1-i] = readl(&iim->iim_bank_area0[IIM0_MAC + i]); 307 308 return is_valid_ether_addr(mac); 309 } 310 311 static int fec_set_hwaddr(struct eth_device *dev, unsigned char *mac) 312 { 313 struct fec_priv *fec = (struct fec_priv *)dev->priv; 314 315 writel(0, &fec->eth->iaddr1); 316 writel(0, &fec->eth->iaddr2); 317 writel(0, &fec->eth->gaddr1); 318 writel(0, &fec->eth->gaddr2); 319 320 /* 321 * Set physical address 322 */ 323 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3], 324 &fec->eth->paddr1); 325 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2); 326 327 return 0; 328 } 329 330 /** 331 * Start the FEC engine 332 * @param[in] dev Our device to handle 333 */ 334 static int fec_open(struct eth_device *edev) 335 { 336 struct fec_priv *fec = (struct fec_priv *)edev->priv; 337 338 debug("fec_open: fec_open(dev)\n"); 339 /* full-duplex, heartbeat disabled */ 340 writel(1 << 2, &fec->eth->x_cntrl); 341 fec->rbd_index = 0; 342 343 /* 344 * Enable FEC-Lite controller 345 */ 346 writel(FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl); 347 348 miiphy_wait_aneg(edev); 349 miiphy_speed(edev->name, CONFIG_FEC_MXC_PHYADDR); 350 miiphy_duplex(edev->name, CONFIG_FEC_MXC_PHYADDR); 351 352 /* 353 * Enable SmartDMA receive task 354 */ 355 fec_rx_task_enable(fec); 356 357 udelay(100000); 358 return 0; 359 } 360 361 static int fec_init(struct eth_device *dev, bd_t* bd) 362 { 363 uint32_t base; 364 struct fec_priv *fec = (struct fec_priv *)dev->priv; 365 366 /* 367 * reserve memory for both buffer descriptor chains at once 368 * Datasheet forces the startaddress of each chain is 16 byte 369 * aligned 370 */ 371 if (fec->base_ptr == NULL) 372 fec->base_ptr = malloc((2 + FEC_RBD_NUM) * 373 sizeof(struct fec_bd) + DB_ALIGNMENT); 374 base = (uint32_t)fec->base_ptr; 375 if (!base) { 376 puts("fec_imx27: not enough malloc memory!\n"); 377 return -ENOMEM; 378 } 379 memset((void *)base, 0, (2 + FEC_RBD_NUM) * 380 sizeof(struct fec_bd) + DB_ALIGNMENT); 381 base += (DB_ALIGNMENT-1); 382 base &= ~(DB_ALIGNMENT-1); 383 384 fec->rbd_base = (struct fec_bd *)base; 385 386 base += FEC_RBD_NUM * sizeof(struct fec_bd); 387 388 fec->tbd_base = (struct fec_bd *)base; 389 390 /* 391 * Set interrupt mask register 392 */ 393 writel(0x00000000, &fec->eth->imask); 394 395 /* 396 * Clear FEC-Lite interrupt event register(IEVENT) 397 */ 398 writel(0xffffffff, &fec->eth->ievent); 399 400 401 /* 402 * Set FEC-Lite receive control register(R_CNTRL): 403 */ 404 if (fec->xcv_type == SEVENWIRE) { 405 /* 406 * Frame length=1518; 7-wire mode 407 */ 408 writel(0x05ee0020, &fec->eth->r_cntrl); /* FIXME 0x05ee0000 */ 409 } else { 410 /* 411 * Frame length=1518; MII mode; 412 */ 413 writel(0x05ee0024, &fec->eth->r_cntrl); /* FIXME 0x05ee0004 */ 414 /* 415 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock 416 * and do not drop the Preamble. 417 */ 418 writel((((imx_get_ahbclk() / 1000000) + 2) / 5) << 1, 419 &fec->eth->mii_speed); 420 debug("fec_init: mii_speed %#lx\n", 421 (((imx_get_ahbclk() / 1000000) + 2) / 5) << 1); 422 } 423 /* 424 * Set Opcode/Pause Duration Register 425 */ 426 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */ 427 writel(0x2, &fec->eth->x_wmrk); 428 /* 429 * Set multicast address filter 430 */ 431 writel(0x00000000, &fec->eth->gaddr1); 432 writel(0x00000000, &fec->eth->gaddr2); 433 434 435 /* clear MIB RAM */ 436 long *mib_ptr = (long *)(IMX_FEC_BASE + 0x200); 437 while (mib_ptr <= (long *)(IMX_FEC_BASE + 0x2FC)) 438 *mib_ptr++ = 0; 439 440 /* FIFO receive start register */ 441 writel(0x520, &fec->eth->r_fstart); 442 443 /* size and address of each buffer */ 444 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr); 445 writel((uint32_t)fec->tbd_base, &fec->eth->etdsr); 446 writel((uint32_t)fec->rbd_base, &fec->eth->erdsr); 447 448 /* 449 * Initialize RxBD/TxBD rings 450 */ 451 if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) { 452 free(fec->base_ptr); 453 return -ENOMEM; 454 } 455 fec_tbd_init(fec); 456 457 458 if (fec->xcv_type != SEVENWIRE) 459 miiphy_restart_aneg(dev); 460 461 fec_open(dev); 462 return 0; 463 } 464 465 /** 466 * Halt the FEC engine 467 * @param[in] dev Our device to handle 468 */ 469 static void fec_halt(struct eth_device *dev) 470 { 471 struct fec_priv *fec = &gfec; 472 int counter = 0xffff; 473 474 /* 475 * issue graceful stop command to the FEC transmitter if necessary 476 */ 477 writel(FEC_ECNTRL_RESET | readl(&fec->eth->x_cntrl), 478 &fec->eth->x_cntrl); 479 480 debug("eth_halt: wait for stop regs\n"); 481 /* 482 * wait for graceful stop to register 483 */ 484 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA))) 485 ; /* FIXME ensure time */ 486 487 /* 488 * Disable SmartDMA tasks 489 */ 490 fec_tx_task_disable(fec); 491 fec_rx_task_disable(fec); 492 493 /* 494 * Disable the Ethernet Controller 495 * Note: this will also reset the BD index counter! 496 */ 497 writel(0, &fec->eth->ecntrl); 498 fec->rbd_index = 0; 499 fec->tbd_index = 0; 500 debug("eth_halt: done\n"); 501 } 502 503 /** 504 * Transmit one frame 505 * @param[in] dev Our ethernet device to handle 506 * @param[in] packet Pointer to the data to be transmitted 507 * @param[in] length Data count in bytes 508 * @return 0 on success 509 */ 510 static int fec_send(struct eth_device *dev, volatile void* packet, int length) 511 { 512 unsigned int status; 513 514 /* 515 * This routine transmits one frame. This routine only accepts 516 * 6-byte Ethernet addresses. 517 */ 518 struct fec_priv *fec = (struct fec_priv *)dev->priv; 519 520 /* 521 * Check for valid length of data. 522 */ 523 if ((length > 1500) || (length <= 0)) { 524 printf("Payload (%d) to large!\n", length); 525 return -1; 526 } 527 528 /* 529 * Setup the transmit buffer 530 * Note: We are always using the first buffer for transmission, 531 * the second will be empty and only used to stop the DMA engine 532 */ 533 writew(length, &fec->tbd_base[fec->tbd_index].data_length); 534 writel((uint32_t)packet, &fec->tbd_base[fec->tbd_index].data_pointer); 535 /* 536 * update BD's status now 537 * This block: 538 * - is always the last in a chain (means no chain) 539 * - should transmitt the CRC 540 * - might be the last BD in the list, so the address counter should 541 * wrap (-> keep the WRAP flag) 542 */ 543 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP; 544 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; 545 writew(status, &fec->tbd_base[fec->tbd_index].status); 546 547 /* 548 * Enable SmartDMA transmit task 549 */ 550 fec_tx_task_enable(fec); 551 552 /* 553 * wait until frame is sent . 554 */ 555 while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) { 556 /* FIXME: Timeout */ 557 } 558 debug("fec_send: status 0x%x index %d\n", 559 readw(&fec->tbd_base[fec->tbd_index].status), 560 fec->tbd_index); 561 /* for next transmission use the other buffer */ 562 if (fec->tbd_index) 563 fec->tbd_index = 0; 564 else 565 fec->tbd_index = 1; 566 567 return 0; 568 } 569 570 /** 571 * Pull one frame from the card 572 * @param[in] dev Our ethernet device to handle 573 * @return Length of packet read 574 */ 575 static int fec_recv(struct eth_device *dev) 576 { 577 struct fec_priv *fec = (struct fec_priv *)dev->priv; 578 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index]; 579 unsigned long ievent; 580 int frame_length, len = 0; 581 struct nbuf *frame; 582 uint16_t bd_status; 583 uchar buff[FEC_MAX_PKT_SIZE]; 584 585 /* 586 * Check if any critical events have happened 587 */ 588 ievent = readl(&fec->eth->ievent); 589 writel(ievent, &fec->eth->ievent); 590 debug("fec_recv: ievent 0x%x\n", ievent); 591 if (ievent & FEC_IEVENT_BABR) { 592 fec_halt(dev); 593 fec_init(dev, fec->bd); 594 printf("some error: 0x%08lx\n", ievent); 595 return 0; 596 } 597 if (ievent & FEC_IEVENT_HBERR) { 598 /* Heartbeat error */ 599 writel(0x00000001 | readl(&fec->eth->x_cntrl), 600 &fec->eth->x_cntrl); 601 } 602 if (ievent & FEC_IEVENT_GRA) { 603 /* Graceful stop complete */ 604 if (readl(&fec->eth->x_cntrl) & 0x00000001) { 605 fec_halt(dev); 606 writel(~0x00000001 & readl(&fec->eth->x_cntrl), 607 &fec->eth->x_cntrl); 608 fec_init(dev, fec->bd); 609 } 610 } 611 612 /* 613 * ensure reading the right buffer status 614 */ 615 bd_status = readw(&rbd->status); 616 debug("fec_recv: status 0x%x\n", bd_status); 617 618 if (!(bd_status & FEC_RBD_EMPTY)) { 619 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) && 620 ((readw(&rbd->data_length) - 4) > 14)) { 621 /* 622 * Get buffer address and size 623 */ 624 frame = (struct nbuf *)readl(&rbd->data_pointer); 625 frame_length = readw(&rbd->data_length) - 4; 626 /* 627 * Fill the buffer and pass it to upper layers 628 */ 629 memcpy(buff, frame->data, frame_length); 630 NetReceive(buff, frame_length); 631 len = frame_length; 632 } else { 633 if (bd_status & FEC_RBD_ERR) 634 printf("error frame: 0x%08lx 0x%08x\n", 635 (ulong)rbd->data_pointer, 636 bd_status); 637 } 638 /* 639 * free the current buffer, restart the engine 640 * and move forward to the next buffer 641 */ 642 fec_rbd_clean(fec->rbd_index == (FEC_RBD_NUM - 1) ? 1 : 0, rbd); 643 fec_rx_task_enable(fec); 644 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM; 645 } 646 debug("fec_recv: stop\n"); 647 648 return len; 649 } 650 651 static int fec_probe(bd_t *bd) 652 { 653 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; 654 struct eth_device *edev; 655 struct fec_priv *fec = &gfec; 656 unsigned char ethaddr_str[20]; 657 unsigned char ethaddr[6]; 658 char *tmp = getenv("ethaddr"); 659 char *end; 660 661 /* enable FEC clock */ 662 writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1); 663 writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0); 664 665 /* create and fill edev struct */ 666 edev = (struct eth_device *)malloc(sizeof(struct eth_device)); 667 if (!edev) { 668 puts("fec_imx27: not enough malloc memory!\n"); 669 return -ENOMEM; 670 } 671 edev->priv = fec; 672 edev->init = fec_init; 673 edev->send = fec_send; 674 edev->recv = fec_recv; 675 edev->halt = fec_halt; 676 677 fec->eth = (struct ethernet_regs *)IMX_FEC_BASE; 678 fec->bd = bd; 679 680 fec->xcv_type = MII100; 681 682 /* Reset chip. */ 683 writel(FEC_ECNTRL_RESET, &fec->eth->ecntrl); 684 while (readl(&fec->eth->ecntrl) & 1) 685 udelay(10); 686 687 /* 688 * Set interrupt mask register 689 */ 690 writel(0x00000000, &fec->eth->imask); 691 692 /* 693 * Clear FEC-Lite interrupt event register(IEVENT) 694 */ 695 writel(0xffffffff, &fec->eth->ievent); 696 697 /* 698 * Set FEC-Lite receive control register(R_CNTRL): 699 */ 700 /* 701 * Frame length=1518; MII mode; 702 */ 703 writel(0x05ee0024, &fec->eth->r_cntrl); /* FIXME 0x05ee0004 */ 704 /* 705 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock 706 * and do not drop the Preamble. 707 */ 708 writel((((imx_get_ahbclk() / 1000000) + 2) / 5) << 1, 709 &fec->eth->mii_speed); 710 debug("fec_init: mii_speed %#lx\n", 711 (((imx_get_ahbclk() / 1000000) + 2) / 5) << 1); 712 713 sprintf(edev->name, "FEC_MXC"); 714 715 miiphy_register(edev->name, fec_miiphy_read, fec_miiphy_write); 716 717 eth_register(edev); 718 719 if ((NULL != tmp) && (12 <= strlen(tmp))) { 720 int i; 721 /* convert MAC from string to int */ 722 for (i = 0; i < 6; i++) { 723 ethaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; 724 if (tmp) 725 tmp = (*end) ? end + 1 : end; 726 } 727 } else if (fec_get_hwaddr(edev, ethaddr) == 0) { 728 printf("got MAC address from EEPROM: %pM\n", ethaddr); 729 setenv("ethaddr", (char *)ethaddr_str); 730 } 731 memcpy(edev->enetaddr, ethaddr, 6); 732 fec_set_hwaddr(edev, ethaddr); 733 734 return 0; 735 } 736 737 int fecmxc_initialize(bd_t *bd) 738 { 739 int lout = 1; 740 741 debug("eth_init: fec_probe(bd)\n"); 742 lout = fec_probe(bd); 743 744 return lout; 745 } 746