1 /* 2 * Opencore 10/100 ethernet mac driver 3 * 4 * Copyright (C) 2007-2008 Avionic Design Development GmbH 5 * Copyright (C) 2008-2009 Avionic Design GmbH 6 * Thierry Reding <thierry.reding@avionic-design.de> 7 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #include <common.h> 15 #include <linux/io.h> 16 #include <malloc.h> 17 #include <net.h> 18 #include <miiphy.h> 19 #include <asm/cache.h> 20 21 /* register offsets */ 22 #define MODER 0x00 23 #define INT_SOURCE 0x04 24 #define INT_MASK 0x08 25 #define IPGT 0x0c 26 #define IPGR1 0x10 27 #define IPGR2 0x14 28 #define PACKETLEN 0x18 29 #define COLLCONF 0x1c 30 #define TX_BD_NUM 0x20 31 #define CTRLMODER 0x24 32 #define MIIMODER 0x28 33 #define MIICOMMAND 0x2c 34 #define MIIADDRESS 0x30 35 #define MIITX_DATA 0x34 36 #define MIIRX_DATA 0x38 37 #define MIISTATUS 0x3c 38 #define MAC_ADDR0 0x40 39 #define MAC_ADDR1 0x44 40 #define ETH_HASH0 0x48 41 #define ETH_HASH1 0x4c 42 #define ETH_TXCTRL 0x50 43 44 /* mode register */ 45 #define MODER_RXEN (1 << 0) /* receive enable */ 46 #define MODER_TXEN (1 << 1) /* transmit enable */ 47 #define MODER_NOPRE (1 << 2) /* no preamble */ 48 #define MODER_BRO (1 << 3) /* broadcast address */ 49 #define MODER_IAM (1 << 4) /* individual address mode */ 50 #define MODER_PRO (1 << 5) /* promiscuous mode */ 51 #define MODER_IFG (1 << 6) /* interframe gap for incoming frames */ 52 #define MODER_LOOP (1 << 7) /* loopback */ 53 #define MODER_NBO (1 << 8) /* no back-off */ 54 #define MODER_EDE (1 << 9) /* excess defer enable */ 55 #define MODER_FULLD (1 << 10) /* full duplex */ 56 #define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */ 57 #define MODER_DCRC (1 << 12) /* delayed CRC enable */ 58 #define MODER_CRC (1 << 13) /* CRC enable */ 59 #define MODER_HUGE (1 << 14) /* huge packets enable */ 60 #define MODER_PAD (1 << 15) /* padding enabled */ 61 #define MODER_RSM (1 << 16) /* receive small packets */ 62 63 /* interrupt source and mask registers */ 64 #define INT_MASK_TXF (1 << 0) /* transmit frame */ 65 #define INT_MASK_TXE (1 << 1) /* transmit error */ 66 #define INT_MASK_RXF (1 << 2) /* receive frame */ 67 #define INT_MASK_RXE (1 << 3) /* receive error */ 68 #define INT_MASK_BUSY (1 << 4) 69 #define INT_MASK_TXC (1 << 5) /* transmit control frame */ 70 #define INT_MASK_RXC (1 << 6) /* receive control frame */ 71 72 #define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE) 73 #define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE) 74 75 #define INT_MASK_ALL ( \ 76 INT_MASK_TXF | INT_MASK_TXE | \ 77 INT_MASK_RXF | INT_MASK_RXE | \ 78 INT_MASK_TXC | INT_MASK_RXC | \ 79 INT_MASK_BUSY \ 80 ) 81 82 /* packet length register */ 83 #define PACKETLEN_MIN(min) (((min) & 0xffff) << 16) 84 #define PACKETLEN_MAX(max) (((max) & 0xffff) << 0) 85 #define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \ 86 PACKETLEN_MAX(max)) 87 88 /* transmit buffer number register */ 89 #define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80) 90 91 /* control module mode register */ 92 #define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */ 93 #define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */ 94 #define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */ 95 96 /* MII mode register */ 97 #define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */ 98 #define MIIMODER_NOPRE (1 << 8) /* no preamble */ 99 100 /* MII command register */ 101 #define MIICOMMAND_SCAN (1 << 0) /* scan status */ 102 #define MIICOMMAND_READ (1 << 1) /* read status */ 103 #define MIICOMMAND_WRITE (1 << 2) /* write control data */ 104 105 /* MII address register */ 106 #define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0) 107 #define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8) 108 #define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \ 109 MIIADDRESS_RGAD(reg)) 110 111 /* MII transmit data register */ 112 #define MIITX_DATA_VAL(x) ((x) & 0xffff) 113 114 /* MII receive data register */ 115 #define MIIRX_DATA_VAL(x) ((x) & 0xffff) 116 117 /* MII status register */ 118 #define MIISTATUS_LINKFAIL (1 << 0) 119 #define MIISTATUS_BUSY (1 << 1) 120 #define MIISTATUS_INVALID (1 << 2) 121 122 /* TX buffer descriptor */ 123 #define TX_BD_CS (1 << 0) /* carrier sense lost */ 124 #define TX_BD_DF (1 << 1) /* defer indication */ 125 #define TX_BD_LC (1 << 2) /* late collision */ 126 #define TX_BD_RL (1 << 3) /* retransmission limit */ 127 #define TX_BD_RETRY_MASK (0x00f0) 128 #define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4) 129 #define TX_BD_UR (1 << 8) /* transmitter underrun */ 130 #define TX_BD_CRC (1 << 11) /* TX CRC enable */ 131 #define TX_BD_PAD (1 << 12) /* pad enable */ 132 #define TX_BD_WRAP (1 << 13) 133 #define TX_BD_IRQ (1 << 14) /* interrupt request enable */ 134 #define TX_BD_READY (1 << 15) /* TX buffer ready */ 135 #define TX_BD_LEN(x) (((x) & 0xffff) << 16) 136 #define TX_BD_LEN_MASK (0xffff << 16) 137 138 #define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \ 139 TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR) 140 141 /* RX buffer descriptor */ 142 #define RX_BD_LC (1 << 0) /* late collision */ 143 #define RX_BD_CRC (1 << 1) /* RX CRC error */ 144 #define RX_BD_SF (1 << 2) /* short frame */ 145 #define RX_BD_TL (1 << 3) /* too long */ 146 #define RX_BD_DN (1 << 4) /* dribble nibble */ 147 #define RX_BD_IS (1 << 5) /* invalid symbol */ 148 #define RX_BD_OR (1 << 6) /* receiver overrun */ 149 #define RX_BD_MISS (1 << 7) 150 #define RX_BD_CF (1 << 8) /* control frame */ 151 #define RX_BD_WRAP (1 << 13) 152 #define RX_BD_IRQ (1 << 14) /* interrupt request enable */ 153 #define RX_BD_EMPTY (1 << 15) 154 #define RX_BD_LEN(x) (((x) & 0xffff) << 16) 155 156 #define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \ 157 RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS) 158 159 #define ETHOC_BUFSIZ 1536 160 #define ETHOC_ZLEN 64 161 #define ETHOC_BD_BASE 0x400 162 #define ETHOC_TIMEOUT (HZ / 2) 163 #define ETHOC_MII_TIMEOUT (1 + (HZ / 5)) 164 #define ETHOC_IOSIZE 0x54 165 166 /** 167 * struct ethoc - driver-private device structure 168 * @num_tx: number of send buffers 169 * @cur_tx: last send buffer written 170 * @dty_tx: last buffer actually sent 171 * @num_rx: number of receive buffers 172 * @cur_rx: current receive buffer 173 */ 174 struct ethoc { 175 u32 num_tx; 176 u32 cur_tx; 177 u32 dty_tx; 178 u32 num_rx; 179 u32 cur_rx; 180 void __iomem *iobase; 181 }; 182 183 /** 184 * struct ethoc_bd - buffer descriptor 185 * @stat: buffer statistics 186 * @addr: physical memory address 187 */ 188 struct ethoc_bd { 189 u32 stat; 190 u32 addr; 191 }; 192 193 static inline u32 ethoc_read(struct ethoc *priv, size_t offset) 194 { 195 return readl(priv->iobase + offset); 196 } 197 198 static inline void ethoc_write(struct ethoc *priv, size_t offset, u32 data) 199 { 200 writel(data, priv->iobase + offset); 201 } 202 203 static inline void ethoc_read_bd(struct ethoc *priv, int index, 204 struct ethoc_bd *bd) 205 { 206 size_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd)); 207 bd->stat = ethoc_read(priv, offset + 0); 208 bd->addr = ethoc_read(priv, offset + 4); 209 } 210 211 static inline void ethoc_write_bd(struct ethoc *priv, int index, 212 const struct ethoc_bd *bd) 213 { 214 size_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd)); 215 ethoc_write(priv, offset + 0, bd->stat); 216 ethoc_write(priv, offset + 4, bd->addr); 217 } 218 219 static int ethoc_set_mac_address(struct eth_device *dev) 220 { 221 struct ethoc *priv = (struct ethoc *)dev->priv; 222 u8 *mac = dev->enetaddr; 223 224 ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) | 225 (mac[4] << 8) | (mac[5] << 0)); 226 ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0)); 227 return 0; 228 } 229 230 static inline void ethoc_ack_irq(struct ethoc *priv, u32 mask) 231 { 232 ethoc_write(priv, INT_SOURCE, mask); 233 } 234 235 static inline void ethoc_enable_rx_and_tx(struct ethoc *priv) 236 { 237 u32 mode = ethoc_read(priv, MODER); 238 mode |= MODER_RXEN | MODER_TXEN; 239 ethoc_write(priv, MODER, mode); 240 } 241 242 static inline void ethoc_disable_rx_and_tx(struct ethoc *priv) 243 { 244 u32 mode = ethoc_read(priv, MODER); 245 mode &= ~(MODER_RXEN | MODER_TXEN); 246 ethoc_write(priv, MODER, mode); 247 } 248 249 static int ethoc_init_ring(struct ethoc *priv) 250 { 251 struct ethoc_bd bd; 252 int i; 253 254 priv->cur_tx = 0; 255 priv->dty_tx = 0; 256 priv->cur_rx = 0; 257 258 /* setup transmission buffers */ 259 bd.stat = TX_BD_IRQ | TX_BD_CRC; 260 261 for (i = 0; i < priv->num_tx; i++) { 262 if (i == priv->num_tx - 1) 263 bd.stat |= TX_BD_WRAP; 264 265 ethoc_write_bd(priv, i, &bd); 266 } 267 268 bd.stat = RX_BD_EMPTY | RX_BD_IRQ; 269 270 for (i = 0; i < priv->num_rx; i++) { 271 bd.addr = (u32)net_rx_packets[i]; 272 if (i == priv->num_rx - 1) 273 bd.stat |= RX_BD_WRAP; 274 275 flush_dcache_range(bd.addr, bd.addr + PKTSIZE_ALIGN); 276 ethoc_write_bd(priv, priv->num_tx + i, &bd); 277 } 278 279 return 0; 280 } 281 282 static int ethoc_reset(struct ethoc *priv) 283 { 284 u32 mode; 285 286 /* TODO: reset controller? */ 287 288 ethoc_disable_rx_and_tx(priv); 289 290 /* TODO: setup registers */ 291 292 /* enable FCS generation and automatic padding */ 293 mode = ethoc_read(priv, MODER); 294 mode |= MODER_CRC | MODER_PAD; 295 ethoc_write(priv, MODER, mode); 296 297 /* set full-duplex mode */ 298 mode = ethoc_read(priv, MODER); 299 mode |= MODER_FULLD; 300 ethoc_write(priv, MODER, mode); 301 ethoc_write(priv, IPGT, 0x15); 302 303 ethoc_ack_irq(priv, INT_MASK_ALL); 304 ethoc_enable_rx_and_tx(priv); 305 return 0; 306 } 307 308 static int ethoc_init(struct eth_device *dev, bd_t * bd) 309 { 310 struct ethoc *priv = (struct ethoc *)dev->priv; 311 printf("ethoc\n"); 312 313 priv->num_tx = 1; 314 priv->num_rx = PKTBUFSRX; 315 ethoc_write(priv, TX_BD_NUM, priv->num_tx); 316 ethoc_init_ring(priv); 317 ethoc_reset(priv); 318 319 return 0; 320 } 321 322 static int ethoc_update_rx_stats(struct ethoc_bd *bd) 323 { 324 int ret = 0; 325 326 if (bd->stat & RX_BD_TL) { 327 debug("ETHOC: " "RX: frame too long\n"); 328 ret++; 329 } 330 331 if (bd->stat & RX_BD_SF) { 332 debug("ETHOC: " "RX: frame too short\n"); 333 ret++; 334 } 335 336 if (bd->stat & RX_BD_DN) 337 debug("ETHOC: " "RX: dribble nibble\n"); 338 339 if (bd->stat & RX_BD_CRC) { 340 debug("ETHOC: " "RX: wrong CRC\n"); 341 ret++; 342 } 343 344 if (bd->stat & RX_BD_OR) { 345 debug("ETHOC: " "RX: overrun\n"); 346 ret++; 347 } 348 349 if (bd->stat & RX_BD_LC) { 350 debug("ETHOC: " "RX: late collision\n"); 351 ret++; 352 } 353 354 return ret; 355 } 356 357 static int ethoc_rx(struct ethoc *priv, int limit) 358 { 359 int count; 360 361 for (count = 0; count < limit; ++count) { 362 u32 entry; 363 struct ethoc_bd bd; 364 365 entry = priv->num_tx + (priv->cur_rx % priv->num_rx); 366 ethoc_read_bd(priv, entry, &bd); 367 if (bd.stat & RX_BD_EMPTY) 368 break; 369 370 debug("%s(): RX buffer %d, %x received\n", 371 __func__, priv->cur_rx, bd.stat); 372 if (ethoc_update_rx_stats(&bd) == 0) { 373 int size = bd.stat >> 16; 374 size -= 4; /* strip the CRC */ 375 net_process_received_packet((void *)bd.addr, size); 376 } 377 378 /* clear the buffer descriptor so it can be reused */ 379 flush_dcache_range(bd.addr, bd.addr + PKTSIZE_ALIGN); 380 bd.stat &= ~RX_BD_STATS; 381 bd.stat |= RX_BD_EMPTY; 382 ethoc_write_bd(priv, entry, &bd); 383 priv->cur_rx++; 384 } 385 386 return count; 387 } 388 389 static int ethoc_update_tx_stats(struct ethoc_bd *bd) 390 { 391 if (bd->stat & TX_BD_LC) 392 debug("ETHOC: " "TX: late collision\n"); 393 394 if (bd->stat & TX_BD_RL) 395 debug("ETHOC: " "TX: retransmit limit\n"); 396 397 if (bd->stat & TX_BD_UR) 398 debug("ETHOC: " "TX: underrun\n"); 399 400 if (bd->stat & TX_BD_CS) 401 debug("ETHOC: " "TX: carrier sense lost\n"); 402 403 return 0; 404 } 405 406 static void ethoc_tx(struct ethoc *priv) 407 { 408 u32 entry = priv->dty_tx % priv->num_tx; 409 struct ethoc_bd bd; 410 411 ethoc_read_bd(priv, entry, &bd); 412 if ((bd.stat & TX_BD_READY) == 0) 413 (void)ethoc_update_tx_stats(&bd); 414 } 415 416 static int ethoc_send(struct eth_device *dev, void *packet, int length) 417 { 418 struct ethoc *priv = (struct ethoc *)dev->priv; 419 struct ethoc_bd bd; 420 u32 entry; 421 u32 pending; 422 int tmo; 423 424 entry = priv->cur_tx % priv->num_tx; 425 ethoc_read_bd(priv, entry, &bd); 426 if (unlikely(length < ETHOC_ZLEN)) 427 bd.stat |= TX_BD_PAD; 428 else 429 bd.stat &= ~TX_BD_PAD; 430 bd.addr = (u32)packet; 431 432 flush_dcache_range(bd.addr, bd.addr + length); 433 bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK); 434 bd.stat |= TX_BD_LEN(length); 435 ethoc_write_bd(priv, entry, &bd); 436 437 /* start transmit */ 438 bd.stat |= TX_BD_READY; 439 ethoc_write_bd(priv, entry, &bd); 440 441 /* wait for transfer to succeed */ 442 tmo = get_timer(0) + 5 * CONFIG_SYS_HZ; 443 while (1) { 444 pending = ethoc_read(priv, INT_SOURCE); 445 ethoc_ack_irq(priv, pending & ~INT_MASK_RX); 446 if (pending & INT_MASK_BUSY) 447 debug("%s(): packet dropped\n", __func__); 448 449 if (pending & INT_MASK_TX) { 450 ethoc_tx(priv); 451 break; 452 } 453 if (get_timer(0) >= tmo) { 454 debug("%s(): timed out\n", __func__); 455 return -1; 456 } 457 } 458 459 debug("%s(): packet sent\n", __func__); 460 return 0; 461 } 462 463 static void ethoc_halt(struct eth_device *dev) 464 { 465 ethoc_disable_rx_and_tx(dev->priv); 466 } 467 468 static int ethoc_recv(struct eth_device *dev) 469 { 470 struct ethoc *priv = (struct ethoc *)dev->priv; 471 u32 pending; 472 473 pending = ethoc_read(priv, INT_SOURCE); 474 ethoc_ack_irq(priv, pending); 475 if (pending & INT_MASK_BUSY) 476 debug("%s(): packet dropped\n", __func__); 477 if (pending & INT_MASK_RX) { 478 debug("%s(): rx irq\n", __func__); 479 ethoc_rx(priv, PKTBUFSRX); 480 } 481 482 return 0; 483 } 484 485 int ethoc_initialize(u8 dev_num, int base_addr) 486 { 487 struct ethoc *priv; 488 struct eth_device *dev; 489 490 priv = malloc(sizeof(*priv)); 491 if (!priv) 492 return 0; 493 dev = malloc(sizeof(*dev)); 494 if (!dev) { 495 free(priv); 496 return 0; 497 } 498 499 memset(dev, 0, sizeof(*dev)); 500 dev->priv = priv; 501 dev->iobase = base_addr; 502 dev->init = ethoc_init; 503 dev->halt = ethoc_halt; 504 dev->send = ethoc_send; 505 dev->recv = ethoc_recv; 506 dev->write_hwaddr = ethoc_set_mac_address; 507 sprintf(dev->name, "%s-%hu", "ETHOC", dev_num); 508 priv->iobase = ioremap(dev->iobase, ETHOC_IOSIZE); 509 510 eth_register(dev); 511 return 1; 512 } 513