1 /* 2 * Opencore 10/100 ethernet mac driver 3 * 4 * Copyright (C) 2007-2008 Avionic Design Development GmbH 5 * Copyright (C) 2008-2009 Avionic Design GmbH 6 * Thierry Reding <thierry.reding@avionic-design.de> 7 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw> 8 * Copyright (C) 2016 Cadence Design Systems Inc. 9 * 10 * SPDX-License-Identifier: GPL-2.0 11 */ 12 13 #include <common.h> 14 #include <dm/device.h> 15 #include <dm/platform_data/net_ethoc.h> 16 #include <linux/io.h> 17 #include <malloc.h> 18 #include <net.h> 19 #include <miiphy.h> 20 #include <asm/cache.h> 21 22 /* register offsets */ 23 #define MODER 0x00 24 #define INT_SOURCE 0x04 25 #define INT_MASK 0x08 26 #define IPGT 0x0c 27 #define IPGR1 0x10 28 #define IPGR2 0x14 29 #define PACKETLEN 0x18 30 #define COLLCONF 0x1c 31 #define TX_BD_NUM 0x20 32 #define CTRLMODER 0x24 33 #define MIIMODER 0x28 34 #define MIICOMMAND 0x2c 35 #define MIIADDRESS 0x30 36 #define MIITX_DATA 0x34 37 #define MIIRX_DATA 0x38 38 #define MIISTATUS 0x3c 39 #define MAC_ADDR0 0x40 40 #define MAC_ADDR1 0x44 41 #define ETH_HASH0 0x48 42 #define ETH_HASH1 0x4c 43 #define ETH_TXCTRL 0x50 44 45 /* mode register */ 46 #define MODER_RXEN (1 << 0) /* receive enable */ 47 #define MODER_TXEN (1 << 1) /* transmit enable */ 48 #define MODER_NOPRE (1 << 2) /* no preamble */ 49 #define MODER_BRO (1 << 3) /* broadcast address */ 50 #define MODER_IAM (1 << 4) /* individual address mode */ 51 #define MODER_PRO (1 << 5) /* promiscuous mode */ 52 #define MODER_IFG (1 << 6) /* interframe gap for incoming frames */ 53 #define MODER_LOOP (1 << 7) /* loopback */ 54 #define MODER_NBO (1 << 8) /* no back-off */ 55 #define MODER_EDE (1 << 9) /* excess defer enable */ 56 #define MODER_FULLD (1 << 10) /* full duplex */ 57 #define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */ 58 #define MODER_DCRC (1 << 12) /* delayed CRC enable */ 59 #define MODER_CRC (1 << 13) /* CRC enable */ 60 #define MODER_HUGE (1 << 14) /* huge packets enable */ 61 #define MODER_PAD (1 << 15) /* padding enabled */ 62 #define MODER_RSM (1 << 16) /* receive small packets */ 63 64 /* interrupt source and mask registers */ 65 #define INT_MASK_TXF (1 << 0) /* transmit frame */ 66 #define INT_MASK_TXE (1 << 1) /* transmit error */ 67 #define INT_MASK_RXF (1 << 2) /* receive frame */ 68 #define INT_MASK_RXE (1 << 3) /* receive error */ 69 #define INT_MASK_BUSY (1 << 4) 70 #define INT_MASK_TXC (1 << 5) /* transmit control frame */ 71 #define INT_MASK_RXC (1 << 6) /* receive control frame */ 72 73 #define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE) 74 #define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE) 75 76 #define INT_MASK_ALL ( \ 77 INT_MASK_TXF | INT_MASK_TXE | \ 78 INT_MASK_RXF | INT_MASK_RXE | \ 79 INT_MASK_TXC | INT_MASK_RXC | \ 80 INT_MASK_BUSY \ 81 ) 82 83 /* packet length register */ 84 #define PACKETLEN_MIN(min) (((min) & 0xffff) << 16) 85 #define PACKETLEN_MAX(max) (((max) & 0xffff) << 0) 86 #define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \ 87 PACKETLEN_MAX(max)) 88 89 /* transmit buffer number register */ 90 #define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80) 91 92 /* control module mode register */ 93 #define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */ 94 #define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */ 95 #define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */ 96 97 /* MII mode register */ 98 #define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */ 99 #define MIIMODER_NOPRE (1 << 8) /* no preamble */ 100 101 /* MII command register */ 102 #define MIICOMMAND_SCAN (1 << 0) /* scan status */ 103 #define MIICOMMAND_READ (1 << 1) /* read status */ 104 #define MIICOMMAND_WRITE (1 << 2) /* write control data */ 105 106 /* MII address register */ 107 #define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0) 108 #define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8) 109 #define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \ 110 MIIADDRESS_RGAD(reg)) 111 112 /* MII transmit data register */ 113 #define MIITX_DATA_VAL(x) ((x) & 0xffff) 114 115 /* MII receive data register */ 116 #define MIIRX_DATA_VAL(x) ((x) & 0xffff) 117 118 /* MII status register */ 119 #define MIISTATUS_LINKFAIL (1 << 0) 120 #define MIISTATUS_BUSY (1 << 1) 121 #define MIISTATUS_INVALID (1 << 2) 122 123 /* TX buffer descriptor */ 124 #define TX_BD_CS (1 << 0) /* carrier sense lost */ 125 #define TX_BD_DF (1 << 1) /* defer indication */ 126 #define TX_BD_LC (1 << 2) /* late collision */ 127 #define TX_BD_RL (1 << 3) /* retransmission limit */ 128 #define TX_BD_RETRY_MASK (0x00f0) 129 #define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4) 130 #define TX_BD_UR (1 << 8) /* transmitter underrun */ 131 #define TX_BD_CRC (1 << 11) /* TX CRC enable */ 132 #define TX_BD_PAD (1 << 12) /* pad enable */ 133 #define TX_BD_WRAP (1 << 13) 134 #define TX_BD_IRQ (1 << 14) /* interrupt request enable */ 135 #define TX_BD_READY (1 << 15) /* TX buffer ready */ 136 #define TX_BD_LEN(x) (((x) & 0xffff) << 16) 137 #define TX_BD_LEN_MASK (0xffff << 16) 138 139 #define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \ 140 TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR) 141 142 /* RX buffer descriptor */ 143 #define RX_BD_LC (1 << 0) /* late collision */ 144 #define RX_BD_CRC (1 << 1) /* RX CRC error */ 145 #define RX_BD_SF (1 << 2) /* short frame */ 146 #define RX_BD_TL (1 << 3) /* too long */ 147 #define RX_BD_DN (1 << 4) /* dribble nibble */ 148 #define RX_BD_IS (1 << 5) /* invalid symbol */ 149 #define RX_BD_OR (1 << 6) /* receiver overrun */ 150 #define RX_BD_MISS (1 << 7) 151 #define RX_BD_CF (1 << 8) /* control frame */ 152 #define RX_BD_WRAP (1 << 13) 153 #define RX_BD_IRQ (1 << 14) /* interrupt request enable */ 154 #define RX_BD_EMPTY (1 << 15) 155 #define RX_BD_LEN(x) (((x) & 0xffff) << 16) 156 157 #define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \ 158 RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS) 159 160 #define ETHOC_BUFSIZ 1536 161 #define ETHOC_ZLEN 64 162 #define ETHOC_BD_BASE 0x400 163 #define ETHOC_TIMEOUT (HZ / 2) 164 #define ETHOC_MII_TIMEOUT (1 + (HZ / 5)) 165 #define ETHOC_IOSIZE 0x54 166 167 /** 168 * struct ethoc - driver-private device structure 169 * @num_tx: number of send buffers 170 * @cur_tx: last send buffer written 171 * @dty_tx: last buffer actually sent 172 * @num_rx: number of receive buffers 173 * @cur_rx: current receive buffer 174 */ 175 struct ethoc { 176 u32 num_tx; 177 u32 cur_tx; 178 u32 dty_tx; 179 u32 num_rx; 180 u32 cur_rx; 181 void __iomem *iobase; 182 }; 183 184 /** 185 * struct ethoc_bd - buffer descriptor 186 * @stat: buffer statistics 187 * @addr: physical memory address 188 */ 189 struct ethoc_bd { 190 u32 stat; 191 u32 addr; 192 }; 193 194 static inline u32 ethoc_read(struct ethoc *priv, size_t offset) 195 { 196 return readl(priv->iobase + offset); 197 } 198 199 static inline void ethoc_write(struct ethoc *priv, size_t offset, u32 data) 200 { 201 writel(data, priv->iobase + offset); 202 } 203 204 static inline void ethoc_read_bd(struct ethoc *priv, int index, 205 struct ethoc_bd *bd) 206 { 207 size_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd)); 208 bd->stat = ethoc_read(priv, offset + 0); 209 bd->addr = ethoc_read(priv, offset + 4); 210 } 211 212 static inline void ethoc_write_bd(struct ethoc *priv, int index, 213 const struct ethoc_bd *bd) 214 { 215 size_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd)); 216 ethoc_write(priv, offset + 0, bd->stat); 217 ethoc_write(priv, offset + 4, bd->addr); 218 } 219 220 static int ethoc_write_hwaddr_common(struct ethoc *priv, u8 *mac) 221 { 222 ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) | 223 (mac[4] << 8) | (mac[5] << 0)); 224 ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0)); 225 return 0; 226 } 227 228 static inline void ethoc_ack_irq(struct ethoc *priv, u32 mask) 229 { 230 ethoc_write(priv, INT_SOURCE, mask); 231 } 232 233 static inline void ethoc_enable_rx_and_tx(struct ethoc *priv) 234 { 235 u32 mode = ethoc_read(priv, MODER); 236 mode |= MODER_RXEN | MODER_TXEN; 237 ethoc_write(priv, MODER, mode); 238 } 239 240 static inline void ethoc_disable_rx_and_tx(struct ethoc *priv) 241 { 242 u32 mode = ethoc_read(priv, MODER); 243 mode &= ~(MODER_RXEN | MODER_TXEN); 244 ethoc_write(priv, MODER, mode); 245 } 246 247 static int ethoc_init_ring(struct ethoc *priv) 248 { 249 struct ethoc_bd bd; 250 int i; 251 252 priv->cur_tx = 0; 253 priv->dty_tx = 0; 254 priv->cur_rx = 0; 255 256 /* setup transmission buffers */ 257 bd.stat = TX_BD_IRQ | TX_BD_CRC; 258 bd.addr = 0; 259 260 for (i = 0; i < priv->num_tx; i++) { 261 if (i == priv->num_tx - 1) 262 bd.stat |= TX_BD_WRAP; 263 264 ethoc_write_bd(priv, i, &bd); 265 } 266 267 bd.stat = RX_BD_EMPTY | RX_BD_IRQ; 268 269 for (i = 0; i < priv->num_rx; i++) { 270 bd.addr = virt_to_phys(net_rx_packets[i]); 271 if (i == priv->num_rx - 1) 272 bd.stat |= RX_BD_WRAP; 273 274 flush_dcache_range((ulong)net_rx_packets[i], 275 (ulong)net_rx_packets[i] + PKTSIZE_ALIGN); 276 ethoc_write_bd(priv, priv->num_tx + i, &bd); 277 } 278 279 return 0; 280 } 281 282 static int ethoc_reset(struct ethoc *priv) 283 { 284 u32 mode; 285 286 /* TODO: reset controller? */ 287 288 ethoc_disable_rx_and_tx(priv); 289 290 /* TODO: setup registers */ 291 292 /* enable FCS generation and automatic padding */ 293 mode = ethoc_read(priv, MODER); 294 mode |= MODER_CRC | MODER_PAD; 295 ethoc_write(priv, MODER, mode); 296 297 /* set full-duplex mode */ 298 mode = ethoc_read(priv, MODER); 299 mode |= MODER_FULLD; 300 ethoc_write(priv, MODER, mode); 301 ethoc_write(priv, IPGT, 0x15); 302 303 ethoc_ack_irq(priv, INT_MASK_ALL); 304 ethoc_enable_rx_and_tx(priv); 305 return 0; 306 } 307 308 static int ethoc_init_common(struct ethoc *priv) 309 { 310 priv->num_tx = 1; 311 priv->num_rx = PKTBUFSRX; 312 ethoc_write(priv, TX_BD_NUM, priv->num_tx); 313 ethoc_init_ring(priv); 314 ethoc_reset(priv); 315 316 return 0; 317 } 318 319 static int ethoc_update_rx_stats(struct ethoc_bd *bd) 320 { 321 int ret = 0; 322 323 if (bd->stat & RX_BD_TL) { 324 debug("ETHOC: " "RX: frame too long\n"); 325 ret++; 326 } 327 328 if (bd->stat & RX_BD_SF) { 329 debug("ETHOC: " "RX: frame too short\n"); 330 ret++; 331 } 332 333 if (bd->stat & RX_BD_DN) 334 debug("ETHOC: " "RX: dribble nibble\n"); 335 336 if (bd->stat & RX_BD_CRC) { 337 debug("ETHOC: " "RX: wrong CRC\n"); 338 ret++; 339 } 340 341 if (bd->stat & RX_BD_OR) { 342 debug("ETHOC: " "RX: overrun\n"); 343 ret++; 344 } 345 346 if (bd->stat & RX_BD_LC) { 347 debug("ETHOC: " "RX: late collision\n"); 348 ret++; 349 } 350 351 return ret; 352 } 353 354 static int ethoc_rx_common(struct ethoc *priv, uchar **packetp) 355 { 356 struct ethoc_bd bd; 357 u32 i = priv->cur_rx % priv->num_rx; 358 u32 entry = priv->num_tx + i; 359 360 ethoc_read_bd(priv, entry, &bd); 361 if (bd.stat & RX_BD_EMPTY) 362 return -EAGAIN; 363 364 debug("%s(): RX buffer %d, %x received\n", 365 __func__, priv->cur_rx, bd.stat); 366 if (ethoc_update_rx_stats(&bd) == 0) { 367 int size = bd.stat >> 16; 368 369 size -= 4; /* strip the CRC */ 370 *packetp = net_rx_packets[i]; 371 return size; 372 } else { 373 return 0; 374 } 375 } 376 377 static int ethoc_is_new_packet_received(struct ethoc *priv) 378 { 379 u32 pending; 380 381 pending = ethoc_read(priv, INT_SOURCE); 382 ethoc_ack_irq(priv, pending); 383 if (pending & INT_MASK_BUSY) 384 debug("%s(): packet dropped\n", __func__); 385 if (pending & INT_MASK_RX) { 386 debug("%s(): rx irq\n", __func__); 387 return 1; 388 } 389 390 return 0; 391 } 392 393 static int ethoc_update_tx_stats(struct ethoc_bd *bd) 394 { 395 if (bd->stat & TX_BD_LC) 396 debug("ETHOC: " "TX: late collision\n"); 397 398 if (bd->stat & TX_BD_RL) 399 debug("ETHOC: " "TX: retransmit limit\n"); 400 401 if (bd->stat & TX_BD_UR) 402 debug("ETHOC: " "TX: underrun\n"); 403 404 if (bd->stat & TX_BD_CS) 405 debug("ETHOC: " "TX: carrier sense lost\n"); 406 407 return 0; 408 } 409 410 static void ethoc_tx(struct ethoc *priv) 411 { 412 u32 entry = priv->dty_tx % priv->num_tx; 413 struct ethoc_bd bd; 414 415 ethoc_read_bd(priv, entry, &bd); 416 if ((bd.stat & TX_BD_READY) == 0) 417 (void)ethoc_update_tx_stats(&bd); 418 } 419 420 static int ethoc_send_common(struct ethoc *priv, void *packet, int length) 421 { 422 struct ethoc_bd bd; 423 u32 entry; 424 u32 pending; 425 int tmo; 426 427 entry = priv->cur_tx % priv->num_tx; 428 ethoc_read_bd(priv, entry, &bd); 429 if (unlikely(length < ETHOC_ZLEN)) 430 bd.stat |= TX_BD_PAD; 431 else 432 bd.stat &= ~TX_BD_PAD; 433 bd.addr = virt_to_phys(packet); 434 435 flush_dcache_range((ulong)packet, (ulong)packet + length); 436 bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK); 437 bd.stat |= TX_BD_LEN(length); 438 ethoc_write_bd(priv, entry, &bd); 439 440 /* start transmit */ 441 bd.stat |= TX_BD_READY; 442 ethoc_write_bd(priv, entry, &bd); 443 444 /* wait for transfer to succeed */ 445 tmo = get_timer(0) + 5 * CONFIG_SYS_HZ; 446 while (1) { 447 pending = ethoc_read(priv, INT_SOURCE); 448 ethoc_ack_irq(priv, pending & ~INT_MASK_RX); 449 if (pending & INT_MASK_BUSY) 450 debug("%s(): packet dropped\n", __func__); 451 452 if (pending & INT_MASK_TX) { 453 ethoc_tx(priv); 454 break; 455 } 456 if (get_timer(0) >= tmo) { 457 debug("%s(): timed out\n", __func__); 458 return -1; 459 } 460 } 461 462 debug("%s(): packet sent\n", __func__); 463 return 0; 464 } 465 466 static int ethoc_free_pkt_common(struct ethoc *priv) 467 { 468 struct ethoc_bd bd; 469 u32 i = priv->cur_rx % priv->num_rx; 470 u32 entry = priv->num_tx + i; 471 472 ethoc_read_bd(priv, entry, &bd); 473 474 /* clear the buffer descriptor so it can be reused */ 475 flush_dcache_range((ulong)net_rx_packets[i], 476 (ulong)net_rx_packets[i] + PKTSIZE_ALIGN); 477 bd.stat &= ~RX_BD_STATS; 478 bd.stat |= RX_BD_EMPTY; 479 ethoc_write_bd(priv, entry, &bd); 480 priv->cur_rx++; 481 482 return 0; 483 } 484 485 #ifdef CONFIG_DM_ETH 486 487 static int ethoc_write_hwaddr(struct udevice *dev) 488 { 489 struct ethoc_eth_pdata *pdata = dev_get_platdata(dev); 490 struct ethoc *priv = dev_get_priv(dev); 491 u8 *mac = pdata->eth_pdata.enetaddr; 492 493 return ethoc_write_hwaddr_common(priv, mac); 494 } 495 496 static int ethoc_send(struct udevice *dev, void *packet, int length) 497 { 498 return ethoc_send_common(dev_get_priv(dev), packet, length); 499 } 500 501 static int ethoc_free_pkt(struct udevice *dev, uchar *packet, int length) 502 { 503 return ethoc_free_pkt_common(dev_get_priv(dev)); 504 } 505 506 static int ethoc_recv(struct udevice *dev, int flags, uchar **packetp) 507 { 508 struct ethoc *priv = dev_get_priv(dev); 509 510 if (flags & ETH_RECV_CHECK_DEVICE) 511 if (!ethoc_is_new_packet_received(priv)) 512 return -EAGAIN; 513 514 return ethoc_rx_common(priv, packetp); 515 } 516 517 static int ethoc_start(struct udevice *dev) 518 { 519 return ethoc_init_common(dev_get_priv(dev)); 520 } 521 522 static void ethoc_stop(struct udevice *dev) 523 { 524 struct ethoc *priv = dev_get_priv(dev); 525 526 ethoc_disable_rx_and_tx(priv); 527 } 528 529 static int ethoc_ofdata_to_platdata(struct udevice *dev) 530 { 531 struct ethoc_eth_pdata *pdata = dev_get_platdata(dev); 532 533 pdata->eth_pdata.iobase = dev_get_addr(dev); 534 return 0; 535 } 536 537 static int ethoc_probe(struct udevice *dev) 538 { 539 struct ethoc_eth_pdata *pdata = dev_get_platdata(dev); 540 struct ethoc *priv = dev_get_priv(dev); 541 542 priv->iobase = ioremap(pdata->eth_pdata.iobase, ETHOC_IOSIZE); 543 return 0; 544 } 545 546 static int ethoc_remove(struct udevice *dev) 547 { 548 struct ethoc *priv = dev_get_priv(dev); 549 550 iounmap(priv->iobase); 551 return 0; 552 } 553 554 static const struct eth_ops ethoc_ops = { 555 .start = ethoc_start, 556 .stop = ethoc_stop, 557 .send = ethoc_send, 558 .recv = ethoc_recv, 559 .free_pkt = ethoc_free_pkt, 560 .write_hwaddr = ethoc_write_hwaddr, 561 }; 562 563 static const struct udevice_id ethoc_ids[] = { 564 { .compatible = "opencores,ethoc" }, 565 { } 566 }; 567 568 U_BOOT_DRIVER(ethoc) = { 569 .name = "ethoc", 570 .id = UCLASS_ETH, 571 .of_match = ethoc_ids, 572 .ofdata_to_platdata = ethoc_ofdata_to_platdata, 573 .probe = ethoc_probe, 574 .remove = ethoc_remove, 575 .ops = ðoc_ops, 576 .priv_auto_alloc_size = sizeof(struct ethoc), 577 .platdata_auto_alloc_size = sizeof(struct ethoc_eth_pdata), 578 }; 579 580 #else 581 582 static int ethoc_init(struct eth_device *dev, bd_t *bd) 583 { 584 struct ethoc *priv = (struct ethoc *)dev->priv; 585 586 return ethoc_init_common(priv); 587 } 588 589 static int ethoc_write_hwaddr(struct eth_device *dev) 590 { 591 struct ethoc *priv = (struct ethoc *)dev->priv; 592 u8 *mac = dev->enetaddr; 593 594 return ethoc_write_hwaddr_common(priv, mac); 595 } 596 597 static int ethoc_send(struct eth_device *dev, void *packet, int length) 598 { 599 return ethoc_send_common(dev->priv, packet, length); 600 } 601 602 static void ethoc_halt(struct eth_device *dev) 603 { 604 ethoc_disable_rx_and_tx(dev->priv); 605 } 606 607 static int ethoc_recv(struct eth_device *dev) 608 { 609 struct ethoc *priv = (struct ethoc *)dev->priv; 610 int count; 611 612 if (!ethoc_is_new_packet_received(priv)) 613 return 0; 614 615 for (count = 0; count < PKTBUFSRX; ++count) { 616 uchar *packetp; 617 int size = ethoc_rx_common(priv, &packetp); 618 619 if (size < 0) 620 break; 621 if (size > 0) 622 net_process_received_packet(packetp, size); 623 ethoc_free_pkt_common(priv); 624 } 625 return 0; 626 } 627 628 int ethoc_initialize(u8 dev_num, int base_addr) 629 { 630 struct ethoc *priv; 631 struct eth_device *dev; 632 633 priv = malloc(sizeof(*priv)); 634 if (!priv) 635 return 0; 636 dev = malloc(sizeof(*dev)); 637 if (!dev) { 638 free(priv); 639 return 0; 640 } 641 642 memset(dev, 0, sizeof(*dev)); 643 dev->priv = priv; 644 dev->iobase = base_addr; 645 dev->init = ethoc_init; 646 dev->halt = ethoc_halt; 647 dev->send = ethoc_send; 648 dev->recv = ethoc_recv; 649 dev->write_hwaddr = ethoc_write_hwaddr; 650 sprintf(dev->name, "%s-%hu", "ETHOC", dev_num); 651 priv->iobase = ioremap(dev->iobase, ETHOC_IOSIZE); 652 653 eth_register(dev); 654 return 1; 655 } 656 657 #endif 658