1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2002 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 */ 6 7 #include <common.h> 8 #include <malloc.h> 9 #include <net.h> 10 #include <netdev.h> 11 #include <asm/io.h> 12 #include <pci.h> 13 #include <miiphy.h> 14 15 #undef DEBUG 16 17 /* Ethernet chip registers. 18 */ 19 #define SCBStatus 0 /* Rx/Command Unit Status *Word* */ 20 #define SCBIntAckByte 1 /* Rx/Command Unit STAT/ACK byte */ 21 #define SCBCmd 2 /* Rx/Command Unit Command *Word* */ 22 #define SCBIntrCtlByte 3 /* Rx/Command Unit Intr.Control Byte */ 23 #define SCBPointer 4 /* General purpose pointer. */ 24 #define SCBPort 8 /* Misc. commands and operands. */ 25 #define SCBflash 12 /* Flash memory control. */ 26 #define SCBeeprom 14 /* EEPROM memory control. */ 27 #define SCBCtrlMDI 16 /* MDI interface control. */ 28 #define SCBEarlyRx 20 /* Early receive byte count. */ 29 #define SCBGenControl 28 /* 82559 General Control Register */ 30 #define SCBGenStatus 29 /* 82559 General Status register */ 31 32 /* 82559 SCB status word defnitions 33 */ 34 #define SCB_STATUS_CX 0x8000 /* CU finished command (transmit) */ 35 #define SCB_STATUS_FR 0x4000 /* frame received */ 36 #define SCB_STATUS_CNA 0x2000 /* CU left active state */ 37 #define SCB_STATUS_RNR 0x1000 /* receiver left ready state */ 38 #define SCB_STATUS_MDI 0x0800 /* MDI read/write cycle done */ 39 #define SCB_STATUS_SWI 0x0400 /* software generated interrupt */ 40 #define SCB_STATUS_FCP 0x0100 /* flow control pause interrupt */ 41 42 #define SCB_INTACK_MASK 0xFD00 /* all the above */ 43 44 #define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA) 45 #define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR) 46 47 /* System control block commands 48 */ 49 /* CU Commands */ 50 #define CU_NOP 0x0000 51 #define CU_START 0x0010 52 #define CU_RESUME 0x0020 53 #define CU_STATSADDR 0x0040 /* Load Dump Statistics ctrs addr */ 54 #define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */ 55 #define CU_ADDR_LOAD 0x0060 /* Base address to add to CU commands */ 56 #define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */ 57 58 /* RUC Commands */ 59 #define RUC_NOP 0x0000 60 #define RUC_START 0x0001 61 #define RUC_RESUME 0x0002 62 #define RUC_ABORT 0x0004 63 #define RUC_ADDR_LOAD 0x0006 /* (seems not to clear on acceptance) */ 64 #define RUC_RESUMENR 0x0007 65 66 #define CU_CMD_MASK 0x00f0 67 #define RU_CMD_MASK 0x0007 68 69 #define SCB_M 0x0100 /* 0 = enable interrupt, 1 = disable */ 70 #define SCB_SWI 0x0200 /* 1 - cause device to interrupt */ 71 72 #define CU_STATUS_MASK 0x00C0 73 #define RU_STATUS_MASK 0x003C 74 75 #define RU_STATUS_IDLE (0<<2) 76 #define RU_STATUS_SUS (1<<2) 77 #define RU_STATUS_NORES (2<<2) 78 #define RU_STATUS_READY (4<<2) 79 #define RU_STATUS_NO_RBDS_SUS ((1<<2)|(8<<2)) 80 #define RU_STATUS_NO_RBDS_NORES ((2<<2)|(8<<2)) 81 #define RU_STATUS_NO_RBDS_READY ((4<<2)|(8<<2)) 82 83 /* 82559 Port interface commands. 84 */ 85 #define I82559_RESET 0x00000000 /* Software reset */ 86 #define I82559_SELFTEST 0x00000001 /* 82559 Selftest command */ 87 #define I82559_SELECTIVE_RESET 0x00000002 88 #define I82559_DUMP 0x00000003 89 #define I82559_DUMP_WAKEUP 0x00000007 90 91 /* 82559 Eeprom interface. 92 */ 93 #define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */ 94 #define EE_CS 0x02 /* EEPROM chip select. */ 95 #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ 96 #define EE_WRITE_0 0x01 97 #define EE_WRITE_1 0x05 98 #define EE_DATA_READ 0x08 /* EEPROM chip data out. */ 99 #define EE_ENB (0x4800 | EE_CS) 100 #define EE_CMD_BITS 3 101 #define EE_DATA_BITS 16 102 103 /* The EEPROM commands include the alway-set leading bit. 104 */ 105 #define EE_EWENB_CMD (4 << addr_len) 106 #define EE_WRITE_CMD (5 << addr_len) 107 #define EE_READ_CMD (6 << addr_len) 108 #define EE_ERASE_CMD (7 << addr_len) 109 110 /* Receive frame descriptors. 111 */ 112 struct RxFD { 113 volatile u16 status; 114 volatile u16 control; 115 volatile u32 link; /* struct RxFD * */ 116 volatile u32 rx_buf_addr; /* void * */ 117 volatile u32 count; 118 119 volatile u8 data[PKTSIZE_ALIGN]; 120 }; 121 122 #define RFD_STATUS_C 0x8000 /* completion of received frame */ 123 #define RFD_STATUS_OK 0x2000 /* frame received with no errors */ 124 125 #define RFD_CONTROL_EL 0x8000 /* 1=last RFD in RFA */ 126 #define RFD_CONTROL_S 0x4000 /* 1=suspend RU after receiving frame */ 127 #define RFD_CONTROL_H 0x0010 /* 1=RFD is a header RFD */ 128 #define RFD_CONTROL_SF 0x0008 /* 0=simplified, 1=flexible mode */ 129 130 #define RFD_COUNT_MASK 0x3fff 131 #define RFD_COUNT_F 0x4000 132 #define RFD_COUNT_EOF 0x8000 133 134 #define RFD_RX_CRC 0x0800 /* crc error */ 135 #define RFD_RX_ALIGNMENT 0x0400 /* alignment error */ 136 #define RFD_RX_RESOURCE 0x0200 /* out of space, no resources */ 137 #define RFD_RX_DMA_OVER 0x0100 /* DMA overrun */ 138 #define RFD_RX_SHORT 0x0080 /* short frame error */ 139 #define RFD_RX_LENGTH 0x0020 140 #define RFD_RX_ERROR 0x0010 /* receive error */ 141 #define RFD_RX_NO_ADR_MATCH 0x0004 /* no address match */ 142 #define RFD_RX_IA_MATCH 0x0002 /* individual address does not match */ 143 #define RFD_RX_TCO 0x0001 /* TCO indication */ 144 145 /* Transmit frame descriptors 146 */ 147 struct TxFD { /* Transmit frame descriptor set. */ 148 volatile u16 status; 149 volatile u16 command; 150 volatile u32 link; /* void * */ 151 volatile u32 tx_desc_addr; /* Always points to the tx_buf_addr element. */ 152 volatile s32 count; 153 154 volatile u32 tx_buf_addr0; /* void *, frame to be transmitted. */ 155 volatile s32 tx_buf_size0; /* Length of Tx frame. */ 156 volatile u32 tx_buf_addr1; /* void *, frame to be transmitted. */ 157 volatile s32 tx_buf_size1; /* Length of Tx frame. */ 158 }; 159 160 #define TxCB_CMD_TRANSMIT 0x0004 /* transmit command */ 161 #define TxCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */ 162 #define TxCB_CMD_NC 0x0010 /* 0=CRC insert by controller */ 163 #define TxCB_CMD_I 0x2000 /* generate interrupt on completion */ 164 #define TxCB_CMD_S 0x4000 /* suspend on completion */ 165 #define TxCB_CMD_EL 0x8000 /* last command block in CBL */ 166 167 #define TxCB_COUNT_MASK 0x3fff 168 #define TxCB_COUNT_EOF 0x8000 169 170 /* The Speedo3 Rx and Tx frame/buffer descriptors. 171 */ 172 struct descriptor { /* A generic descriptor. */ 173 volatile u16 status; 174 volatile u16 command; 175 volatile u32 link; /* struct descriptor * */ 176 177 unsigned char params[0]; 178 }; 179 180 #define CONFIG_SYS_CMD_EL 0x8000 181 #define CONFIG_SYS_CMD_SUSPEND 0x4000 182 #define CONFIG_SYS_CMD_INT 0x2000 183 #define CONFIG_SYS_CMD_IAS 0x0001 /* individual address setup */ 184 #define CONFIG_SYS_CMD_CONFIGURE 0x0002 /* configure */ 185 186 #define CONFIG_SYS_STATUS_C 0x8000 187 #define CONFIG_SYS_STATUS_OK 0x2000 188 189 /* Misc. 190 */ 191 #define NUM_RX_DESC PKTBUFSRX 192 #define NUM_TX_DESC 1 /* Number of TX descriptors */ 193 194 #define TOUT_LOOP 1000000 195 196 static struct RxFD rx_ring[NUM_RX_DESC]; /* RX descriptor ring */ 197 static struct TxFD tx_ring[NUM_TX_DESC]; /* TX descriptor ring */ 198 static int rx_next; /* RX descriptor ring pointer */ 199 static int tx_next; /* TX descriptor ring pointer */ 200 static int tx_threshold; 201 202 /* 203 * The parameters for a CmdConfigure operation. 204 * There are so many options that it would be difficult to document 205 * each bit. We mostly use the default or recommended settings. 206 */ 207 static const char i82558_config_cmd[] = { 208 22, 0x08, 0, 1, 0, 0, 0x22, 0x03, 1, /* 1=Use MII 0=Use AUI */ 209 0, 0x2E, 0, 0x60, 0x08, 0x88, 210 0x68, 0, 0x40, 0xf2, 0x84, /* Disable FC */ 211 0x31, 0x05, 212 }; 213 214 static void init_rx_ring (struct eth_device *dev); 215 static void purge_tx_ring (struct eth_device *dev); 216 217 static void read_hw_addr (struct eth_device *dev, bd_t * bis); 218 219 static int eepro100_init (struct eth_device *dev, bd_t * bis); 220 static int eepro100_send(struct eth_device *dev, void *packet, int length); 221 static int eepro100_recv (struct eth_device *dev); 222 static void eepro100_halt (struct eth_device *dev); 223 224 #if defined(CONFIG_E500) 225 #define bus_to_phys(a) (a) 226 #define phys_to_bus(a) (a) 227 #else 228 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a) 229 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) 230 #endif 231 232 static inline int INW (struct eth_device *dev, u_long addr) 233 { 234 return le16_to_cpu(*(volatile u16 *)(addr + (u_long)dev->iobase)); 235 } 236 237 static inline void OUTW (struct eth_device *dev, int command, u_long addr) 238 { 239 *(volatile u16 *)((addr + (u_long)dev->iobase)) = cpu_to_le16(command); 240 } 241 242 static inline void OUTL (struct eth_device *dev, int command, u_long addr) 243 { 244 *(volatile u32 *)((addr + (u_long)dev->iobase)) = cpu_to_le32(command); 245 } 246 247 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 248 static inline int INL (struct eth_device *dev, u_long addr) 249 { 250 return le32_to_cpu(*(volatile u32 *)(addr + (u_long)dev->iobase)); 251 } 252 253 static int get_phyreg (struct eth_device *dev, unsigned char addr, 254 unsigned char reg, unsigned short *value) 255 { 256 int cmd; 257 int timeout = 50; 258 259 /* read requested data */ 260 cmd = (2 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16); 261 OUTL (dev, cmd, SCBCtrlMDI); 262 263 do { 264 udelay(1000); 265 cmd = INL (dev, SCBCtrlMDI); 266 } while (!(cmd & (1 << 28)) && (--timeout)); 267 268 if (timeout == 0) 269 return -1; 270 271 *value = (unsigned short) (cmd & 0xffff); 272 273 return 0; 274 } 275 276 static int set_phyreg (struct eth_device *dev, unsigned char addr, 277 unsigned char reg, unsigned short value) 278 { 279 int cmd; 280 int timeout = 50; 281 282 /* write requested data */ 283 cmd = (1 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16); 284 OUTL (dev, cmd | value, SCBCtrlMDI); 285 286 while (!(INL (dev, SCBCtrlMDI) & (1 << 28)) && (--timeout)) 287 udelay(1000); 288 289 if (timeout == 0) 290 return -1; 291 292 return 0; 293 } 294 295 /* Check if given phyaddr is valid, i.e. there is a PHY connected. 296 * Do this by checking model value field from ID2 register. 297 */ 298 static struct eth_device* verify_phyaddr (const char *devname, 299 unsigned char addr) 300 { 301 struct eth_device *dev; 302 unsigned short value; 303 unsigned char model; 304 305 dev = eth_get_dev_by_name(devname); 306 if (dev == NULL) { 307 printf("%s: no such device\n", devname); 308 return NULL; 309 } 310 311 /* read id2 register */ 312 if (get_phyreg(dev, addr, MII_PHYSID2, &value) != 0) { 313 printf("%s: mii read timeout!\n", devname); 314 return NULL; 315 } 316 317 /* get model */ 318 model = (unsigned char)((value >> 4) & 0x003f); 319 320 if (model == 0) { 321 printf("%s: no PHY at address %d\n", devname, addr); 322 return NULL; 323 } 324 325 return dev; 326 } 327 328 static int eepro100_miiphy_read(struct mii_dev *bus, int addr, int devad, 329 int reg) 330 { 331 unsigned short value = 0; 332 struct eth_device *dev; 333 334 dev = verify_phyaddr(bus->name, addr); 335 if (dev == NULL) 336 return -1; 337 338 if (get_phyreg(dev, addr, reg, &value) != 0) { 339 printf("%s: mii read timeout!\n", bus->name); 340 return -1; 341 } 342 343 return value; 344 } 345 346 static int eepro100_miiphy_write(struct mii_dev *bus, int addr, int devad, 347 int reg, u16 value) 348 { 349 struct eth_device *dev; 350 351 dev = verify_phyaddr(bus->name, addr); 352 if (dev == NULL) 353 return -1; 354 355 if (set_phyreg(dev, addr, reg, value) != 0) { 356 printf("%s: mii write timeout!\n", bus->name); 357 return -1; 358 } 359 360 return 0; 361 } 362 363 #endif 364 365 /* Wait for the chip get the command. 366 */ 367 static int wait_for_eepro100 (struct eth_device *dev) 368 { 369 int i; 370 371 for (i = 0; INW (dev, SCBCmd) & (CU_CMD_MASK | RU_CMD_MASK); i++) { 372 if (i >= TOUT_LOOP) { 373 return 0; 374 } 375 } 376 377 return 1; 378 } 379 380 static struct pci_device_id supported[] = { 381 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557}, 382 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559}, 383 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER}, 384 {} 385 }; 386 387 int eepro100_initialize (bd_t * bis) 388 { 389 pci_dev_t devno; 390 int card_number = 0; 391 struct eth_device *dev; 392 u32 iobase, status; 393 int idx = 0; 394 395 while (1) { 396 /* Find PCI device 397 */ 398 if ((devno = pci_find_devices (supported, idx++)) < 0) { 399 break; 400 } 401 402 pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase); 403 iobase &= ~0xf; 404 405 #ifdef DEBUG 406 printf ("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n", 407 iobase); 408 #endif 409 410 pci_write_config_dword (devno, 411 PCI_COMMAND, 412 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 413 414 /* Check if I/O accesses and Bus Mastering are enabled. 415 */ 416 pci_read_config_dword (devno, PCI_COMMAND, &status); 417 if (!(status & PCI_COMMAND_MEMORY)) { 418 printf ("Error: Can not enable MEM access.\n"); 419 continue; 420 } 421 422 if (!(status & PCI_COMMAND_MASTER)) { 423 printf ("Error: Can not enable Bus Mastering.\n"); 424 continue; 425 } 426 427 dev = (struct eth_device *) malloc (sizeof *dev); 428 if (!dev) { 429 printf("eepro100: Can not allocate memory\n"); 430 break; 431 } 432 memset(dev, 0, sizeof(*dev)); 433 434 sprintf (dev->name, "i82559#%d", card_number); 435 dev->priv = (void *) devno; /* this have to come before bus_to_phys() */ 436 dev->iobase = bus_to_phys (iobase); 437 dev->init = eepro100_init; 438 dev->halt = eepro100_halt; 439 dev->send = eepro100_send; 440 dev->recv = eepro100_recv; 441 442 eth_register (dev); 443 444 #if defined (CONFIG_MII) || defined(CONFIG_CMD_MII) 445 /* register mii command access routines */ 446 int retval; 447 struct mii_dev *mdiodev = mdio_alloc(); 448 if (!mdiodev) 449 return -ENOMEM; 450 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); 451 mdiodev->read = eepro100_miiphy_read; 452 mdiodev->write = eepro100_miiphy_write; 453 454 retval = mdio_register(mdiodev); 455 if (retval < 0) 456 return retval; 457 #endif 458 459 card_number++; 460 461 /* Set the latency timer for value. 462 */ 463 pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20); 464 465 udelay (10 * 1000); 466 467 read_hw_addr (dev, bis); 468 } 469 470 return card_number; 471 } 472 473 474 static int eepro100_init (struct eth_device *dev, bd_t * bis) 475 { 476 int i, status = -1; 477 int tx_cur; 478 struct descriptor *ias_cmd, *cfg_cmd; 479 480 /* Reset the ethernet controller 481 */ 482 OUTL (dev, I82559_SELECTIVE_RESET, SCBPort); 483 udelay (20); 484 485 OUTL (dev, I82559_RESET, SCBPort); 486 udelay (20); 487 488 if (!wait_for_eepro100 (dev)) { 489 printf ("Error: Can not reset ethernet controller.\n"); 490 goto Done; 491 } 492 OUTL (dev, 0, SCBPointer); 493 OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd); 494 495 if (!wait_for_eepro100 (dev)) { 496 printf ("Error: Can not reset ethernet controller.\n"); 497 goto Done; 498 } 499 OUTL (dev, 0, SCBPointer); 500 OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd); 501 502 /* Initialize Rx and Tx rings. 503 */ 504 init_rx_ring (dev); 505 purge_tx_ring (dev); 506 507 /* Tell the adapter where the RX ring is located. 508 */ 509 if (!wait_for_eepro100 (dev)) { 510 printf ("Error: Can not reset ethernet controller.\n"); 511 goto Done; 512 } 513 514 OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer); 515 OUTW (dev, SCB_M | RUC_START, SCBCmd); 516 517 /* Send the Configure frame */ 518 tx_cur = tx_next; 519 tx_next = ((tx_next + 1) % NUM_TX_DESC); 520 521 cfg_cmd = (struct descriptor *) &tx_ring[tx_cur]; 522 cfg_cmd->command = cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND | CONFIG_SYS_CMD_CONFIGURE)); 523 cfg_cmd->status = 0; 524 cfg_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next])); 525 526 memcpy (cfg_cmd->params, i82558_config_cmd, 527 sizeof (i82558_config_cmd)); 528 529 if (!wait_for_eepro100 (dev)) { 530 printf ("Error---CONFIG_SYS_CMD_CONFIGURE: Can not reset ethernet controller.\n"); 531 goto Done; 532 } 533 534 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer); 535 OUTW (dev, SCB_M | CU_START, SCBCmd); 536 537 for (i = 0; 538 !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C); 539 i++) { 540 if (i >= TOUT_LOOP) { 541 printf ("%s: Tx error buffer not ready\n", dev->name); 542 goto Done; 543 } 544 } 545 546 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) { 547 printf ("TX error status = 0x%08X\n", 548 le16_to_cpu (tx_ring[tx_cur].status)); 549 goto Done; 550 } 551 552 /* Send the Individual Address Setup frame 553 */ 554 tx_cur = tx_next; 555 tx_next = ((tx_next + 1) % NUM_TX_DESC); 556 557 ias_cmd = (struct descriptor *) &tx_ring[tx_cur]; 558 ias_cmd->command = cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND | CONFIG_SYS_CMD_IAS)); 559 ias_cmd->status = 0; 560 ias_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next])); 561 562 memcpy (ias_cmd->params, dev->enetaddr, 6); 563 564 /* Tell the adapter where the TX ring is located. 565 */ 566 if (!wait_for_eepro100 (dev)) { 567 printf ("Error: Can not reset ethernet controller.\n"); 568 goto Done; 569 } 570 571 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer); 572 OUTW (dev, SCB_M | CU_START, SCBCmd); 573 574 for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C); 575 i++) { 576 if (i >= TOUT_LOOP) { 577 printf ("%s: Tx error buffer not ready\n", 578 dev->name); 579 goto Done; 580 } 581 } 582 583 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) { 584 printf ("TX error status = 0x%08X\n", 585 le16_to_cpu (tx_ring[tx_cur].status)); 586 goto Done; 587 } 588 589 status = 0; 590 591 Done: 592 return status; 593 } 594 595 static int eepro100_send(struct eth_device *dev, void *packet, int length) 596 { 597 int i, status = -1; 598 int tx_cur; 599 600 if (length <= 0) { 601 printf ("%s: bad packet size: %d\n", dev->name, length); 602 goto Done; 603 } 604 605 tx_cur = tx_next; 606 tx_next = (tx_next + 1) % NUM_TX_DESC; 607 608 tx_ring[tx_cur].command = cpu_to_le16 ( TxCB_CMD_TRANSMIT | 609 TxCB_CMD_SF | 610 TxCB_CMD_S | 611 TxCB_CMD_EL ); 612 tx_ring[tx_cur].status = 0; 613 tx_ring[tx_cur].count = cpu_to_le32 (tx_threshold); 614 tx_ring[tx_cur].link = 615 cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next])); 616 tx_ring[tx_cur].tx_desc_addr = 617 cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_cur].tx_buf_addr0)); 618 tx_ring[tx_cur].tx_buf_addr0 = 619 cpu_to_le32 (phys_to_bus ((u_long) packet)); 620 tx_ring[tx_cur].tx_buf_size0 = cpu_to_le32 (length); 621 622 if (!wait_for_eepro100 (dev)) { 623 printf ("%s: Tx error ethernet controller not ready.\n", 624 dev->name); 625 goto Done; 626 } 627 628 /* Send the packet. 629 */ 630 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer); 631 OUTW (dev, SCB_M | CU_START, SCBCmd); 632 633 for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C); 634 i++) { 635 if (i >= TOUT_LOOP) { 636 printf ("%s: Tx error buffer not ready\n", dev->name); 637 goto Done; 638 } 639 } 640 641 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) { 642 printf ("TX error status = 0x%08X\n", 643 le16_to_cpu (tx_ring[tx_cur].status)); 644 goto Done; 645 } 646 647 status = length; 648 649 Done: 650 return status; 651 } 652 653 static int eepro100_recv (struct eth_device *dev) 654 { 655 u16 status, stat; 656 int rx_prev, length = 0; 657 658 stat = INW (dev, SCBStatus); 659 OUTW (dev, stat & SCB_STATUS_RNR, SCBStatus); 660 661 for (;;) { 662 status = le16_to_cpu (rx_ring[rx_next].status); 663 664 if (!(status & RFD_STATUS_C)) { 665 break; 666 } 667 668 /* Valid frame status. 669 */ 670 if ((status & RFD_STATUS_OK)) { 671 /* A valid frame received. 672 */ 673 length = le32_to_cpu (rx_ring[rx_next].count) & 0x3fff; 674 675 /* Pass the packet up to the protocol 676 * layers. 677 */ 678 net_process_received_packet((u8 *)rx_ring[rx_next].data, 679 length); 680 } else { 681 /* There was an error. 682 */ 683 printf ("RX error status = 0x%08X\n", status); 684 } 685 686 rx_ring[rx_next].control = cpu_to_le16 (RFD_CONTROL_S); 687 rx_ring[rx_next].status = 0; 688 rx_ring[rx_next].count = cpu_to_le32 (PKTSIZE_ALIGN << 16); 689 690 rx_prev = (rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC; 691 rx_ring[rx_prev].control = 0; 692 693 /* Update entry information. 694 */ 695 rx_next = (rx_next + 1) % NUM_RX_DESC; 696 } 697 698 if (stat & SCB_STATUS_RNR) { 699 700 printf ("%s: Receiver is not ready, restart it !\n", dev->name); 701 702 /* Reinitialize Rx ring. 703 */ 704 init_rx_ring (dev); 705 706 if (!wait_for_eepro100 (dev)) { 707 printf ("Error: Can not restart ethernet controller.\n"); 708 goto Done; 709 } 710 711 OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer); 712 OUTW (dev, SCB_M | RUC_START, SCBCmd); 713 } 714 715 Done: 716 return length; 717 } 718 719 static void eepro100_halt (struct eth_device *dev) 720 { 721 /* Reset the ethernet controller 722 */ 723 OUTL (dev, I82559_SELECTIVE_RESET, SCBPort); 724 udelay (20); 725 726 OUTL (dev, I82559_RESET, SCBPort); 727 udelay (20); 728 729 if (!wait_for_eepro100 (dev)) { 730 printf ("Error: Can not reset ethernet controller.\n"); 731 goto Done; 732 } 733 OUTL (dev, 0, SCBPointer); 734 OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd); 735 736 if (!wait_for_eepro100 (dev)) { 737 printf ("Error: Can not reset ethernet controller.\n"); 738 goto Done; 739 } 740 OUTL (dev, 0, SCBPointer); 741 OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd); 742 743 Done: 744 return; 745 } 746 747 /* SROM Read. 748 */ 749 static int read_eeprom (struct eth_device *dev, int location, int addr_len) 750 { 751 unsigned short retval = 0; 752 int read_cmd = location | EE_READ_CMD; 753 int i; 754 755 OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom); 756 OUTW (dev, EE_ENB, SCBeeprom); 757 758 /* Shift the read command bits out. */ 759 for (i = 12; i >= 0; i--) { 760 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 761 762 OUTW (dev, EE_ENB | dataval, SCBeeprom); 763 udelay (1); 764 OUTW (dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); 765 udelay (1); 766 } 767 OUTW (dev, EE_ENB, SCBeeprom); 768 769 for (i = 15; i >= 0; i--) { 770 OUTW (dev, EE_ENB | EE_SHIFT_CLK, SCBeeprom); 771 udelay (1); 772 retval = (retval << 1) | 773 ((INW (dev, SCBeeprom) & EE_DATA_READ) ? 1 : 0); 774 OUTW (dev, EE_ENB, SCBeeprom); 775 udelay (1); 776 } 777 778 /* Terminate the EEPROM access. */ 779 OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom); 780 return retval; 781 } 782 783 #ifdef CONFIG_EEPRO100_SROM_WRITE 784 int eepro100_write_eeprom (struct eth_device* dev, int location, int addr_len, unsigned short data) 785 { 786 unsigned short dataval; 787 int enable_cmd = 0x3f | EE_EWENB_CMD; 788 int write_cmd = location | EE_WRITE_CMD; 789 int i; 790 unsigned long datalong, tmplong; 791 792 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); 793 udelay(1); 794 OUTW(dev, EE_ENB, SCBeeprom); 795 796 /* Shift the enable command bits out. */ 797 for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--) 798 { 799 dataval = (enable_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 800 OUTW(dev, EE_ENB | dataval, SCBeeprom); 801 udelay(1); 802 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); 803 udelay(1); 804 } 805 806 OUTW(dev, EE_ENB, SCBeeprom); 807 udelay(1); 808 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); 809 udelay(1); 810 OUTW(dev, EE_ENB, SCBeeprom); 811 812 813 /* Shift the write command bits out. */ 814 for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--) 815 { 816 dataval = (write_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 817 OUTW(dev, EE_ENB | dataval, SCBeeprom); 818 udelay(1); 819 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); 820 udelay(1); 821 } 822 823 /* Write the data */ 824 datalong= (unsigned long) ((((data) & 0x00ff) << 8) | ( (data) >> 8)); 825 826 for (i = 0; i< EE_DATA_BITS; i++) 827 { 828 /* Extract and move data bit to bit DI */ 829 dataval = ((datalong & 0x8000)>>13) ? EE_DATA_WRITE : 0; 830 831 OUTW(dev, EE_ENB | dataval, SCBeeprom); 832 udelay(1); 833 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); 834 udelay(1); 835 OUTW(dev, EE_ENB | dataval, SCBeeprom); 836 udelay(1); 837 838 datalong = datalong << 1; /* Adjust significant data bit*/ 839 } 840 841 /* Finish up command (toggle CS) */ 842 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); 843 udelay(1); /* delay for more than 250 ns */ 844 OUTW(dev, EE_ENB, SCBeeprom); 845 846 /* Wait for programming ready (D0 = 1) */ 847 tmplong = 10; 848 do 849 { 850 dataval = INW(dev, SCBeeprom); 851 if (dataval & EE_DATA_READ) 852 break; 853 udelay(10000); 854 } 855 while (-- tmplong); 856 857 if (tmplong == 0) 858 { 859 printf ("Write i82559 eeprom timed out (100 ms waiting for data ready.\n"); 860 return -1; 861 } 862 863 /* Terminate the EEPROM access. */ 864 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); 865 866 return 0; 867 } 868 #endif 869 870 static void init_rx_ring (struct eth_device *dev) 871 { 872 int i; 873 874 for (i = 0; i < NUM_RX_DESC; i++) { 875 rx_ring[i].status = 0; 876 rx_ring[i].control = 877 (i == NUM_RX_DESC - 1) ? cpu_to_le16 (RFD_CONTROL_S) : 0; 878 rx_ring[i].link = 879 cpu_to_le32 (phys_to_bus 880 ((u32) & rx_ring[(i + 1) % NUM_RX_DESC])); 881 rx_ring[i].rx_buf_addr = 0xffffffff; 882 rx_ring[i].count = cpu_to_le32 (PKTSIZE_ALIGN << 16); 883 } 884 885 rx_next = 0; 886 } 887 888 static void purge_tx_ring (struct eth_device *dev) 889 { 890 int i; 891 892 tx_next = 0; 893 tx_threshold = 0x01208000; 894 895 for (i = 0; i < NUM_TX_DESC; i++) { 896 tx_ring[i].status = 0; 897 tx_ring[i].command = 0; 898 tx_ring[i].link = 0; 899 tx_ring[i].tx_desc_addr = 0; 900 tx_ring[i].count = 0; 901 902 tx_ring[i].tx_buf_addr0 = 0; 903 tx_ring[i].tx_buf_size0 = 0; 904 tx_ring[i].tx_buf_addr1 = 0; 905 tx_ring[i].tx_buf_size1 = 0; 906 } 907 } 908 909 static void read_hw_addr (struct eth_device *dev, bd_t * bis) 910 { 911 u16 sum = 0; 912 int i, j; 913 int addr_len = read_eeprom (dev, 0, 6) == 0xffff ? 8 : 6; 914 915 for (j = 0, i = 0; i < 0x40; i++) { 916 u16 value = read_eeprom (dev, i, addr_len); 917 918 sum += value; 919 if (i < 3) { 920 dev->enetaddr[j++] = value; 921 dev->enetaddr[j++] = value >> 8; 922 } 923 } 924 925 if (sum != 0xBABA) { 926 memset (dev->enetaddr, 0, ETH_ALEN); 927 #ifdef DEBUG 928 printf ("%s: Invalid EEPROM checksum %#4.4x, " 929 "check settings before activating this device!\n", 930 dev->name, sum); 931 #endif 932 } 933 } 934