1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2002 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 */ 6 7 #include <common.h> 8 #include <malloc.h> 9 #include <net.h> 10 #include <netdev.h> 11 #include <asm/io.h> 12 #include <pci.h> 13 #include <miiphy.h> 14 15 #undef DEBUG 16 17 /* Ethernet chip registers. 18 */ 19 #define SCBStatus 0 /* Rx/Command Unit Status *Word* */ 20 #define SCBIntAckByte 1 /* Rx/Command Unit STAT/ACK byte */ 21 #define SCBCmd 2 /* Rx/Command Unit Command *Word* */ 22 #define SCBIntrCtlByte 3 /* Rx/Command Unit Intr.Control Byte */ 23 #define SCBPointer 4 /* General purpose pointer. */ 24 #define SCBPort 8 /* Misc. commands and operands. */ 25 #define SCBflash 12 /* Flash memory control. */ 26 #define SCBeeprom 14 /* EEPROM memory control. */ 27 #define SCBCtrlMDI 16 /* MDI interface control. */ 28 #define SCBEarlyRx 20 /* Early receive byte count. */ 29 #define SCBGenControl 28 /* 82559 General Control Register */ 30 #define SCBGenStatus 29 /* 82559 General Status register */ 31 32 /* 82559 SCB status word defnitions 33 */ 34 #define SCB_STATUS_CX 0x8000 /* CU finished command (transmit) */ 35 #define SCB_STATUS_FR 0x4000 /* frame received */ 36 #define SCB_STATUS_CNA 0x2000 /* CU left active state */ 37 #define SCB_STATUS_RNR 0x1000 /* receiver left ready state */ 38 #define SCB_STATUS_MDI 0x0800 /* MDI read/write cycle done */ 39 #define SCB_STATUS_SWI 0x0400 /* software generated interrupt */ 40 #define SCB_STATUS_FCP 0x0100 /* flow control pause interrupt */ 41 42 #define SCB_INTACK_MASK 0xFD00 /* all the above */ 43 44 #define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA) 45 #define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR) 46 47 /* System control block commands 48 */ 49 /* CU Commands */ 50 #define CU_NOP 0x0000 51 #define CU_START 0x0010 52 #define CU_RESUME 0x0020 53 #define CU_STATSADDR 0x0040 /* Load Dump Statistics ctrs addr */ 54 #define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */ 55 #define CU_ADDR_LOAD 0x0060 /* Base address to add to CU commands */ 56 #define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */ 57 58 /* RUC Commands */ 59 #define RUC_NOP 0x0000 60 #define RUC_START 0x0001 61 #define RUC_RESUME 0x0002 62 #define RUC_ABORT 0x0004 63 #define RUC_ADDR_LOAD 0x0006 /* (seems not to clear on acceptance) */ 64 #define RUC_RESUMENR 0x0007 65 66 #define CU_CMD_MASK 0x00f0 67 #define RU_CMD_MASK 0x0007 68 69 #define SCB_M 0x0100 /* 0 = enable interrupt, 1 = disable */ 70 #define SCB_SWI 0x0200 /* 1 - cause device to interrupt */ 71 72 #define CU_STATUS_MASK 0x00C0 73 #define RU_STATUS_MASK 0x003C 74 75 #define RU_STATUS_IDLE (0<<2) 76 #define RU_STATUS_SUS (1<<2) 77 #define RU_STATUS_NORES (2<<2) 78 #define RU_STATUS_READY (4<<2) 79 #define RU_STATUS_NO_RBDS_SUS ((1<<2)|(8<<2)) 80 #define RU_STATUS_NO_RBDS_NORES ((2<<2)|(8<<2)) 81 #define RU_STATUS_NO_RBDS_READY ((4<<2)|(8<<2)) 82 83 /* 82559 Port interface commands. 84 */ 85 #define I82559_RESET 0x00000000 /* Software reset */ 86 #define I82559_SELFTEST 0x00000001 /* 82559 Selftest command */ 87 #define I82559_SELECTIVE_RESET 0x00000002 88 #define I82559_DUMP 0x00000003 89 #define I82559_DUMP_WAKEUP 0x00000007 90 91 /* 82559 Eeprom interface. 92 */ 93 #define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */ 94 #define EE_CS 0x02 /* EEPROM chip select. */ 95 #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ 96 #define EE_WRITE_0 0x01 97 #define EE_WRITE_1 0x05 98 #define EE_DATA_READ 0x08 /* EEPROM chip data out. */ 99 #define EE_ENB (0x4800 | EE_CS) 100 #define EE_CMD_BITS 3 101 #define EE_DATA_BITS 16 102 103 /* The EEPROM commands include the alway-set leading bit. 104 */ 105 #define EE_EWENB_CMD (4 << addr_len) 106 #define EE_WRITE_CMD (5 << addr_len) 107 #define EE_READ_CMD (6 << addr_len) 108 #define EE_ERASE_CMD (7 << addr_len) 109 110 /* Receive frame descriptors. 111 */ 112 struct RxFD { 113 volatile u16 status; 114 volatile u16 control; 115 volatile u32 link; /* struct RxFD * */ 116 volatile u32 rx_buf_addr; /* void * */ 117 volatile u32 count; 118 119 volatile u8 data[PKTSIZE_ALIGN]; 120 }; 121 122 #define RFD_STATUS_C 0x8000 /* completion of received frame */ 123 #define RFD_STATUS_OK 0x2000 /* frame received with no errors */ 124 125 #define RFD_CONTROL_EL 0x8000 /* 1=last RFD in RFA */ 126 #define RFD_CONTROL_S 0x4000 /* 1=suspend RU after receiving frame */ 127 #define RFD_CONTROL_H 0x0010 /* 1=RFD is a header RFD */ 128 #define RFD_CONTROL_SF 0x0008 /* 0=simplified, 1=flexible mode */ 129 130 #define RFD_COUNT_MASK 0x3fff 131 #define RFD_COUNT_F 0x4000 132 #define RFD_COUNT_EOF 0x8000 133 134 #define RFD_RX_CRC 0x0800 /* crc error */ 135 #define RFD_RX_ALIGNMENT 0x0400 /* alignment error */ 136 #define RFD_RX_RESOURCE 0x0200 /* out of space, no resources */ 137 #define RFD_RX_DMA_OVER 0x0100 /* DMA overrun */ 138 #define RFD_RX_SHORT 0x0080 /* short frame error */ 139 #define RFD_RX_LENGTH 0x0020 140 #define RFD_RX_ERROR 0x0010 /* receive error */ 141 #define RFD_RX_NO_ADR_MATCH 0x0004 /* no address match */ 142 #define RFD_RX_IA_MATCH 0x0002 /* individual address does not match */ 143 #define RFD_RX_TCO 0x0001 /* TCO indication */ 144 145 /* Transmit frame descriptors 146 */ 147 struct TxFD { /* Transmit frame descriptor set. */ 148 volatile u16 status; 149 volatile u16 command; 150 volatile u32 link; /* void * */ 151 volatile u32 tx_desc_addr; /* Always points to the tx_buf_addr element. */ 152 volatile s32 count; 153 154 volatile u32 tx_buf_addr0; /* void *, frame to be transmitted. */ 155 volatile s32 tx_buf_size0; /* Length of Tx frame. */ 156 volatile u32 tx_buf_addr1; /* void *, frame to be transmitted. */ 157 volatile s32 tx_buf_size1; /* Length of Tx frame. */ 158 }; 159 160 #define TxCB_CMD_TRANSMIT 0x0004 /* transmit command */ 161 #define TxCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */ 162 #define TxCB_CMD_NC 0x0010 /* 0=CRC insert by controller */ 163 #define TxCB_CMD_I 0x2000 /* generate interrupt on completion */ 164 #define TxCB_CMD_S 0x4000 /* suspend on completion */ 165 #define TxCB_CMD_EL 0x8000 /* last command block in CBL */ 166 167 #define TxCB_COUNT_MASK 0x3fff 168 #define TxCB_COUNT_EOF 0x8000 169 170 /* The Speedo3 Rx and Tx frame/buffer descriptors. 171 */ 172 struct descriptor { /* A generic descriptor. */ 173 volatile u16 status; 174 volatile u16 command; 175 volatile u32 link; /* struct descriptor * */ 176 177 unsigned char params[0]; 178 }; 179 180 #define CONFIG_SYS_CMD_EL 0x8000 181 #define CONFIG_SYS_CMD_SUSPEND 0x4000 182 #define CONFIG_SYS_CMD_INT 0x2000 183 #define CONFIG_SYS_CMD_IAS 0x0001 /* individual address setup */ 184 #define CONFIG_SYS_CMD_CONFIGURE 0x0002 /* configure */ 185 186 #define CONFIG_SYS_STATUS_C 0x8000 187 #define CONFIG_SYS_STATUS_OK 0x2000 188 189 /* Misc. 190 */ 191 #define NUM_RX_DESC PKTBUFSRX 192 #define NUM_TX_DESC 1 /* Number of TX descriptors */ 193 194 #define TOUT_LOOP 1000000 195 196 #define ETH_ALEN 6 197 198 static struct RxFD rx_ring[NUM_RX_DESC]; /* RX descriptor ring */ 199 static struct TxFD tx_ring[NUM_TX_DESC]; /* TX descriptor ring */ 200 static int rx_next; /* RX descriptor ring pointer */ 201 static int tx_next; /* TX descriptor ring pointer */ 202 static int tx_threshold; 203 204 /* 205 * The parameters for a CmdConfigure operation. 206 * There are so many options that it would be difficult to document 207 * each bit. We mostly use the default or recommended settings. 208 */ 209 static const char i82558_config_cmd[] = { 210 22, 0x08, 0, 1, 0, 0, 0x22, 0x03, 1, /* 1=Use MII 0=Use AUI */ 211 0, 0x2E, 0, 0x60, 0x08, 0x88, 212 0x68, 0, 0x40, 0xf2, 0x84, /* Disable FC */ 213 0x31, 0x05, 214 }; 215 216 static void init_rx_ring (struct eth_device *dev); 217 static void purge_tx_ring (struct eth_device *dev); 218 219 static void read_hw_addr (struct eth_device *dev, bd_t * bis); 220 221 static int eepro100_init (struct eth_device *dev, bd_t * bis); 222 static int eepro100_send(struct eth_device *dev, void *packet, int length); 223 static int eepro100_recv (struct eth_device *dev); 224 static void eepro100_halt (struct eth_device *dev); 225 226 #if defined(CONFIG_E500) 227 #define bus_to_phys(a) (a) 228 #define phys_to_bus(a) (a) 229 #else 230 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a) 231 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) 232 #endif 233 234 static inline int INW (struct eth_device *dev, u_long addr) 235 { 236 return le16_to_cpu(*(volatile u16 *)(addr + (u_long)dev->iobase)); 237 } 238 239 static inline void OUTW (struct eth_device *dev, int command, u_long addr) 240 { 241 *(volatile u16 *)((addr + (u_long)dev->iobase)) = cpu_to_le16(command); 242 } 243 244 static inline void OUTL (struct eth_device *dev, int command, u_long addr) 245 { 246 *(volatile u32 *)((addr + (u_long)dev->iobase)) = cpu_to_le32(command); 247 } 248 249 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 250 static inline int INL (struct eth_device *dev, u_long addr) 251 { 252 return le32_to_cpu(*(volatile u32 *)(addr + (u_long)dev->iobase)); 253 } 254 255 static int get_phyreg (struct eth_device *dev, unsigned char addr, 256 unsigned char reg, unsigned short *value) 257 { 258 int cmd; 259 int timeout = 50; 260 261 /* read requested data */ 262 cmd = (2 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16); 263 OUTL (dev, cmd, SCBCtrlMDI); 264 265 do { 266 udelay(1000); 267 cmd = INL (dev, SCBCtrlMDI); 268 } while (!(cmd & (1 << 28)) && (--timeout)); 269 270 if (timeout == 0) 271 return -1; 272 273 *value = (unsigned short) (cmd & 0xffff); 274 275 return 0; 276 } 277 278 static int set_phyreg (struct eth_device *dev, unsigned char addr, 279 unsigned char reg, unsigned short value) 280 { 281 int cmd; 282 int timeout = 50; 283 284 /* write requested data */ 285 cmd = (1 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16); 286 OUTL (dev, cmd | value, SCBCtrlMDI); 287 288 while (!(INL (dev, SCBCtrlMDI) & (1 << 28)) && (--timeout)) 289 udelay(1000); 290 291 if (timeout == 0) 292 return -1; 293 294 return 0; 295 } 296 297 /* Check if given phyaddr is valid, i.e. there is a PHY connected. 298 * Do this by checking model value field from ID2 register. 299 */ 300 static struct eth_device* verify_phyaddr (const char *devname, 301 unsigned char addr) 302 { 303 struct eth_device *dev; 304 unsigned short value; 305 unsigned char model; 306 307 dev = eth_get_dev_by_name(devname); 308 if (dev == NULL) { 309 printf("%s: no such device\n", devname); 310 return NULL; 311 } 312 313 /* read id2 register */ 314 if (get_phyreg(dev, addr, MII_PHYSID2, &value) != 0) { 315 printf("%s: mii read timeout!\n", devname); 316 return NULL; 317 } 318 319 /* get model */ 320 model = (unsigned char)((value >> 4) & 0x003f); 321 322 if (model == 0) { 323 printf("%s: no PHY at address %d\n", devname, addr); 324 return NULL; 325 } 326 327 return dev; 328 } 329 330 static int eepro100_miiphy_read(struct mii_dev *bus, int addr, int devad, 331 int reg) 332 { 333 unsigned short value = 0; 334 struct eth_device *dev; 335 336 dev = verify_phyaddr(bus->name, addr); 337 if (dev == NULL) 338 return -1; 339 340 if (get_phyreg(dev, addr, reg, &value) != 0) { 341 printf("%s: mii read timeout!\n", bus->name); 342 return -1; 343 } 344 345 return value; 346 } 347 348 static int eepro100_miiphy_write(struct mii_dev *bus, int addr, int devad, 349 int reg, u16 value) 350 { 351 struct eth_device *dev; 352 353 dev = verify_phyaddr(bus->name, addr); 354 if (dev == NULL) 355 return -1; 356 357 if (set_phyreg(dev, addr, reg, value) != 0) { 358 printf("%s: mii write timeout!\n", bus->name); 359 return -1; 360 } 361 362 return 0; 363 } 364 365 #endif 366 367 /* Wait for the chip get the command. 368 */ 369 static int wait_for_eepro100 (struct eth_device *dev) 370 { 371 int i; 372 373 for (i = 0; INW (dev, SCBCmd) & (CU_CMD_MASK | RU_CMD_MASK); i++) { 374 if (i >= TOUT_LOOP) { 375 return 0; 376 } 377 } 378 379 return 1; 380 } 381 382 static struct pci_device_id supported[] = { 383 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557}, 384 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559}, 385 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER}, 386 {} 387 }; 388 389 int eepro100_initialize (bd_t * bis) 390 { 391 pci_dev_t devno; 392 int card_number = 0; 393 struct eth_device *dev; 394 u32 iobase, status; 395 int idx = 0; 396 397 while (1) { 398 /* Find PCI device 399 */ 400 if ((devno = pci_find_devices (supported, idx++)) < 0) { 401 break; 402 } 403 404 pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase); 405 iobase &= ~0xf; 406 407 #ifdef DEBUG 408 printf ("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n", 409 iobase); 410 #endif 411 412 pci_write_config_dword (devno, 413 PCI_COMMAND, 414 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 415 416 /* Check if I/O accesses and Bus Mastering are enabled. 417 */ 418 pci_read_config_dword (devno, PCI_COMMAND, &status); 419 if (!(status & PCI_COMMAND_MEMORY)) { 420 printf ("Error: Can not enable MEM access.\n"); 421 continue; 422 } 423 424 if (!(status & PCI_COMMAND_MASTER)) { 425 printf ("Error: Can not enable Bus Mastering.\n"); 426 continue; 427 } 428 429 dev = (struct eth_device *) malloc (sizeof *dev); 430 if (!dev) { 431 printf("eepro100: Can not allocate memory\n"); 432 break; 433 } 434 memset(dev, 0, sizeof(*dev)); 435 436 sprintf (dev->name, "i82559#%d", card_number); 437 dev->priv = (void *) devno; /* this have to come before bus_to_phys() */ 438 dev->iobase = bus_to_phys (iobase); 439 dev->init = eepro100_init; 440 dev->halt = eepro100_halt; 441 dev->send = eepro100_send; 442 dev->recv = eepro100_recv; 443 444 eth_register (dev); 445 446 #if defined (CONFIG_MII) || defined(CONFIG_CMD_MII) 447 /* register mii command access routines */ 448 int retval; 449 struct mii_dev *mdiodev = mdio_alloc(); 450 if (!mdiodev) 451 return -ENOMEM; 452 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); 453 mdiodev->read = eepro100_miiphy_read; 454 mdiodev->write = eepro100_miiphy_write; 455 456 retval = mdio_register(mdiodev); 457 if (retval < 0) 458 return retval; 459 #endif 460 461 card_number++; 462 463 /* Set the latency timer for value. 464 */ 465 pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20); 466 467 udelay (10 * 1000); 468 469 read_hw_addr (dev, bis); 470 } 471 472 return card_number; 473 } 474 475 476 static int eepro100_init (struct eth_device *dev, bd_t * bis) 477 { 478 int i, status = -1; 479 int tx_cur; 480 struct descriptor *ias_cmd, *cfg_cmd; 481 482 /* Reset the ethernet controller 483 */ 484 OUTL (dev, I82559_SELECTIVE_RESET, SCBPort); 485 udelay (20); 486 487 OUTL (dev, I82559_RESET, SCBPort); 488 udelay (20); 489 490 if (!wait_for_eepro100 (dev)) { 491 printf ("Error: Can not reset ethernet controller.\n"); 492 goto Done; 493 } 494 OUTL (dev, 0, SCBPointer); 495 OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd); 496 497 if (!wait_for_eepro100 (dev)) { 498 printf ("Error: Can not reset ethernet controller.\n"); 499 goto Done; 500 } 501 OUTL (dev, 0, SCBPointer); 502 OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd); 503 504 /* Initialize Rx and Tx rings. 505 */ 506 init_rx_ring (dev); 507 purge_tx_ring (dev); 508 509 /* Tell the adapter where the RX ring is located. 510 */ 511 if (!wait_for_eepro100 (dev)) { 512 printf ("Error: Can not reset ethernet controller.\n"); 513 goto Done; 514 } 515 516 OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer); 517 OUTW (dev, SCB_M | RUC_START, SCBCmd); 518 519 /* Send the Configure frame */ 520 tx_cur = tx_next; 521 tx_next = ((tx_next + 1) % NUM_TX_DESC); 522 523 cfg_cmd = (struct descriptor *) &tx_ring[tx_cur]; 524 cfg_cmd->command = cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND | CONFIG_SYS_CMD_CONFIGURE)); 525 cfg_cmd->status = 0; 526 cfg_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next])); 527 528 memcpy (cfg_cmd->params, i82558_config_cmd, 529 sizeof (i82558_config_cmd)); 530 531 if (!wait_for_eepro100 (dev)) { 532 printf ("Error---CONFIG_SYS_CMD_CONFIGURE: Can not reset ethernet controller.\n"); 533 goto Done; 534 } 535 536 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer); 537 OUTW (dev, SCB_M | CU_START, SCBCmd); 538 539 for (i = 0; 540 !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C); 541 i++) { 542 if (i >= TOUT_LOOP) { 543 printf ("%s: Tx error buffer not ready\n", dev->name); 544 goto Done; 545 } 546 } 547 548 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) { 549 printf ("TX error status = 0x%08X\n", 550 le16_to_cpu (tx_ring[tx_cur].status)); 551 goto Done; 552 } 553 554 /* Send the Individual Address Setup frame 555 */ 556 tx_cur = tx_next; 557 tx_next = ((tx_next + 1) % NUM_TX_DESC); 558 559 ias_cmd = (struct descriptor *) &tx_ring[tx_cur]; 560 ias_cmd->command = cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND | CONFIG_SYS_CMD_IAS)); 561 ias_cmd->status = 0; 562 ias_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next])); 563 564 memcpy (ias_cmd->params, dev->enetaddr, 6); 565 566 /* Tell the adapter where the TX ring is located. 567 */ 568 if (!wait_for_eepro100 (dev)) { 569 printf ("Error: Can not reset ethernet controller.\n"); 570 goto Done; 571 } 572 573 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer); 574 OUTW (dev, SCB_M | CU_START, SCBCmd); 575 576 for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C); 577 i++) { 578 if (i >= TOUT_LOOP) { 579 printf ("%s: Tx error buffer not ready\n", 580 dev->name); 581 goto Done; 582 } 583 } 584 585 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) { 586 printf ("TX error status = 0x%08X\n", 587 le16_to_cpu (tx_ring[tx_cur].status)); 588 goto Done; 589 } 590 591 status = 0; 592 593 Done: 594 return status; 595 } 596 597 static int eepro100_send(struct eth_device *dev, void *packet, int length) 598 { 599 int i, status = -1; 600 int tx_cur; 601 602 if (length <= 0) { 603 printf ("%s: bad packet size: %d\n", dev->name, length); 604 goto Done; 605 } 606 607 tx_cur = tx_next; 608 tx_next = (tx_next + 1) % NUM_TX_DESC; 609 610 tx_ring[tx_cur].command = cpu_to_le16 ( TxCB_CMD_TRANSMIT | 611 TxCB_CMD_SF | 612 TxCB_CMD_S | 613 TxCB_CMD_EL ); 614 tx_ring[tx_cur].status = 0; 615 tx_ring[tx_cur].count = cpu_to_le32 (tx_threshold); 616 tx_ring[tx_cur].link = 617 cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next])); 618 tx_ring[tx_cur].tx_desc_addr = 619 cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_cur].tx_buf_addr0)); 620 tx_ring[tx_cur].tx_buf_addr0 = 621 cpu_to_le32 (phys_to_bus ((u_long) packet)); 622 tx_ring[tx_cur].tx_buf_size0 = cpu_to_le32 (length); 623 624 if (!wait_for_eepro100 (dev)) { 625 printf ("%s: Tx error ethernet controller not ready.\n", 626 dev->name); 627 goto Done; 628 } 629 630 /* Send the packet. 631 */ 632 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer); 633 OUTW (dev, SCB_M | CU_START, SCBCmd); 634 635 for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C); 636 i++) { 637 if (i >= TOUT_LOOP) { 638 printf ("%s: Tx error buffer not ready\n", dev->name); 639 goto Done; 640 } 641 } 642 643 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) { 644 printf ("TX error status = 0x%08X\n", 645 le16_to_cpu (tx_ring[tx_cur].status)); 646 goto Done; 647 } 648 649 status = length; 650 651 Done: 652 return status; 653 } 654 655 static int eepro100_recv (struct eth_device *dev) 656 { 657 u16 status, stat; 658 int rx_prev, length = 0; 659 660 stat = INW (dev, SCBStatus); 661 OUTW (dev, stat & SCB_STATUS_RNR, SCBStatus); 662 663 for (;;) { 664 status = le16_to_cpu (rx_ring[rx_next].status); 665 666 if (!(status & RFD_STATUS_C)) { 667 break; 668 } 669 670 /* Valid frame status. 671 */ 672 if ((status & RFD_STATUS_OK)) { 673 /* A valid frame received. 674 */ 675 length = le32_to_cpu (rx_ring[rx_next].count) & 0x3fff; 676 677 /* Pass the packet up to the protocol 678 * layers. 679 */ 680 net_process_received_packet((u8 *)rx_ring[rx_next].data, 681 length); 682 } else { 683 /* There was an error. 684 */ 685 printf ("RX error status = 0x%08X\n", status); 686 } 687 688 rx_ring[rx_next].control = cpu_to_le16 (RFD_CONTROL_S); 689 rx_ring[rx_next].status = 0; 690 rx_ring[rx_next].count = cpu_to_le32 (PKTSIZE_ALIGN << 16); 691 692 rx_prev = (rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC; 693 rx_ring[rx_prev].control = 0; 694 695 /* Update entry information. 696 */ 697 rx_next = (rx_next + 1) % NUM_RX_DESC; 698 } 699 700 if (stat & SCB_STATUS_RNR) { 701 702 printf ("%s: Receiver is not ready, restart it !\n", dev->name); 703 704 /* Reinitialize Rx ring. 705 */ 706 init_rx_ring (dev); 707 708 if (!wait_for_eepro100 (dev)) { 709 printf ("Error: Can not restart ethernet controller.\n"); 710 goto Done; 711 } 712 713 OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer); 714 OUTW (dev, SCB_M | RUC_START, SCBCmd); 715 } 716 717 Done: 718 return length; 719 } 720 721 static void eepro100_halt (struct eth_device *dev) 722 { 723 /* Reset the ethernet controller 724 */ 725 OUTL (dev, I82559_SELECTIVE_RESET, SCBPort); 726 udelay (20); 727 728 OUTL (dev, I82559_RESET, SCBPort); 729 udelay (20); 730 731 if (!wait_for_eepro100 (dev)) { 732 printf ("Error: Can not reset ethernet controller.\n"); 733 goto Done; 734 } 735 OUTL (dev, 0, SCBPointer); 736 OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd); 737 738 if (!wait_for_eepro100 (dev)) { 739 printf ("Error: Can not reset ethernet controller.\n"); 740 goto Done; 741 } 742 OUTL (dev, 0, SCBPointer); 743 OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd); 744 745 Done: 746 return; 747 } 748 749 /* SROM Read. 750 */ 751 static int read_eeprom (struct eth_device *dev, int location, int addr_len) 752 { 753 unsigned short retval = 0; 754 int read_cmd = location | EE_READ_CMD; 755 int i; 756 757 OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom); 758 OUTW (dev, EE_ENB, SCBeeprom); 759 760 /* Shift the read command bits out. */ 761 for (i = 12; i >= 0; i--) { 762 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 763 764 OUTW (dev, EE_ENB | dataval, SCBeeprom); 765 udelay (1); 766 OUTW (dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); 767 udelay (1); 768 } 769 OUTW (dev, EE_ENB, SCBeeprom); 770 771 for (i = 15; i >= 0; i--) { 772 OUTW (dev, EE_ENB | EE_SHIFT_CLK, SCBeeprom); 773 udelay (1); 774 retval = (retval << 1) | 775 ((INW (dev, SCBeeprom) & EE_DATA_READ) ? 1 : 0); 776 OUTW (dev, EE_ENB, SCBeeprom); 777 udelay (1); 778 } 779 780 /* Terminate the EEPROM access. */ 781 OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom); 782 return retval; 783 } 784 785 #ifdef CONFIG_EEPRO100_SROM_WRITE 786 int eepro100_write_eeprom (struct eth_device* dev, int location, int addr_len, unsigned short data) 787 { 788 unsigned short dataval; 789 int enable_cmd = 0x3f | EE_EWENB_CMD; 790 int write_cmd = location | EE_WRITE_CMD; 791 int i; 792 unsigned long datalong, tmplong; 793 794 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); 795 udelay(1); 796 OUTW(dev, EE_ENB, SCBeeprom); 797 798 /* Shift the enable command bits out. */ 799 for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--) 800 { 801 dataval = (enable_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 802 OUTW(dev, EE_ENB | dataval, SCBeeprom); 803 udelay(1); 804 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); 805 udelay(1); 806 } 807 808 OUTW(dev, EE_ENB, SCBeeprom); 809 udelay(1); 810 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); 811 udelay(1); 812 OUTW(dev, EE_ENB, SCBeeprom); 813 814 815 /* Shift the write command bits out. */ 816 for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--) 817 { 818 dataval = (write_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 819 OUTW(dev, EE_ENB | dataval, SCBeeprom); 820 udelay(1); 821 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); 822 udelay(1); 823 } 824 825 /* Write the data */ 826 datalong= (unsigned long) ((((data) & 0x00ff) << 8) | ( (data) >> 8)); 827 828 for (i = 0; i< EE_DATA_BITS; i++) 829 { 830 /* Extract and move data bit to bit DI */ 831 dataval = ((datalong & 0x8000)>>13) ? EE_DATA_WRITE : 0; 832 833 OUTW(dev, EE_ENB | dataval, SCBeeprom); 834 udelay(1); 835 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); 836 udelay(1); 837 OUTW(dev, EE_ENB | dataval, SCBeeprom); 838 udelay(1); 839 840 datalong = datalong << 1; /* Adjust significant data bit*/ 841 } 842 843 /* Finish up command (toggle CS) */ 844 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); 845 udelay(1); /* delay for more than 250 ns */ 846 OUTW(dev, EE_ENB, SCBeeprom); 847 848 /* Wait for programming ready (D0 = 1) */ 849 tmplong = 10; 850 do 851 { 852 dataval = INW(dev, SCBeeprom); 853 if (dataval & EE_DATA_READ) 854 break; 855 udelay(10000); 856 } 857 while (-- tmplong); 858 859 if (tmplong == 0) 860 { 861 printf ("Write i82559 eeprom timed out (100 ms waiting for data ready.\n"); 862 return -1; 863 } 864 865 /* Terminate the EEPROM access. */ 866 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); 867 868 return 0; 869 } 870 #endif 871 872 static void init_rx_ring (struct eth_device *dev) 873 { 874 int i; 875 876 for (i = 0; i < NUM_RX_DESC; i++) { 877 rx_ring[i].status = 0; 878 rx_ring[i].control = 879 (i == NUM_RX_DESC - 1) ? cpu_to_le16 (RFD_CONTROL_S) : 0; 880 rx_ring[i].link = 881 cpu_to_le32 (phys_to_bus 882 ((u32) & rx_ring[(i + 1) % NUM_RX_DESC])); 883 rx_ring[i].rx_buf_addr = 0xffffffff; 884 rx_ring[i].count = cpu_to_le32 (PKTSIZE_ALIGN << 16); 885 } 886 887 rx_next = 0; 888 } 889 890 static void purge_tx_ring (struct eth_device *dev) 891 { 892 int i; 893 894 tx_next = 0; 895 tx_threshold = 0x01208000; 896 897 for (i = 0; i < NUM_TX_DESC; i++) { 898 tx_ring[i].status = 0; 899 tx_ring[i].command = 0; 900 tx_ring[i].link = 0; 901 tx_ring[i].tx_desc_addr = 0; 902 tx_ring[i].count = 0; 903 904 tx_ring[i].tx_buf_addr0 = 0; 905 tx_ring[i].tx_buf_size0 = 0; 906 tx_ring[i].tx_buf_addr1 = 0; 907 tx_ring[i].tx_buf_size1 = 0; 908 } 909 } 910 911 static void read_hw_addr (struct eth_device *dev, bd_t * bis) 912 { 913 u16 sum = 0; 914 int i, j; 915 int addr_len = read_eeprom (dev, 0, 6) == 0xffff ? 8 : 6; 916 917 for (j = 0, i = 0; i < 0x40; i++) { 918 u16 value = read_eeprom (dev, i, addr_len); 919 920 sum += value; 921 if (i < 3) { 922 dev->enetaddr[j++] = value; 923 dev->enetaddr[j++] = value >> 8; 924 } 925 } 926 927 if (sum != 0xBABA) { 928 memset (dev->enetaddr, 0, ETH_ALEN); 929 #ifdef DEBUG 930 printf ("%s: Invalid EEPROM checksum %#4.4x, " 931 "check settings before activating this device!\n", 932 dev->name, sum); 933 #endif 934 } 935 } 936