1 /* 2 * (C) Copyright 2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <malloc.h> 26 #include <net.h> 27 #include <netdev.h> 28 #include <asm/io.h> 29 #include <pci.h> 30 #include <miiphy.h> 31 32 #undef DEBUG 33 34 /* Ethernet chip registers. 35 */ 36 #define SCBStatus 0 /* Rx/Command Unit Status *Word* */ 37 #define SCBIntAckByte 1 /* Rx/Command Unit STAT/ACK byte */ 38 #define SCBCmd 2 /* Rx/Command Unit Command *Word* */ 39 #define SCBIntrCtlByte 3 /* Rx/Command Unit Intr.Control Byte */ 40 #define SCBPointer 4 /* General purpose pointer. */ 41 #define SCBPort 8 /* Misc. commands and operands. */ 42 #define SCBflash 12 /* Flash memory control. */ 43 #define SCBeeprom 14 /* EEPROM memory control. */ 44 #define SCBCtrlMDI 16 /* MDI interface control. */ 45 #define SCBEarlyRx 20 /* Early receive byte count. */ 46 #define SCBGenControl 28 /* 82559 General Control Register */ 47 #define SCBGenStatus 29 /* 82559 General Status register */ 48 49 /* 82559 SCB status word defnitions 50 */ 51 #define SCB_STATUS_CX 0x8000 /* CU finished command (transmit) */ 52 #define SCB_STATUS_FR 0x4000 /* frame received */ 53 #define SCB_STATUS_CNA 0x2000 /* CU left active state */ 54 #define SCB_STATUS_RNR 0x1000 /* receiver left ready state */ 55 #define SCB_STATUS_MDI 0x0800 /* MDI read/write cycle done */ 56 #define SCB_STATUS_SWI 0x0400 /* software generated interrupt */ 57 #define SCB_STATUS_FCP 0x0100 /* flow control pause interrupt */ 58 59 #define SCB_INTACK_MASK 0xFD00 /* all the above */ 60 61 #define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA) 62 #define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR) 63 64 /* System control block commands 65 */ 66 /* CU Commands */ 67 #define CU_NOP 0x0000 68 #define CU_START 0x0010 69 #define CU_RESUME 0x0020 70 #define CU_STATSADDR 0x0040 /* Load Dump Statistics ctrs addr */ 71 #define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */ 72 #define CU_ADDR_LOAD 0x0060 /* Base address to add to CU commands */ 73 #define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */ 74 75 /* RUC Commands */ 76 #define RUC_NOP 0x0000 77 #define RUC_START 0x0001 78 #define RUC_RESUME 0x0002 79 #define RUC_ABORT 0x0004 80 #define RUC_ADDR_LOAD 0x0006 /* (seems not to clear on acceptance) */ 81 #define RUC_RESUMENR 0x0007 82 83 #define CU_CMD_MASK 0x00f0 84 #define RU_CMD_MASK 0x0007 85 86 #define SCB_M 0x0100 /* 0 = enable interrupt, 1 = disable */ 87 #define SCB_SWI 0x0200 /* 1 - cause device to interrupt */ 88 89 #define CU_STATUS_MASK 0x00C0 90 #define RU_STATUS_MASK 0x003C 91 92 #define RU_STATUS_IDLE (0<<2) 93 #define RU_STATUS_SUS (1<<2) 94 #define RU_STATUS_NORES (2<<2) 95 #define RU_STATUS_READY (4<<2) 96 #define RU_STATUS_NO_RBDS_SUS ((1<<2)|(8<<2)) 97 #define RU_STATUS_NO_RBDS_NORES ((2<<2)|(8<<2)) 98 #define RU_STATUS_NO_RBDS_READY ((4<<2)|(8<<2)) 99 100 /* 82559 Port interface commands. 101 */ 102 #define I82559_RESET 0x00000000 /* Software reset */ 103 #define I82559_SELFTEST 0x00000001 /* 82559 Selftest command */ 104 #define I82559_SELECTIVE_RESET 0x00000002 105 #define I82559_DUMP 0x00000003 106 #define I82559_DUMP_WAKEUP 0x00000007 107 108 /* 82559 Eeprom interface. 109 */ 110 #define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */ 111 #define EE_CS 0x02 /* EEPROM chip select. */ 112 #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ 113 #define EE_WRITE_0 0x01 114 #define EE_WRITE_1 0x05 115 #define EE_DATA_READ 0x08 /* EEPROM chip data out. */ 116 #define EE_ENB (0x4800 | EE_CS) 117 #define EE_CMD_BITS 3 118 #define EE_DATA_BITS 16 119 120 /* The EEPROM commands include the alway-set leading bit. 121 */ 122 #define EE_EWENB_CMD (4 << addr_len) 123 #define EE_WRITE_CMD (5 << addr_len) 124 #define EE_READ_CMD (6 << addr_len) 125 #define EE_ERASE_CMD (7 << addr_len) 126 127 /* Receive frame descriptors. 128 */ 129 struct RxFD { 130 volatile u16 status; 131 volatile u16 control; 132 volatile u32 link; /* struct RxFD * */ 133 volatile u32 rx_buf_addr; /* void * */ 134 volatile u32 count; 135 136 volatile u8 data[PKTSIZE_ALIGN]; 137 }; 138 139 #define RFD_STATUS_C 0x8000 /* completion of received frame */ 140 #define RFD_STATUS_OK 0x2000 /* frame received with no errors */ 141 142 #define RFD_CONTROL_EL 0x8000 /* 1=last RFD in RFA */ 143 #define RFD_CONTROL_S 0x4000 /* 1=suspend RU after receiving frame */ 144 #define RFD_CONTROL_H 0x0010 /* 1=RFD is a header RFD */ 145 #define RFD_CONTROL_SF 0x0008 /* 0=simplified, 1=flexible mode */ 146 147 #define RFD_COUNT_MASK 0x3fff 148 #define RFD_COUNT_F 0x4000 149 #define RFD_COUNT_EOF 0x8000 150 151 #define RFD_RX_CRC 0x0800 /* crc error */ 152 #define RFD_RX_ALIGNMENT 0x0400 /* alignment error */ 153 #define RFD_RX_RESOURCE 0x0200 /* out of space, no resources */ 154 #define RFD_RX_DMA_OVER 0x0100 /* DMA overrun */ 155 #define RFD_RX_SHORT 0x0080 /* short frame error */ 156 #define RFD_RX_LENGTH 0x0020 157 #define RFD_RX_ERROR 0x0010 /* receive error */ 158 #define RFD_RX_NO_ADR_MATCH 0x0004 /* no address match */ 159 #define RFD_RX_IA_MATCH 0x0002 /* individual address does not match */ 160 #define RFD_RX_TCO 0x0001 /* TCO indication */ 161 162 /* Transmit frame descriptors 163 */ 164 struct TxFD { /* Transmit frame descriptor set. */ 165 volatile u16 status; 166 volatile u16 command; 167 volatile u32 link; /* void * */ 168 volatile u32 tx_desc_addr; /* Always points to the tx_buf_addr element. */ 169 volatile s32 count; 170 171 volatile u32 tx_buf_addr0; /* void *, frame to be transmitted. */ 172 volatile s32 tx_buf_size0; /* Length of Tx frame. */ 173 volatile u32 tx_buf_addr1; /* void *, frame to be transmitted. */ 174 volatile s32 tx_buf_size1; /* Length of Tx frame. */ 175 }; 176 177 #define TxCB_CMD_TRANSMIT 0x0004 /* transmit command */ 178 #define TxCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */ 179 #define TxCB_CMD_NC 0x0010 /* 0=CRC insert by controller */ 180 #define TxCB_CMD_I 0x2000 /* generate interrupt on completion */ 181 #define TxCB_CMD_S 0x4000 /* suspend on completion */ 182 #define TxCB_CMD_EL 0x8000 /* last command block in CBL */ 183 184 #define TxCB_COUNT_MASK 0x3fff 185 #define TxCB_COUNT_EOF 0x8000 186 187 /* The Speedo3 Rx and Tx frame/buffer descriptors. 188 */ 189 struct descriptor { /* A generic descriptor. */ 190 volatile u16 status; 191 volatile u16 command; 192 volatile u32 link; /* struct descriptor * */ 193 194 unsigned char params[0]; 195 }; 196 197 #define CONFIG_SYS_CMD_EL 0x8000 198 #define CONFIG_SYS_CMD_SUSPEND 0x4000 199 #define CONFIG_SYS_CMD_INT 0x2000 200 #define CONFIG_SYS_CMD_IAS 0x0001 /* individual address setup */ 201 #define CONFIG_SYS_CMD_CONFIGURE 0x0002 /* configure */ 202 203 #define CONFIG_SYS_STATUS_C 0x8000 204 #define CONFIG_SYS_STATUS_OK 0x2000 205 206 /* Misc. 207 */ 208 #define NUM_RX_DESC PKTBUFSRX 209 #define NUM_TX_DESC 1 /* Number of TX descriptors */ 210 211 #define TOUT_LOOP 1000000 212 213 #define ETH_ALEN 6 214 215 static struct RxFD rx_ring[NUM_RX_DESC]; /* RX descriptor ring */ 216 static struct TxFD tx_ring[NUM_TX_DESC]; /* TX descriptor ring */ 217 static int rx_next; /* RX descriptor ring pointer */ 218 static int tx_next; /* TX descriptor ring pointer */ 219 static int tx_threshold; 220 221 /* 222 * The parameters for a CmdConfigure operation. 223 * There are so many options that it would be difficult to document 224 * each bit. We mostly use the default or recommended settings. 225 */ 226 static const char i82557_config_cmd[] = { 227 22, 0x08, 0, 0, 0, 0, 0x32, 0x03, 1, /* 1=Use MII 0=Use AUI */ 228 0, 0x2E, 0, 0x60, 0, 229 0xf2, 0x48, 0, 0x40, 0xf2, 0x80, /* 0x40=Force full-duplex */ 230 0x3f, 0x05, 231 }; 232 static const char i82558_config_cmd[] = { 233 22, 0x08, 0, 1, 0, 0, 0x22, 0x03, 1, /* 1=Use MII 0=Use AUI */ 234 0, 0x2E, 0, 0x60, 0x08, 0x88, 235 0x68, 0, 0x40, 0xf2, 0x84, /* Disable FC */ 236 0x31, 0x05, 237 }; 238 239 static void init_rx_ring (struct eth_device *dev); 240 static void purge_tx_ring (struct eth_device *dev); 241 242 static void read_hw_addr (struct eth_device *dev, bd_t * bis); 243 244 static int eepro100_init (struct eth_device *dev, bd_t * bis); 245 static int eepro100_send (struct eth_device *dev, volatile void *packet, 246 int length); 247 static int eepro100_recv (struct eth_device *dev); 248 static void eepro100_halt (struct eth_device *dev); 249 250 #if defined(CONFIG_E500) || defined(CONFIG_DB64360) || defined(CONFIG_DB64460) 251 #define bus_to_phys(a) (a) 252 #define phys_to_bus(a) (a) 253 #else 254 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a) 255 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) 256 #endif 257 258 static inline int INW (struct eth_device *dev, u_long addr) 259 { 260 return le16_to_cpu (*(volatile u16 *) (addr + dev->iobase)); 261 } 262 263 static inline void OUTW (struct eth_device *dev, int command, u_long addr) 264 { 265 *(volatile u16 *) ((addr + dev->iobase)) = cpu_to_le16 (command); 266 } 267 268 static inline void OUTL (struct eth_device *dev, int command, u_long addr) 269 { 270 *(volatile u32 *) ((addr + dev->iobase)) = cpu_to_le32 (command); 271 } 272 273 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 274 static inline int INL (struct eth_device *dev, u_long addr) 275 { 276 return le32_to_cpu (*(volatile u32 *) (addr + dev->iobase)); 277 } 278 279 static int get_phyreg (struct eth_device *dev, unsigned char addr, 280 unsigned char reg, unsigned short *value) 281 { 282 int cmd; 283 int timeout = 50; 284 285 /* read requested data */ 286 cmd = (2 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16); 287 OUTL (dev, cmd, SCBCtrlMDI); 288 289 do { 290 udelay(1000); 291 cmd = INL (dev, SCBCtrlMDI); 292 } while (!(cmd & (1 << 28)) && (--timeout)); 293 294 if (timeout == 0) 295 return -1; 296 297 *value = (unsigned short) (cmd & 0xffff); 298 299 return 0; 300 } 301 302 static int set_phyreg (struct eth_device *dev, unsigned char addr, 303 unsigned char reg, unsigned short value) 304 { 305 int cmd; 306 int timeout = 50; 307 308 /* write requested data */ 309 cmd = (1 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16); 310 OUTL (dev, cmd | value, SCBCtrlMDI); 311 312 while (!(INL (dev, SCBCtrlMDI) & (1 << 28)) && (--timeout)) 313 udelay(1000); 314 315 if (timeout == 0) 316 return -1; 317 318 return 0; 319 } 320 321 /* Check if given phyaddr is valid, i.e. there is a PHY connected. 322 * Do this by checking model value field from ID2 register. 323 */ 324 static struct eth_device* verify_phyaddr (const char *devname, 325 unsigned char addr) 326 { 327 struct eth_device *dev; 328 unsigned short value; 329 unsigned char model; 330 331 dev = eth_get_dev_by_name(devname); 332 if (dev == NULL) { 333 printf("%s: no such device\n", devname); 334 return NULL; 335 } 336 337 /* read id2 register */ 338 if (get_phyreg(dev, addr, MII_PHYSID2, &value) != 0) { 339 printf("%s: mii read timeout!\n", devname); 340 return NULL; 341 } 342 343 /* get model */ 344 model = (unsigned char)((value >> 4) & 0x003f); 345 346 if (model == 0) { 347 printf("%s: no PHY at address %d\n", devname, addr); 348 return NULL; 349 } 350 351 return dev; 352 } 353 354 static int eepro100_miiphy_read(const char *devname, unsigned char addr, 355 unsigned char reg, unsigned short *value) 356 { 357 struct eth_device *dev; 358 359 dev = verify_phyaddr(devname, addr); 360 if (dev == NULL) 361 return -1; 362 363 if (get_phyreg(dev, addr, reg, value) != 0) { 364 printf("%s: mii read timeout!\n", devname); 365 return -1; 366 } 367 368 return 0; 369 } 370 371 static int eepro100_miiphy_write(const char *devname, unsigned char addr, 372 unsigned char reg, unsigned short value) 373 { 374 struct eth_device *dev; 375 376 dev = verify_phyaddr(devname, addr); 377 if (dev == NULL) 378 return -1; 379 380 if (set_phyreg(dev, addr, reg, value) != 0) { 381 printf("%s: mii write timeout!\n", devname); 382 return -1; 383 } 384 385 return 0; 386 } 387 388 #endif 389 390 /* Wait for the chip get the command. 391 */ 392 static int wait_for_eepro100 (struct eth_device *dev) 393 { 394 int i; 395 396 for (i = 0; INW (dev, SCBCmd) & (CU_CMD_MASK | RU_CMD_MASK); i++) { 397 if (i >= TOUT_LOOP) { 398 return 0; 399 } 400 } 401 402 return 1; 403 } 404 405 static struct pci_device_id supported[] = { 406 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557}, 407 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559}, 408 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER}, 409 {} 410 }; 411 412 int eepro100_initialize (bd_t * bis) 413 { 414 pci_dev_t devno; 415 int card_number = 0; 416 struct eth_device *dev; 417 u32 iobase, status; 418 int idx = 0; 419 420 while (1) { 421 /* Find PCI device 422 */ 423 if ((devno = pci_find_devices (supported, idx++)) < 0) { 424 break; 425 } 426 427 pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase); 428 iobase &= ~0xf; 429 430 #ifdef DEBUG 431 printf ("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n", 432 iobase); 433 #endif 434 435 pci_write_config_dword (devno, 436 PCI_COMMAND, 437 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 438 439 /* Check if I/O accesses and Bus Mastering are enabled. 440 */ 441 pci_read_config_dword (devno, PCI_COMMAND, &status); 442 if (!(status & PCI_COMMAND_MEMORY)) { 443 printf ("Error: Can not enable MEM access.\n"); 444 continue; 445 } 446 447 if (!(status & PCI_COMMAND_MASTER)) { 448 printf ("Error: Can not enable Bus Mastering.\n"); 449 continue; 450 } 451 452 dev = (struct eth_device *) malloc (sizeof *dev); 453 if (!dev) { 454 printf("eepro100: Can not allocate memory\n"); 455 break; 456 } 457 memset(dev, 0, sizeof(*dev)); 458 459 sprintf (dev->name, "i82559#%d", card_number); 460 dev->priv = (void *) devno; /* this have to come before bus_to_phys() */ 461 dev->iobase = bus_to_phys (iobase); 462 dev->init = eepro100_init; 463 dev->halt = eepro100_halt; 464 dev->send = eepro100_send; 465 dev->recv = eepro100_recv; 466 467 eth_register (dev); 468 469 #if defined (CONFIG_MII) || defined(CONFIG_CMD_MII) 470 /* register mii command access routines */ 471 miiphy_register(dev->name, 472 eepro100_miiphy_read, eepro100_miiphy_write); 473 #endif 474 475 card_number++; 476 477 /* Set the latency timer for value. 478 */ 479 pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20); 480 481 udelay (10 * 1000); 482 483 read_hw_addr (dev, bis); 484 } 485 486 return card_number; 487 } 488 489 490 static int eepro100_init (struct eth_device *dev, bd_t * bis) 491 { 492 int i, status = -1; 493 int tx_cur; 494 struct descriptor *ias_cmd, *cfg_cmd; 495 496 /* Reset the ethernet controller 497 */ 498 OUTL (dev, I82559_SELECTIVE_RESET, SCBPort); 499 udelay (20); 500 501 OUTL (dev, I82559_RESET, SCBPort); 502 udelay (20); 503 504 if (!wait_for_eepro100 (dev)) { 505 printf ("Error: Can not reset ethernet controller.\n"); 506 goto Done; 507 } 508 OUTL (dev, 0, SCBPointer); 509 OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd); 510 511 if (!wait_for_eepro100 (dev)) { 512 printf ("Error: Can not reset ethernet controller.\n"); 513 goto Done; 514 } 515 OUTL (dev, 0, SCBPointer); 516 OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd); 517 518 /* Initialize Rx and Tx rings. 519 */ 520 init_rx_ring (dev); 521 purge_tx_ring (dev); 522 523 /* Tell the adapter where the RX ring is located. 524 */ 525 if (!wait_for_eepro100 (dev)) { 526 printf ("Error: Can not reset ethernet controller.\n"); 527 goto Done; 528 } 529 530 OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer); 531 OUTW (dev, SCB_M | RUC_START, SCBCmd); 532 533 /* Send the Configure frame */ 534 tx_cur = tx_next; 535 tx_next = ((tx_next + 1) % NUM_TX_DESC); 536 537 cfg_cmd = (struct descriptor *) &tx_ring[tx_cur]; 538 cfg_cmd->command = cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND | CONFIG_SYS_CMD_CONFIGURE)); 539 cfg_cmd->status = 0; 540 cfg_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next])); 541 542 memcpy (cfg_cmd->params, i82558_config_cmd, 543 sizeof (i82558_config_cmd)); 544 545 if (!wait_for_eepro100 (dev)) { 546 printf ("Error---CONFIG_SYS_CMD_CONFIGURE: Can not reset ethernet controller.\n"); 547 goto Done; 548 } 549 550 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer); 551 OUTW (dev, SCB_M | CU_START, SCBCmd); 552 553 for (i = 0; 554 !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C); 555 i++) { 556 if (i >= TOUT_LOOP) { 557 printf ("%s: Tx error buffer not ready\n", dev->name); 558 goto Done; 559 } 560 } 561 562 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) { 563 printf ("TX error status = 0x%08X\n", 564 le16_to_cpu (tx_ring[tx_cur].status)); 565 goto Done; 566 } 567 568 /* Send the Individual Address Setup frame 569 */ 570 tx_cur = tx_next; 571 tx_next = ((tx_next + 1) % NUM_TX_DESC); 572 573 ias_cmd = (struct descriptor *) &tx_ring[tx_cur]; 574 ias_cmd->command = cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND | CONFIG_SYS_CMD_IAS)); 575 ias_cmd->status = 0; 576 ias_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next])); 577 578 memcpy (ias_cmd->params, dev->enetaddr, 6); 579 580 /* Tell the adapter where the TX ring is located. 581 */ 582 if (!wait_for_eepro100 (dev)) { 583 printf ("Error: Can not reset ethernet controller.\n"); 584 goto Done; 585 } 586 587 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer); 588 OUTW (dev, SCB_M | CU_START, SCBCmd); 589 590 for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C); 591 i++) { 592 if (i >= TOUT_LOOP) { 593 printf ("%s: Tx error buffer not ready\n", 594 dev->name); 595 goto Done; 596 } 597 } 598 599 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) { 600 printf ("TX error status = 0x%08X\n", 601 le16_to_cpu (tx_ring[tx_cur].status)); 602 goto Done; 603 } 604 605 status = 0; 606 607 Done: 608 return status; 609 } 610 611 static int eepro100_send (struct eth_device *dev, volatile void *packet, int length) 612 { 613 int i, status = -1; 614 int tx_cur; 615 616 if (length <= 0) { 617 printf ("%s: bad packet size: %d\n", dev->name, length); 618 goto Done; 619 } 620 621 tx_cur = tx_next; 622 tx_next = (tx_next + 1) % NUM_TX_DESC; 623 624 tx_ring[tx_cur].command = cpu_to_le16 ( TxCB_CMD_TRANSMIT | 625 TxCB_CMD_SF | 626 TxCB_CMD_S | 627 TxCB_CMD_EL ); 628 tx_ring[tx_cur].status = 0; 629 tx_ring[tx_cur].count = cpu_to_le32 (tx_threshold); 630 tx_ring[tx_cur].link = 631 cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next])); 632 tx_ring[tx_cur].tx_desc_addr = 633 cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_cur].tx_buf_addr0)); 634 tx_ring[tx_cur].tx_buf_addr0 = 635 cpu_to_le32 (phys_to_bus ((u_long) packet)); 636 tx_ring[tx_cur].tx_buf_size0 = cpu_to_le32 (length); 637 638 if (!wait_for_eepro100 (dev)) { 639 printf ("%s: Tx error ethernet controller not ready.\n", 640 dev->name); 641 goto Done; 642 } 643 644 /* Send the packet. 645 */ 646 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer); 647 OUTW (dev, SCB_M | CU_START, SCBCmd); 648 649 for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C); 650 i++) { 651 if (i >= TOUT_LOOP) { 652 printf ("%s: Tx error buffer not ready\n", dev->name); 653 goto Done; 654 } 655 } 656 657 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) { 658 printf ("TX error status = 0x%08X\n", 659 le16_to_cpu (tx_ring[tx_cur].status)); 660 goto Done; 661 } 662 663 status = length; 664 665 Done: 666 return status; 667 } 668 669 static int eepro100_recv (struct eth_device *dev) 670 { 671 u16 status, stat; 672 int rx_prev, length = 0; 673 674 stat = INW (dev, SCBStatus); 675 OUTW (dev, stat & SCB_STATUS_RNR, SCBStatus); 676 677 for (;;) { 678 status = le16_to_cpu (rx_ring[rx_next].status); 679 680 if (!(status & RFD_STATUS_C)) { 681 break; 682 } 683 684 /* Valid frame status. 685 */ 686 if ((status & RFD_STATUS_OK)) { 687 /* A valid frame received. 688 */ 689 length = le32_to_cpu (rx_ring[rx_next].count) & 0x3fff; 690 691 /* Pass the packet up to the protocol 692 * layers. 693 */ 694 NetReceive (rx_ring[rx_next].data, length); 695 } else { 696 /* There was an error. 697 */ 698 printf ("RX error status = 0x%08X\n", status); 699 } 700 701 rx_ring[rx_next].control = cpu_to_le16 (RFD_CONTROL_S); 702 rx_ring[rx_next].status = 0; 703 rx_ring[rx_next].count = cpu_to_le32 (PKTSIZE_ALIGN << 16); 704 705 rx_prev = (rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC; 706 rx_ring[rx_prev].control = 0; 707 708 /* Update entry information. 709 */ 710 rx_next = (rx_next + 1) % NUM_RX_DESC; 711 } 712 713 if (stat & SCB_STATUS_RNR) { 714 715 printf ("%s: Receiver is not ready, restart it !\n", dev->name); 716 717 /* Reinitialize Rx ring. 718 */ 719 init_rx_ring (dev); 720 721 if (!wait_for_eepro100 (dev)) { 722 printf ("Error: Can not restart ethernet controller.\n"); 723 goto Done; 724 } 725 726 OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer); 727 OUTW (dev, SCB_M | RUC_START, SCBCmd); 728 } 729 730 Done: 731 return length; 732 } 733 734 static void eepro100_halt (struct eth_device *dev) 735 { 736 /* Reset the ethernet controller 737 */ 738 OUTL (dev, I82559_SELECTIVE_RESET, SCBPort); 739 udelay (20); 740 741 OUTL (dev, I82559_RESET, SCBPort); 742 udelay (20); 743 744 if (!wait_for_eepro100 (dev)) { 745 printf ("Error: Can not reset ethernet controller.\n"); 746 goto Done; 747 } 748 OUTL (dev, 0, SCBPointer); 749 OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd); 750 751 if (!wait_for_eepro100 (dev)) { 752 printf ("Error: Can not reset ethernet controller.\n"); 753 goto Done; 754 } 755 OUTL (dev, 0, SCBPointer); 756 OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd); 757 758 Done: 759 return; 760 } 761 762 /* SROM Read. 763 */ 764 static int read_eeprom (struct eth_device *dev, int location, int addr_len) 765 { 766 unsigned short retval = 0; 767 int read_cmd = location | EE_READ_CMD; 768 int i; 769 770 OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom); 771 OUTW (dev, EE_ENB, SCBeeprom); 772 773 /* Shift the read command bits out. */ 774 for (i = 12; i >= 0; i--) { 775 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 776 777 OUTW (dev, EE_ENB | dataval, SCBeeprom); 778 udelay (1); 779 OUTW (dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); 780 udelay (1); 781 } 782 OUTW (dev, EE_ENB, SCBeeprom); 783 784 for (i = 15; i >= 0; i--) { 785 OUTW (dev, EE_ENB | EE_SHIFT_CLK, SCBeeprom); 786 udelay (1); 787 retval = (retval << 1) | 788 ((INW (dev, SCBeeprom) & EE_DATA_READ) ? 1 : 0); 789 OUTW (dev, EE_ENB, SCBeeprom); 790 udelay (1); 791 } 792 793 /* Terminate the EEPROM access. */ 794 OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom); 795 return retval; 796 } 797 798 #ifdef CONFIG_EEPRO100_SROM_WRITE 799 int eepro100_write_eeprom (struct eth_device* dev, int location, int addr_len, unsigned short data) 800 { 801 unsigned short dataval; 802 int enable_cmd = 0x3f | EE_EWENB_CMD; 803 int write_cmd = location | EE_WRITE_CMD; 804 int i; 805 unsigned long datalong, tmplong; 806 807 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); 808 udelay(1); 809 OUTW(dev, EE_ENB, SCBeeprom); 810 811 /* Shift the enable command bits out. */ 812 for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--) 813 { 814 dataval = (enable_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 815 OUTW(dev, EE_ENB | dataval, SCBeeprom); 816 udelay(1); 817 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); 818 udelay(1); 819 } 820 821 OUTW(dev, EE_ENB, SCBeeprom); 822 udelay(1); 823 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); 824 udelay(1); 825 OUTW(dev, EE_ENB, SCBeeprom); 826 827 828 /* Shift the write command bits out. */ 829 for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--) 830 { 831 dataval = (write_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 832 OUTW(dev, EE_ENB | dataval, SCBeeprom); 833 udelay(1); 834 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); 835 udelay(1); 836 } 837 838 /* Write the data */ 839 datalong= (unsigned long) ((((data) & 0x00ff) << 8) | ( (data) >> 8)); 840 841 for (i = 0; i< EE_DATA_BITS; i++) 842 { 843 /* Extract and move data bit to bit DI */ 844 dataval = ((datalong & 0x8000)>>13) ? EE_DATA_WRITE : 0; 845 846 OUTW(dev, EE_ENB | dataval, SCBeeprom); 847 udelay(1); 848 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); 849 udelay(1); 850 OUTW(dev, EE_ENB | dataval, SCBeeprom); 851 udelay(1); 852 853 datalong = datalong << 1; /* Adjust significant data bit*/ 854 } 855 856 /* Finish up command (toggle CS) */ 857 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); 858 udelay(1); /* delay for more than 250 ns */ 859 OUTW(dev, EE_ENB, SCBeeprom); 860 861 /* Wait for programming ready (D0 = 1) */ 862 tmplong = 10; 863 do 864 { 865 dataval = INW(dev, SCBeeprom); 866 if (dataval & EE_DATA_READ) 867 break; 868 udelay(10000); 869 } 870 while (-- tmplong); 871 872 if (tmplong == 0) 873 { 874 printf ("Write i82559 eeprom timed out (100 ms waiting for data ready.\n"); 875 return -1; 876 } 877 878 /* Terminate the EEPROM access. */ 879 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); 880 881 return 0; 882 } 883 #endif 884 885 static void init_rx_ring (struct eth_device *dev) 886 { 887 int i; 888 889 for (i = 0; i < NUM_RX_DESC; i++) { 890 rx_ring[i].status = 0; 891 rx_ring[i].control = 892 (i == NUM_RX_DESC - 1) ? cpu_to_le16 (RFD_CONTROL_S) : 0; 893 rx_ring[i].link = 894 cpu_to_le32 (phys_to_bus 895 ((u32) & rx_ring[(i + 1) % NUM_RX_DESC])); 896 rx_ring[i].rx_buf_addr = 0xffffffff; 897 rx_ring[i].count = cpu_to_le32 (PKTSIZE_ALIGN << 16); 898 } 899 900 rx_next = 0; 901 } 902 903 static void purge_tx_ring (struct eth_device *dev) 904 { 905 int i; 906 907 tx_next = 0; 908 tx_threshold = 0x01208000; 909 910 for (i = 0; i < NUM_TX_DESC; i++) { 911 tx_ring[i].status = 0; 912 tx_ring[i].command = 0; 913 tx_ring[i].link = 0; 914 tx_ring[i].tx_desc_addr = 0; 915 tx_ring[i].count = 0; 916 917 tx_ring[i].tx_buf_addr0 = 0; 918 tx_ring[i].tx_buf_size0 = 0; 919 tx_ring[i].tx_buf_addr1 = 0; 920 tx_ring[i].tx_buf_size1 = 0; 921 } 922 } 923 924 static void read_hw_addr (struct eth_device *dev, bd_t * bis) 925 { 926 u16 sum = 0; 927 int i, j; 928 int addr_len = read_eeprom (dev, 0, 6) == 0xffff ? 8 : 6; 929 930 for (j = 0, i = 0; i < 0x40; i++) { 931 u16 value = read_eeprom (dev, i, addr_len); 932 933 sum += value; 934 if (i < 3) { 935 dev->enetaddr[j++] = value; 936 dev->enetaddr[j++] = value >> 8; 937 } 938 } 939 940 if (sum != 0xBABA) { 941 memset (dev->enetaddr, 0, ETH_ALEN); 942 #ifdef DEBUG 943 printf ("%s: Invalid EEPROM checksum %#4.4x, " 944 "check settings before activating this device!\n", 945 dev->name, sum); 946 #endif 947 } 948 } 949